Intel Mainstone II (ARM) machine by Armin Kuster.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3736 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
bd9bdce694
commit
ef056e4398
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@ -496,7 +496,7 @@ VL_OBJS+= arm-semi.o
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VL_OBJS+= pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
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VL_OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o
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VL_OBJS+= pflash_cfi01.o gumstix.o
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VL_OBJS+= spitz.o ide.o serial.o nand.o ecc.o
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VL_OBJS+= spitz.o ide.o serial.o nand.o ecc.o mainstone.o
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VL_OBJS+= omap.o omap_lcdc.o omap1_clk.o omap_mmc.o omap_i2c.o
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VL_OBJS+= palm.o tsc210x.o
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CPPFLAGS += -DHAS_AUDIO
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@ -93,4 +93,7 @@ extern QEMUMachine mcf5208evb_machine;
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/* dummy_m68k.c */
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extern QEMUMachine dummy_m68k_machine;
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/* mainstone.c */
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extern QEMUMachine mainstone2_machine;
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#endif
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@ -0,0 +1,307 @@
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/*
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* PXA270-based Intel Mainstone platforms.
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*
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* Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
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* <akuster@mvista.com>
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*
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* Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#include "hw.h"
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#include "pxa.h"
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#include "arm-misc.h"
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#include "sysemu.h"
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#include "net.h"
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#include "devices.h"
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#include "boards.h"
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#define MST_ETH_PHYS 0x10000300
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#define MST_FPGA_PHYS 0x08000000
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/* Mainstone FPGA for extern irqs */
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#define FPGA_GPIO_PIN 0
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#define MST_NUM_IRQS 16
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#define MST_BASE MST_FPGA_PHYS
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#define MST_LEDDAT1 0x10
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#define MST_LEDDAT2 0x14
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#define MST_LEDCTRL 0x40
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#define MST_GPSWR 0x60
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#define MST_MSCWR1 0x80
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#define MST_MSCWR2 0x84
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#define MST_MSCWR3 0x88
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#define MST_MSCRD 0x90
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#define MST_INTMSKENA 0xc0
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#define MST_INTSETCLR 0xd0
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#define MST_PCMCIA0 0xe0
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#define MST_PCMCIA1 0xe4
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/* IRQ definitions */
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#define ETHERNET_IRQ 3
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typedef struct mst_irq_state {
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target_phys_addr_t target_base;
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qemu_irq *parent;
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qemu_irq *pins;
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uint32_t prev_level;
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uint32_t leddat1;
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uint32_t leddat2;
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uint32_t ledctrl;
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uint32_t gpswr;
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uint32_t mscwr1;
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uint32_t mscwr2;
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uint32_t mscwr3;
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uint32_t mscrd;
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uint32_t intmskena;
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uint32_t intsetclr;
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uint32_t pcmcia0;
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uint32_t pcmcia1;
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} mst_irq_state;
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static void
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mst_fpga_update_gpio(mst_irq_state *s)
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{
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uint32_t level, diff;
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int bit;
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level = s->prev_level ^ s->intsetclr;
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for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
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bit = ffs(diff) - 1;
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qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
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}
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s->prev_level = level;
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}
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static void
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mst_fpga_set_irq(void *opaque, int irq, int level)
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{
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mst_irq_state *s = (mst_irq_state *)opaque;
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if (level)
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s->prev_level |= 1u << irq;
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else
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s->prev_level &= ~(1u << irq);
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if(s->intmskena & (1u << irq)) {
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s->intsetclr = 1u << irq;
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qemu_set_irq(s->parent[0], level);
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}
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}
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static uint32_t
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mst_fpga_readb(void *opaque, target_phys_addr_t addr)
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{
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mst_irq_state *s = (mst_irq_state *) opaque;
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addr -= s->target_base;
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switch (addr) {
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case MST_LEDDAT1:
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return s->leddat1;
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case MST_LEDDAT2:
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return s->leddat2;
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case MST_LEDCTRL:
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return s->ledctrl;
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case MST_GPSWR:
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return s->gpswr;
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case MST_MSCWR1:
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return s->mscwr1;
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case MST_MSCWR2:
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return s->mscwr2;
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case MST_MSCWR3:
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return s->mscwr3;
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case MST_MSCRD:
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return s->mscrd;
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case MST_INTMSKENA:
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return s->intmskena;
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case MST_INTSETCLR:
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return s->intsetclr;
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case MST_PCMCIA0:
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return s->pcmcia0;
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case MST_PCMCIA1:
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return s->pcmcia1;
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default:
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printf("Mainstone - mst_fpga_readb: Bad register offset "
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REG_FMT " \n", addr);
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}
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return 0;
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}
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static void
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mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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mst_irq_state *s = (mst_irq_state *) opaque;
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addr -= s->target_base;
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value &= 0xffffffff;
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switch (addr) {
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case MST_LEDDAT1:
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s->leddat1 = value;
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break;
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case MST_LEDDAT2:
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s->leddat2 = value;
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break;
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case MST_LEDCTRL:
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s->ledctrl = value;
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break;
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case MST_GPSWR:
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s->gpswr = value;
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break;
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case MST_MSCWR1:
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s->mscwr1 = value;
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break;
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case MST_MSCWR2:
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s->mscwr2 = value;
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break;
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case MST_MSCWR3:
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s->mscwr3 = value;
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break;
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case MST_MSCRD:
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s->mscrd = value;
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break;
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case MST_INTMSKENA: /* Mask interupt */
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s->intmskena = (value & 0xFEEFF);
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mst_fpga_update_gpio(s);
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break;
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case MST_INTSETCLR: /* clear or set interrupt */
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s->intsetclr = (value & 0xFEEFF);
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break;
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case MST_PCMCIA0:
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s->pcmcia0 = value;
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break;
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case MST_PCMCIA1:
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s->pcmcia1 = value;
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break;
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default:
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printf("Mainstone - mst_fpga_writeb: Bad register offset "
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REG_FMT " \n", addr);
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}
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}
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CPUReadMemoryFunc *mst_fpga_readfn[] = {
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mst_fpga_readb,
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mst_fpga_readb,
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mst_fpga_readb,
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};
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CPUWriteMemoryFunc *mst_fpga_writefn[] = {
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mst_fpga_writeb,
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mst_fpga_writeb,
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mst_fpga_writeb,
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};
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static void
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mst_fpga_save(QEMUFile *f, void *opaque)
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{
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struct mst_irq_state *s = (mst_irq_state *) opaque;
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qemu_put_be32s(f, &s->prev_level);
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qemu_put_be32s(f, &s->leddat1);
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qemu_put_be32s(f, &s->leddat2);
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qemu_put_be32s(f, &s->ledctrl);
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qemu_put_be32s(f, &s->gpswr);
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qemu_put_be32s(f, &s->mscwr1);
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qemu_put_be32s(f, &s->mscwr2);
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qemu_put_be32s(f, &s->mscwr3);
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qemu_put_be32s(f, &s->mscrd);
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qemu_put_be32s(f, &s->intmskena);
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qemu_put_be32s(f, &s->intsetclr);
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qemu_put_be32s(f, &s->pcmcia0);
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qemu_put_be32s(f, &s->pcmcia1);
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}
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static int
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mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
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{
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mst_irq_state *s = (mst_irq_state *) opaque;
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qemu_get_be32s(f, &s->prev_level);
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qemu_get_be32s(f, &s->leddat1);
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qemu_get_be32s(f, &s->leddat2);
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qemu_get_be32s(f, &s->ledctrl);
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qemu_get_be32s(f, &s->gpswr);
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qemu_get_be32s(f, &s->mscwr1);
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qemu_get_be32s(f, &s->mscwr2);
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qemu_get_be32s(f, &s->mscwr3);
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qemu_get_be32s(f, &s->mscrd);
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qemu_get_be32s(f, &s->intmskena);
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qemu_get_be32s(f, &s->intsetclr);
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qemu_get_be32s(f, &s->pcmcia0);
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qemu_get_be32s(f, &s->pcmcia1);
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return 0;
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}
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static qemu_irq
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*mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq)
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{
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mst_irq_state *s;
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int iomemtype;
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qemu_irq *qi;
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s = (mst_irq_state *) qemu_mallocz(sizeof(mst_irq_state));
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if (!s)
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return NULL;
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s->target_base = base;
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s->parent = &cpu->pic[irq];
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/* alloc the external 16 irqs */
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qi = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
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s->pins = qi;
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iomemtype = cpu_register_io_memory(0, mst_fpga_readfn,
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mst_fpga_writefn, s);
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cpu_register_physical_memory(MST_BASE, 0x00100000, iomemtype);
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register_savevm("mainstone_fpga", 0, 0, mst_fpga_save, mst_fpga_load, s);
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return qi;
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}
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enum mainstone_model_e { mainstone };
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static void mainstone_common_init(int ram_size, int vga_ram_size,
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DisplayState *ds, const char *kernel_filename,
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const char *kernel_cmdline, const char *initrd_filename,
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const char *cpu_model, enum mainstone_model_e model, int arm_id)
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{
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uint32_t mainstone_ram = 0x04000000;
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uint32_t mainstone_rom = 0x00800000;
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struct pxa2xx_state_s *cpu;
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qemu_irq *mst_irq;
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if (!cpu_model)
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cpu_model = "pxa270-c5";
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/* Setup CPU & memory */
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if (ram_size < mainstone_ram + mainstone_rom + PXA2XX_INTERNAL_SIZE) {
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fprintf(stderr, "This platform requires %i bytes of memory\n",
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mainstone_ram + mainstone_rom + PXA2XX_INTERNAL_SIZE);
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exit(1);
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}
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cpu = pxa270_init(mainstone_ram, ds, cpu_model);
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cpu_register_physical_memory(0, mainstone_rom,
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qemu_ram_alloc(mainstone_rom) | IO_MEM_ROM);
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/* Setup initial (reset) machine state */
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cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
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mst_irq = mst_irq_init(cpu, MST_BASE, PXA2XX_PIC_GPIO_0);
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smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);
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arm_load_kernel(cpu->env, mainstone_ram, kernel_filename, kernel_cmdline,
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initrd_filename, arm_id, PXA2XX_SDRAM_BASE);
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}
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static void mainstone_init(int ram_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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mainstone_common_init(ram_size, vga_ram_size, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
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}
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QEMUMachine mainstone2_machine = {
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"mainstone",
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"Mainstone II (PXA27x)",
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mainstone_init,
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};
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1
vl.c
1
vl.c
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@ -7488,6 +7488,7 @@ static void register_machines(void)
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qemu_register_machine(&lm3s6965evb_machine);
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qemu_register_machine(&connex_machine);
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qemu_register_machine(&verdex_machine);
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qemu_register_machine(&mainstone2_machine);
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#elif defined(TARGET_SH4)
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qemu_register_machine(&shix_machine);
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qemu_register_machine(&r2d_machine);
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