target/arm: Implement SVE conditionally broadcast/extract element
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180613015641.5667-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
3ca879aeb3
commit
ef23cb726d
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@ -463,6 +463,8 @@ DEF_HELPER_FLAGS_4(sve_trn_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_compact_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_compact_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_2(sve_last_active_element, TCG_CALL_NO_RWG, s32, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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@ -430,6 +430,26 @@ TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
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# Note esz >= 2
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COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn
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# SVE conditionally broadcast element to vector
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CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm
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CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm
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# SVE conditionally copy element to SIMD&FP scalar
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CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn
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CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn
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# SVE conditionally copy element to general register
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CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn
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CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn
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# SVE copy element to SIMD&FP scalar register
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LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn
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LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
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# SVE copy element to general register
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LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
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LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
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### SVE Predicate Logical Operations Group
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# SVE predicate logical operations
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@ -2070,3 +2070,15 @@ void HELPER(sve_compact_d)(void *vd, void *vn, void *vg, uint32_t desc)
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d[j] = 0;
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}
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}
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/* Similar to the ARM LastActiveElement pseudocode function, except the
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* result is multiplied by the element size. This includes the not found
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* indication; e.g. not found for esz=3 is -8.
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*/
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int32_t HELPER(sve_last_active_element)(void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
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return last_active_element(vg, DIV_ROUND_UP(oprsz, 8), esz);
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}
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@ -2296,6 +2296,334 @@ static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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return do_zpz_ool(s, a, fns[a->esz]);
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}
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/* Call the helper that computes the ARM LastActiveElement pseudocode
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* function, scaled by the element size. This includes the not found
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* indication; e.g. not found for esz=3 is -8.
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*/
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static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg)
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{
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/* Predicate sizes may be smaller and cannot use simd_desc. We cannot
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* round up, as we do elsewhere, because we need the exact size.
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*/
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TCGv_ptr t_p = tcg_temp_new_ptr();
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TCGv_i32 t_desc;
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unsigned vsz = pred_full_reg_size(s);
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unsigned desc;
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desc = vsz - 2;
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desc = deposit32(desc, SIMD_DATA_SHIFT, 2, esz);
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tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg));
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t_desc = tcg_const_i32(desc);
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gen_helper_sve_last_active_element(ret, t_p, t_desc);
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tcg_temp_free_i32(t_desc);
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tcg_temp_free_ptr(t_p);
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}
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/* Increment LAST to the offset of the next element in the vector,
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* wrapping around to 0.
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*/
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static void incr_last_active(DisasContext *s, TCGv_i32 last, int esz)
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{
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unsigned vsz = vec_full_reg_size(s);
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tcg_gen_addi_i32(last, last, 1 << esz);
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if (is_power_of_2(vsz)) {
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tcg_gen_andi_i32(last, last, vsz - 1);
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} else {
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TCGv_i32 max = tcg_const_i32(vsz);
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TCGv_i32 zero = tcg_const_i32(0);
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tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last);
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tcg_temp_free_i32(max);
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tcg_temp_free_i32(zero);
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}
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}
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/* If LAST < 0, set LAST to the offset of the last element in the vector. */
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static void wrap_last_active(DisasContext *s, TCGv_i32 last, int esz)
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{
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unsigned vsz = vec_full_reg_size(s);
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if (is_power_of_2(vsz)) {
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tcg_gen_andi_i32(last, last, vsz - 1);
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} else {
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TCGv_i32 max = tcg_const_i32(vsz - (1 << esz));
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TCGv_i32 zero = tcg_const_i32(0);
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tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last);
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tcg_temp_free_i32(max);
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tcg_temp_free_i32(zero);
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}
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}
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/* Load an unsigned element of ESZ from BASE+OFS. */
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static TCGv_i64 load_esz(TCGv_ptr base, int ofs, int esz)
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{
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TCGv_i64 r = tcg_temp_new_i64();
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switch (esz) {
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case 0:
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tcg_gen_ld8u_i64(r, base, ofs);
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break;
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case 1:
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tcg_gen_ld16u_i64(r, base, ofs);
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break;
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case 2:
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tcg_gen_ld32u_i64(r, base, ofs);
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break;
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case 3:
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tcg_gen_ld_i64(r, base, ofs);
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break;
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default:
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g_assert_not_reached();
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}
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return r;
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}
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/* Load an unsigned element of ESZ from RM[LAST]. */
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static TCGv_i64 load_last_active(DisasContext *s, TCGv_i32 last,
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int rm, int esz)
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{
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TCGv_ptr p = tcg_temp_new_ptr();
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TCGv_i64 r;
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/* Convert offset into vector into offset into ENV.
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* The final adjustment for the vector register base
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* is added via constant offset to the load.
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*/
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#ifdef HOST_WORDS_BIGENDIAN
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/* Adjust for element ordering. See vec_reg_offset. */
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if (esz < 3) {
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tcg_gen_xori_i32(last, last, 8 - (1 << esz));
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}
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#endif
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tcg_gen_ext_i32_ptr(p, last);
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tcg_gen_add_ptr(p, p, cpu_env);
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r = load_esz(p, vec_full_reg_offset(s, rm), esz);
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tcg_temp_free_ptr(p);
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return r;
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}
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/* Compute CLAST for a Zreg. */
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static bool do_clast_vector(DisasContext *s, arg_rprr_esz *a, bool before)
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{
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TCGv_i32 last;
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TCGLabel *over;
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TCGv_i64 ele;
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unsigned vsz, esz = a->esz;
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if (!sve_access_check(s)) {
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return true;
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}
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last = tcg_temp_local_new_i32();
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over = gen_new_label();
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find_last_active(s, last, esz, a->pg);
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/* There is of course no movcond for a 2048-bit vector,
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* so we must branch over the actual store.
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*/
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tcg_gen_brcondi_i32(TCG_COND_LT, last, 0, over);
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if (!before) {
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incr_last_active(s, last, esz);
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}
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ele = load_last_active(s, last, a->rm, esz);
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tcg_temp_free_i32(last);
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vsz = vec_full_reg_size(s);
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tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), vsz, vsz, ele);
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tcg_temp_free_i64(ele);
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/* If this insn used MOVPRFX, we may need a second move. */
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if (a->rd != a->rn) {
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TCGLabel *done = gen_new_label();
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tcg_gen_br(done);
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gen_set_label(over);
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do_mov_z(s, a->rd, a->rn);
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gen_set_label(done);
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} else {
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gen_set_label(over);
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}
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return true;
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}
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static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
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{
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return do_clast_vector(s, a, false);
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}
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static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
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{
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return do_clast_vector(s, a, true);
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}
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/* Compute CLAST for a scalar. */
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static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
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bool before, TCGv_i64 reg_val)
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{
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TCGv_i32 last = tcg_temp_new_i32();
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TCGv_i64 ele, cmp, zero;
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find_last_active(s, last, esz, pg);
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/* Extend the original value of last prior to incrementing. */
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cmp = tcg_temp_new_i64();
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tcg_gen_ext_i32_i64(cmp, last);
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if (!before) {
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incr_last_active(s, last, esz);
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}
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/* The conceit here is that while last < 0 indicates not found, after
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* adjusting for cpu_env->vfp.zregs[rm], it is still a valid address
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* from which we can load garbage. We then discard the garbage with
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* a conditional move.
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*/
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ele = load_last_active(s, last, rm, esz);
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tcg_temp_free_i32(last);
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zero = tcg_const_i64(0);
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tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, zero, ele, reg_val);
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tcg_temp_free_i64(zero);
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tcg_temp_free_i64(cmp);
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tcg_temp_free_i64(ele);
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}
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/* Compute CLAST for a Vreg. */
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static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before)
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{
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if (sve_access_check(s)) {
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int esz = a->esz;
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int ofs = vec_reg_offset(s, a->rd, 0, esz);
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TCGv_i64 reg = load_esz(cpu_env, ofs, esz);
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do_clast_scalar(s, esz, a->pg, a->rn, before, reg);
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write_fp_dreg(s, a->rd, reg);
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tcg_temp_free_i64(reg);
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}
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return true;
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}
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static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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return do_clast_fp(s, a, false);
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}
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static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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return do_clast_fp(s, a, true);
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}
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/* Compute CLAST for a Xreg. */
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static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before)
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{
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TCGv_i64 reg;
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if (!sve_access_check(s)) {
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return true;
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}
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reg = cpu_reg(s, a->rd);
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switch (a->esz) {
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case 0:
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tcg_gen_ext8u_i64(reg, reg);
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break;
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case 1:
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tcg_gen_ext16u_i64(reg, reg);
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break;
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case 2:
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tcg_gen_ext32u_i64(reg, reg);
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break;
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case 3:
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break;
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default:
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g_assert_not_reached();
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}
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do_clast_scalar(s, a->esz, a->pg, a->rn, before, reg);
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return true;
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}
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static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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return do_clast_general(s, a, false);
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}
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static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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return do_clast_general(s, a, true);
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}
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/* Compute LAST for a scalar. */
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static TCGv_i64 do_last_scalar(DisasContext *s, int esz,
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int pg, int rm, bool before)
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{
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TCGv_i32 last = tcg_temp_new_i32();
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TCGv_i64 ret;
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find_last_active(s, last, esz, pg);
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if (before) {
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wrap_last_active(s, last, esz);
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} else {
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incr_last_active(s, last, esz);
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}
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ret = load_last_active(s, last, rm, esz);
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tcg_temp_free_i32(last);
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return ret;
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}
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/* Compute LAST for a Vreg. */
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static bool do_last_fp(DisasContext *s, arg_rpr_esz *a, bool before)
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{
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if (sve_access_check(s)) {
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TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before);
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write_fp_dreg(s, a->rd, val);
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tcg_temp_free_i64(val);
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}
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return true;
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}
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static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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return do_last_fp(s, a, false);
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}
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static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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return do_last_fp(s, a, true);
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}
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/* Compute LAST for a Xreg. */
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static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before)
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{
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if (sve_access_check(s)) {
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TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before);
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tcg_gen_mov_i64(cpu_reg(s, a->rd), val);
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tcg_temp_free_i64(val);
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}
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return true;
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}
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static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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return do_last_general(s, a, false);
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}
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static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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return do_last_general(s, a, true);
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}
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/*
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*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
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*/
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