Updates to decodetree.py for risc-v.
-----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJb2d23AAoJEGTfOOivfiFfNcoH/1cc/fSj7O9TkaWi1SPSDuDh FzO19HHjM0ZqdUc5tRg47YKDaYpMsE1+py73YW81P5vyp8KXqGohRii8l2SoGHXX uUMgXnoSg+i2G5YFzLYMlEuTS73FP2/sD+9bXcDrdJ7c2+/qiYN2KfmWWUAIxQSw WX6BRDhBSq+GGJfhKsIf8QVNtsOs7TnGfDisWMh6t0BLKho3Fqx6XwMTltfKZbEq xLcw3FK4EpP9gQxl2GViK/YS2wo7HRC4zvugLIjRnFUusU7o4/Hpo6tUK+N6lgZd ZTULcWWrNuMTEs1YkpdNpEqcSrq7Gh6WCnJStPzxL3CTXunIdwM2VlbyvjOU+n0= =snc9 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20181031' into staging Updates to decodetree.py for risc-v. # gpg: Signature made Wed 31 Oct 2018 16:52:07 GMT # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-dt-20181031: decodetree: Allow multiple input files decodetree: Remove "insn" argument from trans_* expanders decodetree: Add !extern flag to argument sets Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
ef30274865
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@ -63,13 +63,16 @@
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#
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# *** Argument set syntax:
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#
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# args_def := '&' identifier ( args_elt )+
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# args_def := '&' identifier ( args_elt )+ ( !extern )?
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# args_elt := identifier
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#
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# Each args_elt defines an argument within the argument set.
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# Each argument set will be rendered as a C structure "arg_$name"
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# with each of the fields being one of the member arguments.
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#
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# If !extern is specified, the backing structure is assumed to
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# have been already declared, typically via a second decoder.
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#
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# Argument set examples:
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#
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# ®3 ra rb rc
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@ -167,19 +170,20 @@ input_file = ''
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output_file = None
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output_fd = None
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insntype = 'uint32_t'
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decode_function = 'decode'
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re_ident = '[a-zA-Z][a-zA-Z0-9_]*'
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def error(lineno, *args):
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def error_with_file(file, lineno, *args):
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"""Print an error message from file:line and args and exit."""
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global output_file
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global output_fd
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if lineno:
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r = '{0}:{1}: error:'.format(input_file, lineno)
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r = '{0}:{1}: error:'.format(file, lineno)
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elif input_file:
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r = '{0}: error:'.format(input_file)
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r = '{0}: error:'.format(file)
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else:
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r = 'error:'
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for a in args:
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@ -191,6 +195,8 @@ def error(lineno, *args):
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os.remove(output_file)
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exit(1)
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def error(lineno, *args):
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error_with_file(input_file, lineno, args)
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def output(*args):
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global output_fd
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@ -392,8 +398,9 @@ class FunctionField:
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class Arguments:
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"""Class representing the extracted fields of a format"""
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def __init__(self, nm, flds):
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def __init__(self, nm, flds, extern):
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self.name = nm
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self.extern = extern
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self.fields = sorted(flds)
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def __str__(self):
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@ -403,10 +410,11 @@ class Arguments:
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return 'arg_' + self.name
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def output_def(self):
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output('typedef struct {\n')
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for n in self.fields:
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output(' int ', n, ';\n')
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output('} ', self.struct_name(), ';\n\n')
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if not self.extern:
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output('typedef struct {\n')
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for n in self.fields:
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output(' int ', n, ';\n')
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output('} ', self.struct_name(), ';\n\n')
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# end Arguments
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@ -414,6 +422,7 @@ class General:
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"""Common code between instruction formats and instruction patterns"""
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def __init__(self, name, lineno, base, fixb, fixm, udfm, fldm, flds):
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self.name = name
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self.file = input_file
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self.lineno = lineno
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self.base = base
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self.fixedbits = fixb
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@ -460,20 +469,19 @@ class Pattern(General):
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output('typedef ', self.base.base.struct_name(),
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' arg_', self.name, ';\n')
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output(translate_scope, 'bool ', translate_prefix, '_', self.name,
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'(DisasContext *ctx, arg_', self.name,
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' *a, ', insntype, ' insn);\n')
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'(DisasContext *ctx, arg_', self.name, ' *a);\n')
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def output_code(self, i, extracted, outerbits, outermask):
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global translate_prefix
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ind = str_indent(i)
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arg = self.base.base.name
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output(ind, '/* line ', str(self.lineno), ' */\n')
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output(ind, '/* ', self.file, ':', str(self.lineno), ' */\n')
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if not extracted:
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output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);\n')
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for n, f in self.fields.items():
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output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n')
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output(ind, 'return ', translate_prefix, '_', self.name,
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'(ctx, &u.f_', arg, ', insn);\n')
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'(ctx, &u.f_', arg, ');\n')
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# end Pattern
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@ -540,7 +548,11 @@ def parse_arguments(lineno, name, toks):
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global re_ident
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flds = []
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extern = False
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for t in toks:
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if re_fullmatch('!extern', t):
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extern = True
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continue
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if not re_fullmatch(re_ident, t):
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error(lineno, 'invalid argument set token "{0}"'.format(t))
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if t in flds:
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@ -549,7 +561,7 @@ def parse_arguments(lineno, name, toks):
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if name in arguments:
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error(lineno, 'duplicate argument set', name)
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arguments[name] = Arguments(name, flds)
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arguments[name] = Arguments(name, flds, extern)
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# end parse_arguments
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@ -573,13 +585,14 @@ def add_field_byname(lineno, flds, new_name, old_name):
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def infer_argument_set(flds):
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global arguments
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global decode_function
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for arg in arguments.values():
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if eq_fields_for_args(flds, arg.fields):
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return arg
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name = str(len(arguments))
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arg = Arguments(name, flds.keys())
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name = decode_function + str(len(arguments))
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arg = Arguments(name, flds.keys(), False)
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arguments[name] = arg
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return arg
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@ -587,6 +600,7 @@ def infer_argument_set(flds):
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def infer_format(arg, fieldmask, flds):
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global arguments
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global formats
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global decode_function
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const_flds = {}
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var_flds = {}
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@ -606,7 +620,7 @@ def infer_format(arg, fieldmask, flds):
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continue
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return (fmt, const_flds)
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name = 'Fmt_' + str(len(formats))
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name = decode_function + '_Fmt_' + str(len(formats))
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if not arg:
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arg = infer_argument_set(flds)
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@ -909,8 +923,9 @@ def build_tree(pats, outerbits, outermask):
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if innermask == 0:
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pnames = []
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for p in pats:
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pnames.append(p.name + ':' + str(p.lineno))
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error(pats[0].lineno, 'overlapping patterns:', pnames)
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pnames.append(p.name + ':' + p.file + ':' + str(p.lineno))
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error_with_file(pats[0].file, pats[0].lineno,
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'overlapping patterns:', pnames)
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fullmask = outermask | innermask
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@ -971,8 +986,8 @@ def main():
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global insnwidth
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global insntype
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global insnmask
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global decode_function
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decode_function = 'decode'
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decode_scope = 'static '
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long_opts = ['decode=', 'translate=', 'output=', 'insnwidth=']
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@ -1001,10 +1016,11 @@ def main():
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if len(args) < 1:
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error(0, 'missing input file')
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input_file = args[0]
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f = open(input_file, 'r')
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parse_file(f)
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f.close()
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for filename in args:
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input_file = filename
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f = open(filename, 'r')
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parse_file(f)
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f.close()
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t = build_tree(patterns, 0, 0)
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prop_format(t)
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File diff suppressed because it is too large
Load Diff
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@ -51,12 +51,11 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *info)
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return 4;
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}
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#define INSN(opcode, format, ...) \
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static bool trans_l_##opcode(disassemble_info *info, \
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arg_l_##opcode *a, uint32_t insn) \
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{ \
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output("l." #opcode, format, ##__VA_ARGS__); \
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return true; \
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#define INSN(opcode, format, ...) \
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static bool trans_l_##opcode(disassemble_info *info, arg_l_##opcode *a) \
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{ \
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output("l." #opcode, format, ##__VA_ARGS__); \
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return true; \
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}
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INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b)
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@ -146,12 +145,12 @@ INSN(psync, "")
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INSN(csync, "")
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INSN(rfe, "")
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#define FP_INSN(opcode, suffix, format, ...) \
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static bool trans_lf_##opcode##_##suffix(disassemble_info *info, \
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arg_lf_##opcode##_##suffix *a, uint32_t insn) \
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{ \
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output("lf." #opcode "." #suffix, format, ##__VA_ARGS__); \
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return true; \
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#define FP_INSN(opcode, suffix, format, ...) \
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static bool trans_lf_##opcode##_##suffix(disassemble_info *info, \
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arg_lf_##opcode##_##suffix *a) \
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{ \
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output("lf." #opcode "." #suffix, format, ##__VA_ARGS__); \
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return true; \
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}
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FP_INSN(add, s, "r%d, r%d, r%d", a->d, a->a, a->b)
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@ -434,105 +434,105 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb)
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gen_ove_cy(dc);
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}
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static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_add(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
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}
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static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_addc(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
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}
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static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_sub(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
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}
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static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_and(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
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}
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static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_or(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
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}
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static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_xor(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
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}
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static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_sll(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
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}
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static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_srl(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
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}
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static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_sra(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
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}
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static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_ror(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
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}
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static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn)
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static bool trans_l_exths(DisasContext *dc, arg_da *a)
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{
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check_r0_write(a->d);
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tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]);
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return true;
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}
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static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn)
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static bool trans_l_extbs(DisasContext *dc, arg_da *a)
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{
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check_r0_write(a->d);
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tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]);
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return true;
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}
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static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn)
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static bool trans_l_exthz(DisasContext *dc, arg_da *a)
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{
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check_r0_write(a->d);
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tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]);
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return true;
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}
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static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn)
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static bool trans_l_extbz(DisasContext *dc, arg_da *a)
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{
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check_r0_write(a->d);
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tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]);
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return true;
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}
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static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
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{
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TCGv zero;
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@ -544,7 +544,7 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn)
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return true;
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}
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static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn)
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static bool trans_l_ff1(DisasContext *dc, arg_da *a)
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{
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check_r0_write(a->d);
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tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1);
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|
@ -552,7 +552,7 @@ static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn)
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return true;
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}
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static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn)
|
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static bool trans_l_fl1(DisasContext *dc, arg_da *a)
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{
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check_r0_write(a->d);
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tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS);
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|
@ -560,47 +560,47 @@ static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn)
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return true;
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}
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static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn)
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static bool trans_l_mul(DisasContext *dc, arg_dab *a)
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{
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check_r0_write(a->d);
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gen_mul(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
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return true;
|
||||
}
|
||||
|
||||
static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn)
|
||||
static bool trans_l_mulu(DisasContext *dc, arg_dab *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
gen_mulu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn)
|
||||
static bool trans_l_div(DisasContext *dc, arg_dab *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
gen_div(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn)
|
||||
static bool trans_l_divu(DisasContext *dc, arg_dab *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
gen_divu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_muld(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_l_muld(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
gen_muld(dc, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_muldu(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_l_muldu(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
gen_muldu(dc, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn)
|
||||
static bool trans_l_j(DisasContext *dc, arg_l_j *a)
|
||||
{
|
||||
target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
|
||||
|
||||
|
|
@ -610,7 +610,7 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_jal(DisasContext *dc, arg_l_jal *a, uint32_t insn)
|
||||
static bool trans_l_jal(DisasContext *dc, arg_l_jal *a)
|
||||
{
|
||||
target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
|
||||
target_ulong ret_pc = dc->base.pc_next + 8;
|
||||
|
|
@ -640,26 +640,26 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond)
|
|||
dc->delayed_branch = 2;
|
||||
}
|
||||
|
||||
static bool trans_l_bf(DisasContext *dc, arg_l_bf *a, uint32_t insn)
|
||||
static bool trans_l_bf(DisasContext *dc, arg_l_bf *a)
|
||||
{
|
||||
do_bf(dc, a, TCG_COND_NE);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a, uint32_t insn)
|
||||
static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a)
|
||||
{
|
||||
do_bf(dc, a, TCG_COND_EQ);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn)
|
||||
static bool trans_l_jr(DisasContext *dc, arg_l_jr *a)
|
||||
{
|
||||
tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]);
|
||||
dc->delayed_branch = 2;
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a, uint32_t insn)
|
||||
static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a)
|
||||
{
|
||||
tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]);
|
||||
tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8);
|
||||
|
|
@ -667,7 +667,7 @@ static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_lwa(DisasContext *dc, arg_load *a, uint32_t insn)
|
||||
static bool trans_l_lwa(DisasContext *dc, arg_load *a)
|
||||
{
|
||||
TCGv ea;
|
||||
|
||||
|
|
@ -692,43 +692,43 @@ static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop)
|
|||
tcg_temp_free(ea);
|
||||
}
|
||||
|
||||
static bool trans_l_lwz(DisasContext *dc, arg_load *a, uint32_t insn)
|
||||
static bool trans_l_lwz(DisasContext *dc, arg_load *a)
|
||||
{
|
||||
do_load(dc, a, MO_TEUL);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_lws(DisasContext *dc, arg_load *a, uint32_t insn)
|
||||
static bool trans_l_lws(DisasContext *dc, arg_load *a)
|
||||
{
|
||||
do_load(dc, a, MO_TESL);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_lbz(DisasContext *dc, arg_load *a, uint32_t insn)
|
||||
static bool trans_l_lbz(DisasContext *dc, arg_load *a)
|
||||
{
|
||||
do_load(dc, a, MO_UB);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_lbs(DisasContext *dc, arg_load *a, uint32_t insn)
|
||||
static bool trans_l_lbs(DisasContext *dc, arg_load *a)
|
||||
{
|
||||
do_load(dc, a, MO_SB);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_lhz(DisasContext *dc, arg_load *a, uint32_t insn)
|
||||
static bool trans_l_lhz(DisasContext *dc, arg_load *a)
|
||||
{
|
||||
do_load(dc, a, MO_TEUW);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_lhs(DisasContext *dc, arg_load *a, uint32_t insn)
|
||||
static bool trans_l_lhs(DisasContext *dc, arg_load *a)
|
||||
{
|
||||
do_load(dc, a, MO_TESW);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_swa(DisasContext *dc, arg_store *a, uint32_t insn)
|
||||
static bool trans_l_swa(DisasContext *dc, arg_store *a)
|
||||
{
|
||||
TCGv ea, val;
|
||||
TCGLabel *lab_fail, *lab_done;
|
||||
|
|
@ -771,30 +771,30 @@ static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop)
|
|||
tcg_temp_free(t0);
|
||||
}
|
||||
|
||||
static bool trans_l_sw(DisasContext *dc, arg_store *a, uint32_t insn)
|
||||
static bool trans_l_sw(DisasContext *dc, arg_store *a)
|
||||
{
|
||||
do_store(dc, a, MO_TEUL);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sb(DisasContext *dc, arg_store *a, uint32_t insn)
|
||||
static bool trans_l_sb(DisasContext *dc, arg_store *a)
|
||||
{
|
||||
do_store(dc, a, MO_UB);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sh(DisasContext *dc, arg_store *a, uint32_t insn)
|
||||
static bool trans_l_sh(DisasContext *dc, arg_store *a)
|
||||
{
|
||||
do_store(dc, a, MO_TEUW);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_nop(DisasContext *dc, arg_l_nop *a, uint32_t insn)
|
||||
static bool trans_l_nop(DisasContext *dc, arg_l_nop *a)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_addi(DisasContext *dc, arg_rri *a, uint32_t insn)
|
||||
static bool trans_l_addi(DisasContext *dc, arg_rri *a)
|
||||
{
|
||||
TCGv t0;
|
||||
|
||||
|
|
@ -805,7 +805,7 @@ static bool trans_l_addi(DisasContext *dc, arg_rri *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_addic(DisasContext *dc, arg_rri *a, uint32_t insn)
|
||||
static bool trans_l_addic(DisasContext *dc, arg_rri *a)
|
||||
{
|
||||
TCGv t0;
|
||||
|
||||
|
|
@ -816,7 +816,7 @@ static bool trans_l_addic(DisasContext *dc, arg_rri *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_muli(DisasContext *dc, arg_rri *a, uint32_t insn)
|
||||
static bool trans_l_muli(DisasContext *dc, arg_rri *a)
|
||||
{
|
||||
TCGv t0;
|
||||
|
||||
|
|
@ -827,7 +827,7 @@ static bool trans_l_muli(DisasContext *dc, arg_rri *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn)
|
||||
static bool trans_l_maci(DisasContext *dc, arg_l_maci *a)
|
||||
{
|
||||
TCGv t0;
|
||||
|
||||
|
|
@ -837,28 +837,28 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn)
|
||||
static bool trans_l_andi(DisasContext *dc, arg_rrk *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn)
|
||||
static bool trans_l_ori(DisasContext *dc, arg_rrk *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn)
|
||||
static bool trans_l_xori(DisasContext *dc, arg_rri *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn)
|
||||
static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
|
||||
|
|
@ -873,7 +873,7 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
|
||||
static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a)
|
||||
{
|
||||
if (is_user(dc)) {
|
||||
gen_illegal_exception(dc);
|
||||
|
|
@ -901,66 +901,66 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_mac(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_l_mac(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
gen_mac(dc, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_msb(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_l_msb(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
gen_msb(dc, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_macu(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_l_macu(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
gen_macu(dc, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_l_msbu(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn)
|
||||
static bool trans_l_slli(DisasContext *dc, arg_dal *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn)
|
||||
static bool trans_l_srli(DisasContext *dc, arg_dal *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn)
|
||||
static bool trans_l_srai(DisasContext *dc, arg_dal *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn)
|
||||
static bool trans_l_rori(DisasContext *dc, arg_dal *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn)
|
||||
static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
tcg_gen_movi_tl(cpu_R[a->d], a->k << 16);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn)
|
||||
static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac);
|
||||
|
|
@ -968,127 +968,127 @@ static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfeq(DisasContext *dc, arg_ab *a, TCGCond cond)
|
||||
static bool trans_l_sfeq(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfne(DisasContext *dc, arg_ab *a, TCGCond cond)
|
||||
static bool trans_l_sfne(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a, TCGCond cond)
|
||||
static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a, TCGCond cond)
|
||||
static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfltu(DisasContext *dc, arg_ab *a, TCGCond cond)
|
||||
static bool trans_l_sfltu(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfleu(DisasContext *dc, arg_ab *a, TCGCond cond)
|
||||
static bool trans_l_sfleu(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfgts(DisasContext *dc, arg_ab *a, TCGCond cond)
|
||||
static bool trans_l_sfgts(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfges(DisasContext *dc, arg_ab *a, TCGCond cond)
|
||||
static bool trans_l_sfges(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sflts(DisasContext *dc, arg_ab *a, TCGCond cond)
|
||||
static bool trans_l_sflts(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond)
|
||||
static bool trans_l_sfles(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a, TCGCond cond)
|
||||
static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a)
|
||||
{
|
||||
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfnei(DisasContext *dc, arg_ai *a, TCGCond cond)
|
||||
static bool trans_l_sfnei(DisasContext *dc, arg_ai *a)
|
||||
{
|
||||
tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a, TCGCond cond)
|
||||
static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a)
|
||||
{
|
||||
tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a, TCGCond cond)
|
||||
static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a)
|
||||
{
|
||||
tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfltui(DisasContext *dc, arg_ai *a, TCGCond cond)
|
||||
static bool trans_l_sfltui(DisasContext *dc, arg_ai *a)
|
||||
{
|
||||
tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfleui(DisasContext *dc, arg_ai *a, TCGCond cond)
|
||||
static bool trans_l_sfleui(DisasContext *dc, arg_ai *a)
|
||||
{
|
||||
tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a, TCGCond cond)
|
||||
static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a)
|
||||
{
|
||||
tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a, TCGCond cond)
|
||||
static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a)
|
||||
{
|
||||
tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a, TCGCond cond)
|
||||
static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a)
|
||||
{
|
||||
tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sflesi(DisasContext *dc, arg_ai *a, TCGCond cond)
|
||||
static bool trans_l_sflesi(DisasContext *dc, arg_ai *a)
|
||||
{
|
||||
tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn)
|
||||
static bool trans_l_sys(DisasContext *dc, arg_l_sys *a)
|
||||
{
|
||||
tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
|
||||
gen_exception(dc, EXCP_SYSCALL);
|
||||
|
|
@ -1096,7 +1096,7 @@ static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn)
|
||||
static bool trans_l_trap(DisasContext *dc, arg_l_trap *a)
|
||||
{
|
||||
tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
|
||||
gen_exception(dc, EXCP_TRAP);
|
||||
|
|
@ -1104,23 +1104,23 @@ static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn)
|
||||
static bool trans_l_msync(DisasContext *dc, arg_l_msync *a)
|
||||
{
|
||||
tcg_gen_mb(TCG_MO_ALL);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn)
|
||||
static bool trans_l_psync(DisasContext *dc, arg_l_psync *a)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn)
|
||||
static bool trans_l_csync(DisasContext *dc, arg_l_csync *a)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn)
|
||||
static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a)
|
||||
{
|
||||
if (is_user(dc)) {
|
||||
gen_illegal_exception(dc);
|
||||
|
|
@ -1162,49 +1162,49 @@ static void do_fpcmp(DisasContext *dc, arg_ab *a,
|
|||
gen_helper_update_fpcsr(cpu_env);
|
||||
}
|
||||
|
||||
static bool trans_lf_add_s(DisasContext *dc, arg_dab *a, uint32_t insn)
|
||||
static bool trans_lf_add_s(DisasContext *dc, arg_dab *a)
|
||||
{
|
||||
do_fp3(dc, a, gen_helper_float_add_s);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a, uint32_t insn)
|
||||
static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a)
|
||||
{
|
||||
do_fp3(dc, a, gen_helper_float_sub_s);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a, uint32_t insn)
|
||||
static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a)
|
||||
{
|
||||
do_fp3(dc, a, gen_helper_float_mul_s);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_div_s(DisasContext *dc, arg_dab *a, uint32_t insn)
|
||||
static bool trans_lf_div_s(DisasContext *dc, arg_dab *a)
|
||||
{
|
||||
do_fp3(dc, a, gen_helper_float_div_s);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a, uint32_t insn)
|
||||
static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a)
|
||||
{
|
||||
do_fp3(dc, a, gen_helper_float_rem_s);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_itof_s(DisasContext *dc, arg_da *a, uint32_t insn)
|
||||
static bool trans_lf_itof_s(DisasContext *dc, arg_da *a)
|
||||
{
|
||||
do_fp2(dc, a, gen_helper_itofs);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a, uint32_t insn)
|
||||
static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a)
|
||||
{
|
||||
do_fp2(dc, a, gen_helper_ftois);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn)
|
||||
static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a)
|
||||
{
|
||||
check_r0_write(a->d);
|
||||
gen_helper_float_madd_s(cpu_R[a->d], cpu_env, cpu_R[a->d],
|
||||
|
|
@ -1213,37 +1213,37 @@ static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
do_fpcmp(dc, a, gen_helper_float_eq_s, false, false);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
do_fpcmp(dc, a, gen_helper_float_eq_s, true, false);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
do_fpcmp(dc, a, gen_helper_float_lt_s, false, true);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
do_fpcmp(dc, a, gen_helper_float_le_s, false, true);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
do_fpcmp(dc, a, gen_helper_float_lt_s, false, false);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn)
|
||||
static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a)
|
||||
{
|
||||
do_fpcmp(dc, a, gen_helper_float_le_s, false, false);
|
||||
return true;
|
||||
|
|
|
|||
Loading…
Reference in New Issue