From ef3f5b9e7f83262e1eaea884b0a562b9fa73859c Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Sat, 15 Apr 2017 07:25:32 +0900 Subject: [PATCH] target/openrisc: add numcores and coreid support These are used to identify the processor in SMP system. Their definition has been defined in verilog cores but it not yet part of the spec but it will be soon. The proposal for this is available: https://openrisc.io/proposals/core-identifier-and-number-of-cores Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/sys_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 6ba816249b..e13666bea0 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -233,6 +233,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ return env->esr; + case TO_SPR(0, 128): /* COREID */ + return 0; + + case TO_SPR(0, 129): /* NUMCORES */ + return 1; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr;