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target/riscv: Add the virtulisation mode 

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Alistair Francis 2020-01-31 17:01:51 -08:00 committed by Palmer Dabbelt
parent 205377f894
commit ef6bb7b626
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GPG Key ID: 2E1319F35FBB1889
3 changed files with 25 additions and 0 deletions
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4
target/riscv/cpu.h
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@ -117,6 +117,8 @@ struct CPURISCVState {
#ifndef CONFIG_USER_ONLY
target_ulong priv;
/* This contains QEMU specific information about the virt state. */
target_ulong virt;
target_ulong resetvec;
target_ulong mhartid;
@ -269,6 +271,8 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,

3
target/riscv/cpu_bits.h
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@ -430,6 +430,9 @@
#define PRV_H 2 /* Reserved */
#define PRV_M 3
/* Virtulisation Register Fields */
#define VIRT_ONOFF 1
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7fc00000

18
target/riscv/cpu_helper.c
View File

@ -82,6 +82,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
bool riscv_cpu_virt_enabled(CPURISCVState *env)
{
if (!riscv_has_ext(env, RVH)) {
return false;
}
return get_field(env->virt, VIRT_ONOFF);
}
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
{
if (!riscv_has_ext(env, RVH)) {
return;
}
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
}
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;