target/riscv: Add the virtulisation mode
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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@ -117,6 +117,8 @@ struct CPURISCVState {
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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target_ulong priv;
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target_ulong priv;
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/* This contains QEMU specific information about the virt state. */
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target_ulong virt;
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target_ulong resetvec;
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target_ulong resetvec;
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target_ulong mhartid;
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target_ulong mhartid;
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@ -269,6 +271,8 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
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bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
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bool riscv_cpu_fp_enabled(CPURISCVState *env);
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bool riscv_cpu_fp_enabled(CPURISCVState *env);
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bool riscv_cpu_virt_enabled(CPURISCVState *env);
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void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
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int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
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int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
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hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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@ -430,6 +430,9 @@
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#define PRV_H 2 /* Reserved */
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#define PRV_H 2 /* Reserved */
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#define PRV_M 3
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#define PRV_M 3
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/* Virtulisation Register Fields */
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#define VIRT_ONOFF 1
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/* RV32 satp CSR field masks */
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/* RV32 satp CSR field masks */
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#define SATP32_MODE 0x80000000
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#define SATP32_MODE 0x80000000
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#define SATP32_ASID 0x7fc00000
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#define SATP32_ASID 0x7fc00000
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@ -82,6 +82,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
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return false;
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return false;
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}
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}
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bool riscv_cpu_virt_enabled(CPURISCVState *env)
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{
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if (!riscv_has_ext(env, RVH)) {
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return false;
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}
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return get_field(env->virt, VIRT_ONOFF);
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}
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void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
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{
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if (!riscv_has_ext(env, RVH)) {
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return;
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}
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env->virt = set_field(env->virt, VIRT_ONOFF, enable);
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}
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int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
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int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
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{
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{
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CPURISCVState *env = &cpu->env;
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CPURISCVState *env = &cpu->env;
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