qtest/libqos: add a function to initialize secondary PCI buses
Scan the PCI devices to find bridge and set PCI_SECONDARY_BUS and PCI_SUBORDINATE_BUS (algorithm from seabios) Signed-off-by: Laurent Vivier <lvivier@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20211208130350.10178-2-lvivier@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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@ -138,6 +138,7 @@ typedef struct PCIBridgeQemuCap {
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uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */
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uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */
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} PCIBridgeQemuCap;
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} PCIBridgeQemuCap;
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#define REDHAT_PCI_CAP_TYPE_OFFSET 3
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#define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
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#define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
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/*
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/*
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@ -152,6 +153,13 @@ typedef struct PCIResReserve {
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uint64_t mem_pref_64;
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uint64_t mem_pref_64;
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} PCIResReserve;
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} PCIResReserve;
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#define REDHAT_PCI_CAP_RES_RESERVE_BUS_RES 4
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#define REDHAT_PCI_CAP_RES_RESERVE_IO 8
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#define REDHAT_PCI_CAP_RES_RESERVE_MEM 16
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#define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_32 20
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#define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_64 24
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#define REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE 32
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int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
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int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
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PCIResReserve res_reserve, Error **errp);
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PCIResReserve res_reserve, Error **errp);
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@ -13,6 +13,8 @@
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "pci.h"
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#include "pci.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_regs.h"
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#include "hw/pci/pci_regs.h"
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#include "qemu/host-utils.h"
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#include "qemu/host-utils.h"
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#include "qgraph.h"
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#include "qgraph.h"
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@ -99,6 +101,123 @@ void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr)
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g_assert(!addr->device_id || device_id == addr->device_id);
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g_assert(!addr->device_id || device_id == addr->device_id);
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}
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}
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static uint8_t qpci_find_resource_reserve_capability(QPCIDevice *dev)
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{
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uint16_t device_id;
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uint8_t cap = 0;
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if (qpci_config_readw(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_REDHAT) {
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return 0;
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}
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device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
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if (device_id != PCI_DEVICE_ID_REDHAT_PCIE_RP &&
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device_id != PCI_DEVICE_ID_REDHAT_BRIDGE) {
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return 0;
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}
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do {
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cap = qpci_find_capability(dev, PCI_CAP_ID_VNDR, cap);
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} while (cap &&
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qpci_config_readb(dev, cap + REDHAT_PCI_CAP_TYPE_OFFSET) !=
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REDHAT_PCI_CAP_RESOURCE_RESERVE);
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if (cap) {
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uint8_t cap_len = qpci_config_readb(dev, cap + PCI_CAP_FLAGS);
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if (cap_len < REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE) {
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return 0;
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}
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}
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return cap;
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}
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static void qpci_secondary_buses_rec(QPCIBus *qbus, int bus, int *pci_bus)
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{
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QPCIDevice *dev;
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uint16_t class;
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uint8_t pribus, secbus, subbus;
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int index;
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for (index = 0; index < 32; index++) {
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dev = qpci_device_find(qbus, QPCI_DEVFN(bus + index, 0));
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if (dev == NULL) {
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continue;
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}
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class = qpci_config_readw(dev, PCI_CLASS_DEVICE);
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if (class == PCI_CLASS_BRIDGE_PCI) {
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qpci_config_writeb(dev, PCI_SECONDARY_BUS, 255);
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qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, 0);
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}
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g_free(dev);
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}
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for (index = 0; index < 32; index++) {
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dev = qpci_device_find(qbus, QPCI_DEVFN(bus + index, 0));
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if (dev == NULL) {
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continue;
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}
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class = qpci_config_readw(dev, PCI_CLASS_DEVICE);
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if (class != PCI_CLASS_BRIDGE_PCI) {
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g_free(dev);
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continue;
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}
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pribus = qpci_config_readb(dev, PCI_PRIMARY_BUS);
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if (pribus != bus) {
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qpci_config_writeb(dev, PCI_PRIMARY_BUS, bus);
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}
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secbus = qpci_config_readb(dev, PCI_SECONDARY_BUS);
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(*pci_bus)++;
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if (*pci_bus != secbus) {
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secbus = *pci_bus;
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qpci_config_writeb(dev, PCI_SECONDARY_BUS, secbus);
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}
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subbus = qpci_config_readb(dev, PCI_SUBORDINATE_BUS);
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qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, 255);
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qpci_secondary_buses_rec(qbus, secbus << 5, pci_bus);
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if (subbus != *pci_bus) {
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uint8_t res_bus = *pci_bus;
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uint8_t cap = qpci_find_resource_reserve_capability(dev);
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if (cap) {
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uint32_t tmp_res_bus;
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tmp_res_bus = qpci_config_readl(dev, cap +
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REDHAT_PCI_CAP_RES_RESERVE_BUS_RES);
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if (tmp_res_bus != (uint32_t)-1) {
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res_bus = tmp_res_bus & 0xFF;
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if ((uint8_t)(res_bus + secbus) < secbus ||
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(uint8_t)(res_bus + secbus) < res_bus) {
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res_bus = 0;
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}
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if (secbus + res_bus > *pci_bus) {
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res_bus = secbus + res_bus;
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}
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}
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}
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subbus = res_bus;
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*pci_bus = res_bus;
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}
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qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, subbus);
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g_free(dev);
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}
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}
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int qpci_secondary_buses_init(QPCIBus *bus)
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{
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int last_bus = 0;
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qpci_secondary_buses_rec(bus, 0, &last_bus);
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return last_bus;
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}
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void qpci_device_enable(QPCIDevice *dev)
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void qpci_device_enable(QPCIDevice *dev)
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{
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{
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uint16_t cmd;
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uint16_t cmd;
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@ -81,6 +81,7 @@ void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
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void *data);
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void *data);
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QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
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QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
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void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr);
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void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr);
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int qpci_secondary_buses_init(QPCIBus *bus);
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bool qpci_has_buggy_msi(QPCIDevice *dev);
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bool qpci_has_buggy_msi(QPCIDevice *dev);
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bool qpci_check_buggy_msi(QPCIDevice *dev);
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bool qpci_check_buggy_msi(QPCIDevice *dev);
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