tcg: Add tcg_reg_alloc_dup2
There are several ways we can expand a vector dup of a 64-bit element on a 32-bit host. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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97
tcg/tcg.c
97
tcg/tcg.c
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@ -4084,6 +4084,98 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
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}
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}
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static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op)
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{
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const TCGLifeData arg_life = op->life;
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TCGTemp *ots, *itsl, *itsh;
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TCGType vtype = TCGOP_VECL(op) + TCG_TYPE_V64;
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/* This opcode is only valid for 32-bit hosts, for 64-bit elements. */
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tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
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tcg_debug_assert(TCGOP_VECE(op) == MO_64);
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ots = arg_temp(op->args[0]);
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itsl = arg_temp(op->args[1]);
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itsh = arg_temp(op->args[2]);
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/* ENV should not be modified. */
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tcg_debug_assert(!temp_readonly(ots));
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/* Allocate the output register now. */
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if (ots->val_type != TEMP_VAL_REG) {
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TCGRegSet allocated_regs = s->reserved_regs;
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TCGRegSet dup_out_regs =
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tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
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/* Make sure to not spill the input registers. */
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if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) {
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tcg_regset_set_reg(allocated_regs, itsl->reg);
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}
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if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) {
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tcg_regset_set_reg(allocated_regs, itsh->reg);
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}
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ots->reg = tcg_reg_alloc(s, dup_out_regs, allocated_regs,
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op->output_pref[0], ots->indirect_base);
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ots->val_type = TEMP_VAL_REG;
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ots->mem_coherent = 0;
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s->reg_to_temp[ots->reg] = ots;
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}
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/* Promote dup2 of immediates to dupi_vec. */
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if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) {
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uint64_t val = deposit64(itsl->val, 32, 32, itsh->val);
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MemOp vece = MO_64;
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if (val == dup_const(MO_8, val)) {
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vece = MO_8;
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} else if (val == dup_const(MO_16, val)) {
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vece = MO_16;
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} else if (val == dup_const(MO_32, val)) {
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vece = MO_32;
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}
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tcg_out_dupi_vec(s, vtype, vece, ots->reg, val);
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goto done;
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}
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/* If the two inputs form one 64-bit value, try dupm_vec. */
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if (itsl + 1 == itsh && itsl->base_type == TCG_TYPE_I64) {
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if (!itsl->mem_coherent) {
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temp_sync(s, itsl, s->reserved_regs, 0, 0);
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}
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if (!itsh->mem_coherent) {
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temp_sync(s, itsh, s->reserved_regs, 0, 0);
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}
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#ifdef HOST_WORDS_BIGENDIAN
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TCGTemp *its = itsh;
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#else
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TCGTemp *its = itsl;
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#endif
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if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg,
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its->mem_base->reg, its->mem_offset)) {
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goto done;
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}
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}
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/* Fall back to generic expansion. */
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return false;
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done:
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if (IS_DEAD_ARG(1)) {
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temp_dead(s, itsl);
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}
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if (IS_DEAD_ARG(2)) {
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temp_dead(s, itsh);
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}
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if (NEED_SYNC_ARG(0)) {
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temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0));
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} else if (IS_DEAD_ARG(0)) {
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temp_dead(s, ots);
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}
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return true;
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}
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#ifdef TCG_TARGET_STACK_GROWSUP
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#define STACK_DIR(x) (-(x))
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#else
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@ -4501,6 +4593,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
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case INDEX_op_call:
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tcg_reg_alloc_call(s, op);
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break;
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case INDEX_op_dup2_vec:
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if (tcg_reg_alloc_dup2(s, op)) {
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break;
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}
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/* fall through */
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default:
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/* Sanity check that we've not introduced any unhandled opcodes. */
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tcg_debug_assert(tcg_op_supported(opc));
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