target/arm: Move the vfp decodetree calls next to the base isa
Have the calls adjacent as an intermediate step toward actually merging the decodes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200224222232.13807-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2646,31 +2646,6 @@ static void gen_neon_dup_high16(TCGv_i32 var)
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tcg_temp_free_i32(tmp);
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}
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/*
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* Disassemble a VFP instruction. Returns nonzero if an error occurred
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* (ie. an undefined instruction).
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*/
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static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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{
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/*
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* If the decodetree decoder handles this insn it will always
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* emit code to either execute the insn or generate an appropriate
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* exception; so we don't need to ever return non-zero to tell
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* the calling code to emit an UNDEF exception.
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*/
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if (extract32(insn, 28, 4) == 0xf) {
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if (disas_vfp_uncond(s, insn)) {
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return 0;
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}
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} else {
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if (disas_vfp(s, insn)) {
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return 0;
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}
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}
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/* If the decodetree decoder didn't handle this insn, it must be UNDEF */
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return 1;
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}
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static inline bool use_goto_tb(DisasContext *s, target_ulong dest)
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{
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#ifndef CONFIG_USER_ONLY
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@ -10778,7 +10753,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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ARCH(5);
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/* Unconditional instructions. */
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if (disas_a32_uncond(s, insn)) {
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/* TODO: Perhaps merge these into one decodetree output file. */
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if (disas_a32_uncond(s, insn) ||
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disas_vfp_uncond(s, insn)) {
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return;
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}
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/* fall back to legacy decoder */
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@ -10805,13 +10782,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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}
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return;
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}
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if ((insn & 0x0f000e10) == 0x0e000a00) {
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/* VFP. */
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if (disas_vfp_insn(s, insn)) {
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goto illegal_op;
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}
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return;
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}
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if ((insn & 0x0e000f00) == 0x0c000100) {
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if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
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/* iWMMXt register transfer. */
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@ -10842,7 +10812,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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arm_skip_unless(s, cond);
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}
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if (disas_a32(s, insn)) {
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/* TODO: Perhaps merge these into one decodetree output file. */
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if (disas_a32(s, insn) ||
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disas_vfp(s, insn)) {
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return;
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}
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/* fall back to legacy decoder */
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@ -10852,11 +10824,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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case 0xd:
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case 0xe:
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if (((insn >> 8) & 0xe) == 10) {
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/* VFP. */
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if (disas_vfp_insn(s, insn)) {
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goto illegal_op;
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}
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} else if (disas_coproc_insn(s, insn)) {
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/* VFP, but failed disas_vfp. */
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goto illegal_op;
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}
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if (disas_coproc_insn(s, insn)) {
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/* Coprocessor. */
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goto illegal_op;
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}
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@ -10945,7 +10916,14 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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ARCH(6T2);
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}
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if (disas_t32(s, insn)) {
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/*
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* TODO: Perhaps merge these into one decodetree output file.
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* Note disas_vfp is written for a32 with cond field in the
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* top nibble. The t32 encoding requires 0xe in the top nibble.
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*/
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if (disas_t32(s, insn) ||
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disas_vfp_uncond(s, insn) ||
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((insn >> 28) == 0xe && disas_vfp(s, insn))) {
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return;
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}
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/* fall back to legacy decoder */
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@ -10962,17 +10940,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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goto illegal_op; /* op0 = 0b11 : unallocated */
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}
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if (disas_vfp_insn(s, insn)) {
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if (((insn >> 8) & 0xe) == 10 &&
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dc_isar_feature(aa32_fpsp_v2, s)) {
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/* FP, and the CPU supports it */
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goto illegal_op;
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} else {
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/* All other insns: NOCP */
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(),
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default_exception_el(s));
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}
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if (((insn >> 8) & 0xe) == 10 &&
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dc_isar_feature(aa32_fpsp_v2, s)) {
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/* FP, and the CPU supports it */
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goto illegal_op;
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} else {
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/* All other insns: NOCP */
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(),
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default_exception_el(s));
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}
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break;
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}
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@ -10995,9 +10971,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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goto illegal_op;
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}
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} else if (((insn >> 8) & 0xe) == 10) {
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if (disas_vfp_insn(s, insn)) {
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goto illegal_op;
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}
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/* VFP, but failed disas_vfp. */
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goto illegal_op;
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} else {
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if (insn & (1 << 28))
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goto illegal_op;
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