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target/arm: Move the vfp decodetree calls next to the base isa

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Have the calls adjacent as an intermediate step toward
actually merging the decodes.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-24 14:22:27 -08:00 committed by Peter Maydell
parent dc778a6873
commit f0f6d5c81b
1 changed files with 29 additions and 54 deletions
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59
target/arm/translate.c
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@ -2646,31 +2646,6 @@ static void gen_neon_dup_high16(TCGv_i32 var)
tcg_temp_free_i32(tmp);
}
/*
* Disassemble a VFP instruction. Returns nonzero if an error occurred
* (ie. an undefined instruction).
*/
static int disas_vfp_insn(DisasContext *s, uint32_t insn)
{
/*
* If the decodetree decoder handles this insn it will always
* emit code to either execute the insn or generate an appropriate
* exception; so we don't need to ever return non-zero to tell
* the calling code to emit an UNDEF exception.
*/
if (extract32(insn, 28, 4) == 0xf) {
if (disas_vfp_uncond(s, insn)) {
return 0;
}
} else {
if (disas_vfp(s, insn)) {
return 0;
}
}
/* If the decodetree decoder didn't handle this insn, it must be UNDEF */
return 1;
}
static inline bool use_goto_tb(DisasContext *s, target_ulong dest)
{
#ifndef CONFIG_USER_ONLY
@ -10778,7 +10753,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
ARCH(5);
/* Unconditional instructions. */
if (disas_a32_uncond(s, insn)) {
/* TODO: Perhaps merge these into one decodetree output file. */
if (disas_a32_uncond(s, insn) ||
disas_vfp_uncond(s, insn)) {
return;
}
/* fall back to legacy decoder */
@ -10805,13 +10782,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
return;
}
if ((insn & 0x0f000e10) == 0x0e000a00) {
/* VFP. */
if (disas_vfp_insn(s, insn)) {
goto illegal_op;
}
return;
}
if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
@ -10842,7 +10812,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
arm_skip_unless(s, cond);
}
if (disas_a32(s, insn)) {
/* TODO: Perhaps merge these into one decodetree output file. */
if (disas_a32(s, insn) ||
disas_vfp(s, insn)) {
return;
}
/* fall back to legacy decoder */
@ -10852,11 +10824,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
case 0xd:
case 0xe:
if (((insn >> 8) & 0xe) == 10) {
/* VFP. */
if (disas_vfp_insn(s, insn)) {
/* VFP, but failed disas_vfp. */
goto illegal_op;
}
} else if (disas_coproc_insn(s, insn)) {
if (disas_coproc_insn(s, insn)) {
/* Coprocessor. */
goto illegal_op;
}
@ -10945,7 +10916,14 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
ARCH(6T2);
}
if (disas_t32(s, insn)) {
/*
* TODO: Perhaps merge these into one decodetree output file.
* Note disas_vfp is written for a32 with cond field in the
* top nibble. The t32 encoding requires 0xe in the top nibble.
*/
if (disas_t32(s, insn) ||
disas_vfp_uncond(s, insn) ||
((insn >> 28) == 0xe && disas_vfp(s, insn))) {
return;
}
/* fall back to legacy decoder */
@ -10962,7 +10940,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op; /* op0 = 0b11 : unallocated */
}
if (disas_vfp_insn(s, insn)) {
if (((insn >> 8) & 0xe) == 10 &&
dc_isar_feature(aa32_fpsp_v2, s)) {
/* FP, and the CPU supports it */
@ -10973,7 +10950,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
syn_uncategorized(),
default_exception_el(s));
}
}
break;
}
if ((insn & 0xfe000a00) == 0xfc000800
@ -10995,9 +10971,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
}
} else if (((insn >> 8) & 0xe) == 10) {
if (disas_vfp_insn(s, insn)) {
/* VFP, but failed disas_vfp. */
goto illegal_op;
}
} else {
if (insn & (1 << 28))
goto illegal_op;