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target/avr: Introduce basic CPU class object

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This patch introduces AVR CPU class object and its basic elements
and functions.

[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Co-developed-by: Michael Rolnik <mrolnik@gmail.com>
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[thuth: Adjusted reset and parent_reset handling]
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-3-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Rolnik 2020-01-26 19:51:34 +01:00 committed by Philippe Mathieu-Daudé
parent c8c0d267fd
commit f1c671f96c
3 changed files with 399 additions and 0 deletions
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53
target/avr/cpu-qom.h Normal file
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@ -0,0 +1,53 @@
/*
* QEMU AVR CPU
*
* Copyright (c) 2016-2020 Michael Rolnik
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#ifndef QEMU_AVR_QOM_H
#define QEMU_AVR_QOM_H
#include "hw/core/cpu.h"
#define TYPE_AVR_CPU "avr-cpu"
#define AVR_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(AVRCPUClass, (klass), TYPE_AVR_CPU)
#define AVR_CPU(obj) \
OBJECT_CHECK(AVRCPU, (obj), TYPE_AVR_CPU)
#define AVR_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(AVRCPUClass, (obj), TYPE_AVR_CPU)
/**
* AVRCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @vr: Version Register value.
*
* A AVR CPU model.
*/
typedef struct AVRCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
} AVRCPUClass;
typedef struct AVRCPU AVRCPU;
#endif /* !defined (QEMU_AVR_CPU_QOM_H) */

207
target/avr/cpu.c Normal file
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@ -0,0 +1,207 @@
/*
* QEMU AVR CPU
*
* Copyright (c) 2019-2020 Michael Rolnik
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/qemu-print.h"
#include "exec/exec-all.h"
#include "cpu.h"
#include "disas/dis-asm.h"
static void avr_cpu_set_pc(CPUState *cs, vaddr value)
{
AVRCPU *cpu = AVR_CPU(cs);
cpu->env.pc_w = value / 2; /* internally PC points to words */
}
static bool avr_cpu_has_work(CPUState *cs)
{
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
&& cpu_interrupts_enabled(env);
}
static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
env->pc_w = tb->pc / 2; /* internally PC points to words */
}
static void avr_cpu_reset(DeviceState *ds)
{
CPUState *cs = CPU(ds);
AVRCPU *cpu = AVR_CPU(cs);
AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
CPUAVRState *env = &cpu->env;
mcc->parent_reset(ds);
env->pc_w = 0;
env->sregI = 1;
env->sregC = 0;
env->sregZ = 0;
env->sregN = 0;
env->sregV = 0;
env->sregS = 0;
env->sregH = 0;
env->sregT = 0;
env->rampD = 0;
env->rampX = 0;
env->rampY = 0;
env->rampZ = 0;
env->eind = 0;
env->sp = 0;
env->skip = 0;
memset(env->r, 0, sizeof(env->r));
tlb_flush(cs);
}
static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->mach = bfd_arch_avr;
info->print_insn = NULL;
}
static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
qemu_init_vcpu(cs);
cpu_reset(cs);
mcc->parent_realize(dev, errp);
}
static void avr_cpu_set_int(void *opaque, int irq, int level)
{
AVRCPU *cpu = opaque;
CPUAVRState *env = &cpu->env;
CPUState *cs = CPU(cpu);
uint64_t mask = (1ull << irq);
if (level) {
env->intsrc |= mask;
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
env->intsrc &= ~mask;
if (env->intsrc == 0) {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
}
static void avr_cpu_initfn(Object *obj)
{
AVRCPU *cpu = AVR_CPU(obj);
cpu_set_cpustate_pointers(cpu);
/* Set the number of interrupts supported by the CPU. */
qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
sizeof(cpu->env.intsrc) * 8);
}
static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
oc = object_class_by_name(cpu_model);
if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
object_class_is_abstract(oc)) {
oc = NULL;
}
return oc;
}
static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
int i;
qemu_fprintf(f, "\n");
qemu_fprintf(f, "PC: %06x\n", env->pc_w);
qemu_fprintf(f, "SP: %04x\n", env->sp);
qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16);
qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16);
qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16);
qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16);
qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16);
qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]);
qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]);
qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]);
qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n",
env->sregI ? 'I' : '-',
env->sregT ? 'T' : '-',
env->sregH ? 'H' : '-',
env->sregS ? 'S' : '-',
env->sregV ? 'V' : '-',
env->sregN ? '-' : 'N', /* Zf has negative logic */
env->sregZ ? 'Z' : '-',
env->sregC ? 'I' : '-');
qemu_fprintf(f, "SKIP: %02x\n", env->skip);
qemu_fprintf(f, "\n");
for (i = 0; i < ARRAY_SIZE(env->r); i++) {
qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]);
if ((i % 8) == 7) {
qemu_fprintf(f, "\n");
}
}
qemu_fprintf(f, "\n");
}
static void avr_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
mcc->parent_realize = dc->realize;
dc->realize = avr_cpu_realizefn;
device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
cc->class_by_name = avr_cpu_class_by_name;
cc->has_work = avr_cpu_has_work;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->tcg_initialize = avr_cpu_tcg_init;
cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
}

139
target/avr/cpu.h
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@ -21,8 +21,17 @@
#ifndef QEMU_AVR_CPU_H
#define QEMU_AVR_CPU_H
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#ifdef CONFIG_USER_ONLY
#error "AVR 8-bit does not support user mode"
#endif
#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
#define TCG_GUEST_DEFAULT_MO 0
/*
@ -63,4 +72,134 @@
*/
#define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS)
typedef struct CPUAVRState CPUAVRState;
struct CPUAVRState {
uint32_t pc_w; /* 0x003fffff up to 22 bits */
uint32_t sregC; /* 0x00000001 1 bit */
uint32_t sregZ; /* 0x00000001 1 bit */
uint32_t sregN; /* 0x00000001 1 bit */
uint32_t sregV; /* 0x00000001 1 bit */
uint32_t sregS; /* 0x00000001 1 bit */
uint32_t sregH; /* 0x00000001 1 bit */
uint32_t sregT; /* 0x00000001 1 bit */
uint32_t sregI; /* 0x00000001 1 bit */
uint32_t rampD; /* 0x00ff0000 8 bits */
uint32_t rampX; /* 0x00ff0000 8 bits */
uint32_t rampY; /* 0x00ff0000 8 bits */
uint32_t rampZ; /* 0x00ff0000 8 bits */
uint32_t eind; /* 0x00ff0000 8 bits */
uint32_t r[NUMBER_OF_CPU_REGISTERS]; /* 8 bits each */
uint32_t sp; /* 16 bits */
uint32_t skip; /* if set skip instruction */
uint64_t intsrc; /* interrupt sources */
bool fullacc; /* CPU/MEM if true MEM only otherwise */
uint64_t features;
};
/**
* AVRCPU:
* @env: #CPUAVRState
*
* A AVR CPU.
*/
typedef struct AVRCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUAVRState env;
} AVRCPU;
void avr_cpu_do_interrupt(CPUState *cpu);
bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#define cpu_list avr_cpu_list
#define cpu_signal_handler cpu_avr_signal_handler
#define cpu_mmu_index avr_cpu_mmu_index
static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)
{
return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
}
void avr_cpu_tcg_init(void);
void avr_cpu_list(void);
int cpu_avr_exec(CPUState *cpu);
int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc);
int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf,
int len, bool is_write);
enum {
TB_FLAGS_FULL_ACCESS = 1,
TB_FLAGS_SKIP = 2,
};
static inline void cpu_get_tb_cpu_state(CPUAVRState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
uint32_t flags = 0;
*pc = env->pc_w * 2;
*cs_base = 0;
if (env->fullacc) {
flags |= TB_FLAGS_FULL_ACCESS;
}
if (env->skip) {
flags |= TB_FLAGS_SKIP;
}
*pflags = flags;
}
static inline int cpu_interrupts_enabled(CPUAVRState *env)
{
return env->sregI != 0;
}
static inline uint8_t cpu_get_sreg(CPUAVRState *env)
{
uint8_t sreg;
sreg = (env->sregC) << 0
| (env->sregZ) << 1
| (env->sregN) << 2
| (env->sregV) << 3
| (env->sregS) << 4
| (env->sregH) << 5
| (env->sregT) << 6
| (env->sregI) << 7;
return sreg;
}
static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg)
{
env->sregC = (sreg >> 0) & 0x01;
env->sregZ = (sreg >> 1) & 0x01;
env->sregN = (sreg >> 2) & 0x01;
env->sregV = (sreg >> 3) & 0x01;
env->sregS = (sreg >> 4) & 0x01;
env->sregH = (sreg >> 5) & 0x01;
env->sregT = (sreg >> 6) & 0x01;
env->sregI = (sreg >> 7) & 0x01;
}
bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
typedef CPUAVRState CPUArchState;
typedef AVRCPU ArchCPU;
#include "exec/cpu-all.h"
#endif /* !defined (QEMU_AVR_CPU_H) */