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qemu-sparc queue 

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Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20190517' into staging

qemu-sparc queue

# gpg: Signature made Fri 17 May 2019 10:30:54 BST
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-sparc-20190517:
  MAINTAINERS: add myself for leon3
  leon3: introduce the plug and play mechanism
  leon3: add a little bootloader
  grlib, apbuart: get rid of the old-style create function
  grlib, gptimer: get rid of the old-style create function
  grlib, irqmp: get rid of the old-style create function
  leon3: fix the error message when no bios are provided
  hw/char/escc: Lower irq when transmit buffer is filled

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-05-17 15:46:37 +01:00
parent e48a748fc8 918b8adeb2
commit f2a930ad8c
10 changed files with 490 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
MAINTAINERS
View File

@ -1158,10 +1158,11 @@ F: include/hw/timer/sun4v-rtc.h
Leon3
M: Fabien Chouteau <chouteau@adacore.com>
M: KONRAD Frederic <frederic.konrad@adacore.com>
S: Maintained
F: hw/sparc/leon3.c
F: hw/*/grlib*
F: include/hw/sparc/grlib.h
F: include/hw/*/grlib*
S390 Machines
-------------

7
hw/char/escc.c
View File

@ -509,6 +509,13 @@ static void escc_mem_write(void *opaque, hwaddr addr,
break;
case SERIAL_DATA:
trace_escc_mem_writeb_data(CHN_C(s), val);
/*
* Lower the irq when data is written to the Tx buffer and no other
* interrupts are currently pending. The irq will be raised again once
* the Tx buffer becomes empty below.
*/
s->txint = 0;
escc_update_irq(s);
s->tx = val;
if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled
if (qemu_chr_fe_backend_connected(&s->chr)) {

4
hw/char/grlib_apbuart.c
View File

@ -1,7 +1,7 @@
/*
* QEMU GRLIB APB UART Emulator
*
* Copyright (c) 2010-2011 AdaCore
* Copyright (c) 2010-2019 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -23,6 +23,7 @@
*/
#include "qemu/osdep.h"
#include "hw/sparc/grlib.h"
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
@ -68,7 +69,6 @@
#define FIFO_LENGTH 1024
#define TYPE_GRLIB_APB_UART "grlib,apbuart"
#define GRLIB_APB_UART(obj) \
OBJECT_CHECK(UART, (obj), TYPE_GRLIB_APB_UART)

3
hw/intc/grlib_irqmp.c
View File

@ -3,7 +3,7 @@
*
* (Multiprocessor and extended interrupt not supported)
*
* Copyright (c) 2010-2011 AdaCore
* Copyright (c) 2010-2019 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -47,7 +47,6 @@
#define FORCE_OFFSET 0x80
#define EXTENDED_OFFSET 0xC0
#define TYPE_GRLIB_IRQMP "grlib,irqmp"
#define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP)
typedef struct IRQMPState IRQMPState;

2
hw/misc/Makefile.objs
View File

@ -77,3 +77,5 @@ obj-$(CONFIG_AUX) += auxbus.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
obj-$(CONFIG_MSF2) += msf2-sysreg.o
obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o
obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o

269
hw/misc/grlib_ahb_apb_pnp.c Normal file
View File

@ -0,0 +1,269 @@
/*
* GRLIB AHB APB PNP
*
* Copyright (C) 2019 AdaCore
*
* Developed by :
* Frederic Konrad <frederic.konrad@adacore.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
*/
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/misc/grlib_ahb_apb_pnp.h"
#define GRLIB_PNP_VENDOR_SHIFT (24)
#define GRLIB_PNP_VENDOR_SIZE (8)
#define GRLIB_PNP_DEV_SHIFT (12)
#define GRLIB_PNP_DEV_SIZE (12)
#define GRLIB_PNP_VER_SHIFT (5)
#define GRLIB_PNP_VER_SIZE (5)
#define GRLIB_PNP_IRQ_SHIFT (0)
#define GRLIB_PNP_IRQ_SIZE (5)
#define GRLIB_PNP_ADDR_SHIFT (20)
#define GRLIB_PNP_ADDR_SIZE (12)
#define GRLIB_PNP_MASK_SHIFT (4)
#define GRLIB_PNP_MASK_SIZE (12)
#define GRLIB_AHB_DEV_ADDR_SHIFT (20)
#define GRLIB_AHB_DEV_ADDR_SIZE (12)
#define GRLIB_AHB_ENTRY_SIZE (0x20)
#define GRLIB_AHB_MAX_DEV (64)
#define GRLIB_AHB_SLAVE_OFFSET (0x800)
#define GRLIB_APB_DEV_ADDR_SHIFT (8)
#define GRLIB_APB_DEV_ADDR_SIZE (12)
#define GRLIB_APB_ENTRY_SIZE (0x08)
#define GRLIB_APB_MAX_DEV (512)
#define GRLIB_PNP_MAX_REGS (0x1000)
typedef struct AHBPnp {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t regs[GRLIB_PNP_MAX_REGS >> 2];
uint8_t master_count;
uint8_t slave_count;
} AHBPnp;
void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
uint8_t vendor, uint16_t device, int slave,
int type)
{
unsigned int reg_start;
/*
* AHB entries look like this:
*
* 31 -------- 23 -------- 11 ----- 9 -------- 4 --- 0
* | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ |
* --------------------------------------------------
* | USER |
* --------------------------------------------------
* | USER |
* --------------------------------------------------
* | USER |
* --------------------------------------------------
* | USER |
* --------------------------------------------------
* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
* | ADDR[31..12] | 00PC | MASK | TYPE |
* --------------------------------------------------
* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
* | ADDR[31..12] | 00PC | MASK | TYPE |
* --------------------------------------------------
* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
* | ADDR[31..12] | 00PC | MASK | TYPE |
* --------------------------------------------------
* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
* | ADDR[31..12] | 00PC | MASK | TYPE |
* --------------------------------------------------
*/
if (slave) {
assert(dev->slave_count < GRLIB_AHB_MAX_DEV);
reg_start = (GRLIB_AHB_SLAVE_OFFSET
+ (dev->slave_count * GRLIB_AHB_ENTRY_SIZE)) >> 2;
dev->slave_count++;
} else {
assert(dev->master_count < GRLIB_AHB_MAX_DEV);
reg_start = (dev->master_count * GRLIB_AHB_ENTRY_SIZE) >> 2;
dev->master_count++;
}
dev->regs[reg_start] = deposit32(dev->regs[reg_start],
GRLIB_PNP_VENDOR_SHIFT,
GRLIB_PNP_VENDOR_SIZE,
vendor);
dev->regs[reg_start] = deposit32(dev->regs[reg_start],
GRLIB_PNP_DEV_SHIFT,
GRLIB_PNP_DEV_SIZE,
device);
reg_start += 4;
/* AHB Memory Space */
dev->regs[reg_start] = type;
dev->regs[reg_start] = deposit32(dev->regs[reg_start],
GRLIB_PNP_ADDR_SHIFT,
GRLIB_PNP_ADDR_SIZE,
extract32(address,
GRLIB_AHB_DEV_ADDR_SHIFT,
GRLIB_AHB_DEV_ADDR_SIZE));
dev->regs[reg_start] = deposit32(dev->regs[reg_start],
GRLIB_PNP_MASK_SHIFT,
GRLIB_PNP_MASK_SIZE,
mask);
}
static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr offset, unsigned size)
{
AHBPnp *ahb_pnp = GRLIB_AHB_PNP(opaque);
return ahb_pnp->regs[offset >> 2];
}
static const MemoryRegionOps grlib_ahb_pnp_ops = {
.read = grlib_ahb_pnp_read,
.endianness = DEVICE_BIG_ENDIAN,
};
static void grlib_ahb_pnp_realize(DeviceState *dev, Error **errp)
{
AHBPnp *ahb_pnp = GRLIB_AHB_PNP(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
memory_region_init_io(&ahb_pnp->iomem, OBJECT(dev), &grlib_ahb_pnp_ops,
ahb_pnp, TYPE_GRLIB_AHB_PNP, GRLIB_PNP_MAX_REGS);
sysbus_init_mmio(sbd, &ahb_pnp->iomem);
}
static void grlib_ahb_pnp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = grlib_ahb_pnp_realize;
}
static const TypeInfo grlib_ahb_pnp_info = {
.name = TYPE_GRLIB_AHB_PNP,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AHBPnp),
.class_init = grlib_ahb_pnp_class_init,
};
/* APBPnp */
typedef struct APBPnp {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t regs[GRLIB_PNP_MAX_REGS >> 2];
uint32_t entry_count;
} APBPnp;
void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
uint8_t vendor, uint16_t device, uint8_t version,
uint8_t irq, int type)
{
unsigned int reg_start;
/*
* APB entries look like this:
*
* 31 -------- 23 -------- 11 ----- 9 ------- 4 --- 0
* | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ |
*
* 31 ---------- 20 --- 15 ----------------- 3 ---- 0
* | ADDR[20..8] | 0000 | MASK | TYPE |
*/
assert(dev->entry_count < GRLIB_APB_MAX_DEV);
reg_start = (dev->entry_count * GRLIB_APB_ENTRY_SIZE) >> 2;
dev->entry_count++;
dev->regs[reg_start] = deposit32(dev->regs[reg_start],
GRLIB_PNP_VENDOR_SHIFT,
GRLIB_PNP_VENDOR_SIZE,
vendor);
dev->regs[reg_start] = deposit32(dev->regs[reg_start],
GRLIB_PNP_DEV_SHIFT,
GRLIB_PNP_DEV_SIZE,
device);
dev->regs[reg_start] = deposit32(dev->regs[reg_start],
GRLIB_PNP_VER_SHIFT,
GRLIB_PNP_VER_SIZE,
version);
dev->regs[reg_start] = deposit32(dev->regs[reg_start],
GRLIB_PNP_IRQ_SHIFT,
GRLIB_PNP_IRQ_SIZE,
irq);
reg_start += 1;
dev->regs[reg_start] = type;
dev->regs[reg_start] = deposit32(dev->regs[reg_start],
GRLIB_PNP_ADDR_SHIFT,
GRLIB_PNP_ADDR_SIZE,
extract32(address,
GRLIB_APB_DEV_ADDR_SHIFT,
GRLIB_APB_DEV_ADDR_SIZE));
dev->regs[reg_start] = deposit32(dev->regs[reg_start],
GRLIB_PNP_MASK_SHIFT,
GRLIB_PNP_MASK_SIZE,
mask);
}
static uint64_t grlib_apb_pnp_read(void *opaque, hwaddr offset, unsigned size)
{
APBPnp *apb_pnp = GRLIB_APB_PNP(opaque);
return apb_pnp->regs[offset >> 2];
}
static const MemoryRegionOps grlib_apb_pnp_ops = {
.read = grlib_apb_pnp_read,
.endianness = DEVICE_BIG_ENDIAN,
};
static void grlib_apb_pnp_realize(DeviceState *dev, Error **errp)
{
APBPnp *apb_pnp = GRLIB_APB_PNP(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
memory_region_init_io(&apb_pnp->iomem, OBJECT(dev), &grlib_apb_pnp_ops,
apb_pnp, TYPE_GRLIB_APB_PNP, GRLIB_PNP_MAX_REGS);
sysbus_init_mmio(sbd, &apb_pnp->iomem);
}
static void grlib_apb_pnp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = grlib_apb_pnp_realize;
}
static const TypeInfo grlib_apb_pnp_info = {
.name = TYPE_GRLIB_APB_PNP,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(APBPnp),
.class_init = grlib_apb_pnp_class_init,
};
static void grlib_ahb_apb_pnp_register_types(void)
{
type_register_static(&grlib_ahb_pnp_info);
type_register_static(&grlib_apb_pnp_info);
}
type_init(grlib_ahb_apb_pnp_register_types)

157
hw/sparc/leon3.c
View File

@ -1,7 +1,7 @@
/*
* QEMU Leon3 System Emulator
*
* Copyright (c) 2010-2011 AdaCore
* Copyright (c) 2010-2019 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -39,20 +39,88 @@
#include "exec/address-spaces.h"
#include "hw/sparc/grlib.h"
#include "hw/misc/grlib_ahb_apb_pnp.h"
/* Default system clock. */
#define CPU_CLK (40 * 1000 * 1000)
#define PROM_FILENAME "u-boot.bin"
#define LEON3_PROM_FILENAME "u-boot.bin"
#define LEON3_PROM_OFFSET (0x00000000)
#define LEON3_RAM_OFFSET (0x40000000)
#define MAX_PILS 16
#define LEON3_UART_OFFSET (0x80000100)
#define LEON3_UART_IRQ (3)
#define LEON3_IRQMP_OFFSET (0x80000200)
#define LEON3_TIMER_OFFSET (0x80000300)
#define LEON3_TIMER_IRQ (6)
#define LEON3_TIMER_COUNT (2)
#define LEON3_APB_PNP_OFFSET (0x800FF000)
#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
typedef struct ResetData {
SPARCCPU *cpu;
uint32_t entry; /* save kernel entry in case of reset */
target_ulong sp; /* initial stack pointer */
} ResetData;
static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val)
{
stl_p(code++, 0x82100000); /* mov %g0, %g1 */
stl_p(code++, 0x84100000); /* mov %g0, %g2 */
stl_p(code++, 0x03000000 +
extract32(addr, 10, 22));
/* sethi %hi(addr), %g1 */
stl_p(code++, 0x82106000 +
extract32(addr, 0, 10));
/* or %g1, addr, %g1 */
stl_p(code++, 0x05000000 +
extract32(val, 10, 22));
/* sethi %hi(val), %g2 */
stl_p(code++, 0x8410a000 +
extract32(val, 0, 10));
/* or %g2, val, %g2 */
stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */
return code;
}
/*
* When loading a kernel in RAM the machine is expected to be in a different
* state (eg: initialized by the bootloader). This little code reproduces
* this behavior.
*/
static void write_bootloader(CPUSPARCState *env, uint8_t *base,
hwaddr kernel_addr)
{
uint32_t *p = (uint32_t *) base;
/* Initialize the UARTs */
/* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */
p = gen_store_u32(p, 0x80000108, 3);
/* Initialize the TIMER 0 */
/* *GPTIMER_SCALER_RELOAD = 40 - 1; */
p = gen_store_u32(p, 0x80000304, 39);
/* *GPTIMER0_COUNTER_RELOAD = 0xFFFE; */
p = gen_store_u32(p, 0x80000314, 0xFFFFFFFE);
/* *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART; */
p = gen_store_u32(p, 0x80000318, 3);
/* JUMP to the entry point */
stl_p(p++, 0x82100000); /* mov %g0, %g1 */
stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
/* sethi %hi(kernel_addr), %g1 */
stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
/* or kernel_addr, %g1 */
stl_p(p++, 0x81c04000); /* jmp %g1 */
stl_p(p++, 0x01000000); /* nop */
}
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
@ -121,6 +189,10 @@ static void leon3_generic_hw_init(MachineState *machine)
int bios_size;
int prom_size;
ResetData *reset_info;
DeviceState *dev;
int i;
AHBPnp *ahb_pnp;
APBPnp *apb_pnp;
/* Init CPU */
cpu = SPARC_CPU(cpu_create(machine->cpu_type));
@ -131,13 +203,35 @@ static void leon3_generic_hw_init(MachineState *machine)
/* Reset data */
reset_info = g_malloc0(sizeof(ResetData));
reset_info->cpu = cpu;
reset_info->sp = 0x40000000 + ram_size;
reset_info->sp = LEON3_RAM_OFFSET + ram_size;
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate IRQ manager */
grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, &leon3_set_pil_in);
ahb_pnp = GRLIB_AHB_PNP(object_new(TYPE_GRLIB_AHB_PNP));
object_property_set_bool(OBJECT(ahb_pnp), true, "realized", &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
GRLIB_CPU_AREA);
apb_pnp = GRLIB_APB_PNP(object_new(TYPE_GRLIB_APB_PNP));
object_property_set_bool(OBJECT(apb_pnp), true, "realized", &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
/* Allocate IRQ manager */
dev = qdev_create(NULL, TYPE_GRLIB_IRQMP);
qdev_prop_set_ptr(dev, "set_pil_in", leon3_set_pil_in);
qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET);
env->irq_manager = dev;
env->qemu_irq_ack = leon3_irq_manager;
cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq, dev, MAX_PILS);
grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
2, 0, GRLIB_APBIO_AREA);
/* Allocate RAM */
if (ram_size > 1 * GiB) {
@ -148,17 +242,17 @@ static void leon3_generic_hw_init(MachineState *machine)
}
memory_region_allocate_system_memory(ram, NULL, "leon3.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0x40000000, ram);
memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, ram);
/* Allocate BIOS */
prom_size = 8 * MiB;
memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
memory_region_set_readonly(prom, true);
memory_region_add_subregion(address_space_mem, 0x00000000, prom);
memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
/* Load boot prom */
if (bios_name == NULL) {
bios_name = PROM_FILENAME;
bios_name = LEON3_PROM_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
@ -174,13 +268,15 @@ static void leon3_generic_hw_init(MachineState *machine)
}
if (bios_size > 0) {
ret = load_image_targphys(filename, 0x00000000, bios_size);
ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
if (ret < 0 || ret > prom_size) {
error_report("could not load prom '%s'", filename);
exit(1);
}
} else if (kernel_filename == NULL && !qtest_enabled()) {
error_report("Can't read bios image %s", filename);
error_report("Can't read bios image '%s'", filename
? filename
: LEON3_PROM_FILENAME);
exit(1);
}
g_free(filename);
@ -202,19 +298,48 @@ static void leon3_generic_hw_init(MachineState *machine)
exit(1);
}
if (bios_size <= 0) {
/* If there is no bios/monitor, start the application. */
env->pc = entry;
env->npc = entry + 4;
reset_info->entry = entry;
/*
* If there is no bios/monitor just start the application but put
* the machine in an initialized state through a little
* bootloader.
*/
uint8_t *bootloader_entry;
bootloader_entry = memory_region_get_ram_ptr(prom);
write_bootloader(env, bootloader_entry, entry);
env->pc = LEON3_PROM_OFFSET;
env->npc = LEON3_PROM_OFFSET + 4;
reset_info->entry = LEON3_PROM_OFFSET;
}
}
/* Allocate timers */
grlib_gptimer_create(0x80000300, 2, CPU_CLK, cpu_irqs, 6);
dev = qdev_create(NULL, TYPE_GRLIB_GPTIMER);
qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT);
qdev_prop_set_uint32(dev, "frequency", CPU_CLK);
qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
for (i = 0; i < LEON3_TIMER_COUNT; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
cpu_irqs[LEON3_TIMER_IRQ + i]);
}
grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV,
0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);
/* Allocate uart */
if (serial_hd(0)) {
grlib_apbuart_create(0x80000100, serial_hd(0), cpu_irqs[3]);
dev = qdev_create(NULL, TYPE_GRLIB_APB_UART);
qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]);
grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
LEON3_UART_IRQ, GRLIB_APBIO_AREA);
}
}

4
hw/timer/grlib_gptimer.c
View File

@ -1,7 +1,7 @@
/*
* QEMU GRLIB GPTimer Emulator
*
* Copyright (c) 2010-2011 AdaCore
* Copyright (c) 2010-2019 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -23,6 +23,7 @@
*/
#include "qemu/osdep.h"
#include "hw/sparc/grlib.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
@ -52,7 +53,6 @@
#define COUNTER_RELOAD_OFFSET 0x04
#define TIMER_BASE 0x10
#define TYPE_GRLIB_GPTIMER "grlib,gptimer"
#define GRLIB_GPTIMER(obj) \
OBJECT_CHECK(GPTimerUnit, (obj), TYPE_GRLIB_GPTIMER)

60
include/hw/misc/grlib_ahb_apb_pnp.h Normal file
View File

@ -0,0 +1,60 @@
/*
* GRLIB AHB APB PNP
*
* Copyright (C) 2019 AdaCore
*
* Developed by :
* Frederic Konrad <frederic.konrad@adacore.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef GRLIB_AHB_APB_PNP_H
#define GRLIB_AHB_APB_PNP_H
#define TYPE_GRLIB_AHB_PNP "grlib,ahbpnp"
#define GRLIB_AHB_PNP(obj) \
OBJECT_CHECK(AHBPnp, (obj), TYPE_GRLIB_AHB_PNP)
typedef struct AHBPnp AHBPnp;
#define TYPE_GRLIB_APB_PNP "grlib,apbpnp"
#define GRLIB_APB_PNP(obj) \
OBJECT_CHECK(APBPnp, (obj), TYPE_GRLIB_APB_PNP)
typedef struct APBPnp APBPnp;
void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
uint8_t vendor, uint16_t device, int slave,
int type);
void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
uint8_t vendor, uint16_t device, uint8_t version,
uint8_t irq, int type);
/* VENDORS */
#define GRLIB_VENDOR_GAISLER (0x01)
/* DEVICES */
#define GRLIB_LEON3_DEV (0x03)
#define GRLIB_APBMST_DEV (0x06)
#define GRLIB_APBUART_DEV (0x0C)
#define GRLIB_IRQMP_DEV (0x0D)
#define GRLIB_GPTIMER_DEV (0x11)
/* TYPE */
#define GRLIB_CPU_AREA (0x00)
#define GRLIB_APBIO_AREA (0x01)
#define GRLIB_AHBMEM_AREA (0x02)
#define GRLIB_AHB_MASTER (0x00)
#define GRLIB_AHB_SLAVE (0x01)
#endif /* GRLIB_AHB_APB_PNP_H */

78
include/hw/sparc/grlib.h
View File

@ -1,7 +1,7 @@
/*
* QEMU GRLIB Components
*
* Copyright (c) 2010-2011 AdaCore
* Copyright (c) 2010-2019 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -33,6 +33,7 @@
*/
/* IRQMP */
#define TYPE_GRLIB_IRQMP "grlib,irqmp"
typedef void (*set_pil_in_fn) (void *opaque, uint32_t pil_in);
@ -40,81 +41,10 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level);
void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
DeviceState *grlib_irqmp_create(hwaddr base,
CPUSPARCState *env,
qemu_irq **cpu_irqs,
uint32_t nr_irqs,
set_pil_in_fn set_pil_in)
{
DeviceState *dev;
assert(cpu_irqs != NULL);
dev = qdev_create(NULL, "grlib,irqmp");
qdev_prop_set_ptr(dev, "set_pil_in", set_pil_in);
qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
qdev_init_nofail(dev);
env->irq_manager = dev;
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
*cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq,
dev,
nr_irqs);
return dev;
}
/* GPTimer */
static inline
DeviceState *grlib_gptimer_create(hwaddr base,
uint32_t nr_timers,
uint32_t freq,
qemu_irq *cpu_irqs,
int base_irq)
{
DeviceState *dev;
int i;
dev = qdev_create(NULL, "grlib,gptimer");
qdev_prop_set_uint32(dev, "nr-timers", nr_timers);
qdev_prop_set_uint32(dev, "frequency", freq);
qdev_prop_set_uint32(dev, "irq-line", base_irq);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < nr_timers; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, cpu_irqs[base_irq + i]);
}
return dev;
}
#define TYPE_GRLIB_GPTIMER "grlib,gptimer"
/* APB UART */
static inline
DeviceState *grlib_apbuart_create(hwaddr base,
Chardev *serial,
qemu_irq irq)
{
DeviceState *dev;
dev = qdev_create(NULL, "grlib,apbuart");
qdev_prop_set_chr(dev, "chrdev", serial);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
return dev;
}
#define TYPE_GRLIB_APB_UART "grlib,apbuart"
#endif /* GRLIB_H */