target/i386: clean up comments over 80 chars per line
Add some comments, clean up comments over 80 chars per line. And there is an extra line in comment of CPUID_8000_0008_EBX_WBNOINVD, remove the extra enter and spaces. Acked-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Tao Xu <tao3.xu@intel.com> Message-Id: <20190926021055.6970-2-tao3.xu@intel.com> [ehabkost: rebase to latest git master] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Tao Xu
Eduardo Habkost
parent
64afc7c32b
commit
f2be0bebb6
@ -669,65 +669,117 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_SVM_PAUSEFILTER (1U << 10)
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#define CPUID_SVM_PFTHRESHOLD (1U << 12)
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#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
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#define CPUID_7_0_EBX_BMI1 (1U << 3)
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#define CPUID_7_0_EBX_HLE (1U << 4)
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#define CPUID_7_0_EBX_AVX2 (1U << 5)
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#define CPUID_7_0_EBX_SMEP (1U << 7)
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#define CPUID_7_0_EBX_BMI2 (1U << 8)
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#define CPUID_7_0_EBX_ERMS (1U << 9)
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#define CPUID_7_0_EBX_INVPCID (1U << 10)
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#define CPUID_7_0_EBX_RTM (1U << 11)
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#define CPUID_7_0_EBX_MPX (1U << 14)
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#define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
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#define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */
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#define CPUID_7_0_EBX_RDSEED (1U << 18)
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#define CPUID_7_0_EBX_ADX (1U << 19)
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#define CPUID_7_0_EBX_SMAP (1U << 20)
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#define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */
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#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
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#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
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#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
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#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
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#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
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#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
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#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
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#define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */
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#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
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#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */
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/* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
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#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
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/* 1st Group of Advanced Bit Manipulation Extensions */
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#define CPUID_7_0_EBX_BMI1 (1U << 3)
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/* Hardware Lock Elision */
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#define CPUID_7_0_EBX_HLE (1U << 4)
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/* Intel Advanced Vector Extensions 2 */
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#define CPUID_7_0_EBX_AVX2 (1U << 5)
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/* Supervisor-mode Execution Prevention */
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#define CPUID_7_0_EBX_SMEP (1U << 7)
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/* 2nd Group of Advanced Bit Manipulation Extensions */
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#define CPUID_7_0_EBX_BMI2 (1U << 8)
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/* Enhanced REP MOVSB/STOSB */
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#define CPUID_7_0_EBX_ERMS (1U << 9)
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/* Invalidate Process-Context Identifier */
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#define CPUID_7_0_EBX_INVPCID (1U << 10)
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/* Restricted Transactional Memory */
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#define CPUID_7_0_EBX_RTM (1U << 11)
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/* Memory Protection Extension */
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#define CPUID_7_0_EBX_MPX (1U << 14)
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/* AVX-512 Foundation */
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#define CPUID_7_0_EBX_AVX512F (1U << 16)
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/* AVX-512 Doubleword & Quadword Instruction */
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#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
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/* Read Random SEED */
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#define CPUID_7_0_EBX_RDSEED (1U << 18)
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/* ADCX and ADOX instructions */
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#define CPUID_7_0_EBX_ADX (1U << 19)
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/* Supervisor Mode Access Prevention */
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#define CPUID_7_0_EBX_SMAP (1U << 20)
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/* AVX-512 Integer Fused Multiply Add */
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#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
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/* Persistent Commit */
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#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
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/* Flush a Cache Line Optimized */
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#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
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/* Cache Line Write Back */
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#define CPUID_7_0_EBX_CLWB (1U << 24)
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/* Intel Processor Trace */
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#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
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/* AVX-512 Prefetch */
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#define CPUID_7_0_EBX_AVX512PF (1U << 26)
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/* AVX-512 Exponential and Reciprocal */
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#define CPUID_7_0_EBX_AVX512ER (1U << 27)
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/* AVX-512 Conflict Detection */
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#define CPUID_7_0_EBX_AVX512CD (1U << 28)
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/* SHA1/SHA256 Instruction Extensions */
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#define CPUID_7_0_EBX_SHA_NI (1U << 29)
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/* AVX-512 Byte and Word Instructions */
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#define CPUID_7_0_EBX_AVX512BW (1U << 30)
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/* AVX-512 Vector Length Extensions */
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#define CPUID_7_0_EBX_AVX512VL (1U << 31)
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#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
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#define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */
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#define CPUID_7_0_ECX_UMIP (1U << 2)
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#define CPUID_7_0_ECX_PKU (1U << 3)
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#define CPUID_7_0_ECX_OSPKE (1U << 4)
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#define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
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#define CPUID_7_0_ECX_GFNI (1U << 8)
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#define CPUID_7_0_ECX_VAES (1U << 9)
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#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
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#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
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#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
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#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
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#define CPUID_7_0_ECX_LA57 (1U << 16)
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#define CPUID_7_0_ECX_RDPID (1U << 22)
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#define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */
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#define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */
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#define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */
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/* AVX-512 Vector Byte Manipulation Instruction */
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#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
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#define CPUID_7_0_ECX_VBMI (1U << 1)
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/* User-Mode Instruction Prevention */
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#define CPUID_7_0_ECX_UMIP (1U << 2)
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/* Protection Keys for User-mode Pages */
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#define CPUID_7_0_ECX_PKU (1U << 3)
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/* OS Enable Protection Keys */
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#define CPUID_7_0_ECX_OSPKE (1U << 4)
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/* Additional AVX-512 Vector Byte Manipulation Instruction */
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#define CPUID_7_0_ECX_VBMI2 (1U << 6)
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/* Galois Field New Instructions */
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#define CPUID_7_0_ECX_GFNI (1U << 8)
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/* Vector AES Instructions */
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#define CPUID_7_0_ECX_VAES (1U << 9)
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/* Carry-Less Multiplication Quadword */
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#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
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/* Vector Neural Network Instructions */
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#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
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/* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
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#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
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/* POPCNT for vectors of DW/QW */
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#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
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/* 5-level Page Tables */
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#define CPUID_7_0_ECX_LA57 (1U << 16)
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/* Read Processor ID */
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#define CPUID_7_0_ECX_RDPID (1U << 22)
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/* Cache Line Demote Instruction */
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#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
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/* Move Doubleword as Direct Store Instruction */
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#define CPUID_7_0_ECX_MOVDIRI (1U << 27)
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/* Move 64 Bytes as Direct Store Instruction */
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#define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
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#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
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#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
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#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
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#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capability*/
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#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
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/* AVX512 Neural Network Instructions */
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#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
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/* AVX512 Multiply Accumulation Single Precision */
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#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
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/* Speculation Control */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
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/* Arch Capabilities */
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#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
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/* Core Capability */
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#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
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/* Speculative Store Bypass Disable */
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#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
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#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction */
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/* AVX512 BFloat16 Instruction */
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#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
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#define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* CLZERO instruction */
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#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */
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#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
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do not invalidate cache */
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#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
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/* CLZERO instruction */
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#define CPUID_8000_0008_EBX_CLZERO (1U << 0)
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/* Always save/restore FP error pointers */
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#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
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/* Write back and do not invalidate cache */
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#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
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/* Indirect Branch Prediction Barrier */
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#define CPUID_8000_0008_EBX_IBPB (1U << 12)
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#define CPUID_XSAVE_XSAVEOPT (1U << 0)
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#define CPUID_XSAVE_XSAVEC (1U << 1)
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