target/riscv: Fix manually parsed 16 bit insn
during the refactor to decodetree we removed the manual decoding that is necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld and c.fsw/c.sd. This reintroduces the manual parsing and the omited implementation. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Tested-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
parent
d4e65539e5
commit
f330433b36
@ -44,10 +44,19 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
|
||||
{
|
||||
#ifdef TARGET_RISCV32
|
||||
/* C.FLW ( RV32FC-only ) */
|
||||
return false;
|
||||
REQUIRE_FPU;
|
||||
REQUIRE_EXT(ctx, RVF);
|
||||
|
||||
arg_c_lw tmp;
|
||||
decode_insn16_extract_cl_w(&tmp, ctx->opcode);
|
||||
arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
|
||||
return trans_flw(ctx, &arg);
|
||||
#else
|
||||
/* C.LD ( RV64C/RV128C-only ) */
|
||||
return false;
|
||||
arg_c_fld tmp;
|
||||
decode_insn16_extract_cl_d(&tmp, ctx->opcode);
|
||||
arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
|
||||
return trans_ld(ctx, &arg);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -67,10 +76,19 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
|
||||
{
|
||||
#ifdef TARGET_RISCV32
|
||||
/* C.FSW ( RV32FC-only ) */
|
||||
return false;
|
||||
REQUIRE_FPU;
|
||||
REQUIRE_EXT(ctx, RVF);
|
||||
|
||||
arg_c_sw tmp;
|
||||
decode_insn16_extract_cs_w(&tmp, ctx->opcode);
|
||||
arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
|
||||
return trans_fsw(ctx, &arg);
|
||||
#else
|
||||
/* C.SD ( RV64C/RV128C-only ) */
|
||||
return false;
|
||||
arg_c_fsd tmp;
|
||||
decode_insn16_extract_cs_d(&tmp, ctx->opcode);
|
||||
arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
|
||||
return trans_sd(ctx, &arg);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -88,7 +106,9 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
|
||||
{
|
||||
#ifdef TARGET_RISCV32
|
||||
/* C.JAL */
|
||||
arg_jal arg = { .rd = 1, .imm = a->imm };
|
||||
arg_c_j tmp;
|
||||
decode_insn16_extract_cj(&tmp, ctx->opcode);
|
||||
arg_jal arg = { .rd = 1, .imm = tmp.imm };
|
||||
return trans_jal(ctx, &arg);
|
||||
#else
|
||||
/* C.ADDIW */
|
||||
|
Loading…
Reference in New Issue
Block a user