hw/pci-host/astro: Implement Hard Fail and Soft Fail mode
The Astro/Elroy chip can work in either Hard-Fail or Soft-Fail mode. Hard fail means the system bus will send an HPMC (=crash) to the processor, soft fail means the system bus will ignore timeouts of MMIO-reads or MMIO-writes and return -1ULL. The HF mode is controlled by a bit in the status register and is usually programmed by the OS. Return the corresponing values based on the current value of that bit. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -131,15 +131,21 @@ static MemTxResult elroy_chip_read_with_attrs(void *opaque, hwaddr addr,
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if (s->iosapic_reg_select < ARRAY_SIZE(s->iosapic_reg)) {
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val = s->iosapic_reg[s->iosapic_reg_select];
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} else {
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val = 0;
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ret = MEMTX_DECODE_ERROR;
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goto check_hf;
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}
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}
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trace_iosapic_reg_read(s->iosapic_reg_select, size, val);
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break;
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default:
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val = 0;
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ret = MEMTX_DECODE_ERROR;
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check_hf:
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if (s->status_control & HF_ENABLE) {
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val = 0;
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ret = MEMTX_DECODE_ERROR;
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} else {
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/* return -1ULL if HardFail is disabled */
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val = ~0;
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ret = MEMTX_OK;
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}
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}
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trace_elroy_read(addr, size, val);
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@ -187,7 +193,7 @@ static MemTxResult elroy_chip_write_with_attrs(void *opaque, hwaddr addr,
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if (s->iosapic_reg_select < ARRAY_SIZE(s->iosapic_reg)) {
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s->iosapic_reg[s->iosapic_reg_select] = val;
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} else {
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return MEMTX_DECODE_ERROR;
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goto check_hf;
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}
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break;
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case 0x0840: /* IOSAPIC_REG_EOI */
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@ -200,7 +206,10 @@ static MemTxResult elroy_chip_write_with_attrs(void *opaque, hwaddr addr,
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}
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break;
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default:
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return MEMTX_DECODE_ERROR;
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check_hf:
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if (s->status_control & HF_ENABLE) {
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return MEMTX_DECODE_ERROR;
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}
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}
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return MEMTX_OK;
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}
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@ -27,6 +27,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ElroyState, ELROY_PCI_HOST_BRIDGE)
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#define IOS_DIST_BASE_ADDR 0xfffee00000ULL
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#define IOS_DIST_BASE_SIZE 0x10000ULL
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#define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
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struct AstroState;
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struct ElroyState {
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