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target-arm queue: 

* fpu: Fix rounding mode for floatN_to_uintM_round_to_zero
  * tcg: Fix guest state corruption when running 64-bit Arm
    guests on a 32-bit host (especially when using icount)
  * linux-user/signal.c: Ensure AArch64 signal frame isn't too small
  * cpus.c: ensure running CPU recalculates icount deadlines on timer expiry
  * target/arm: Report unsupported MPU region sizes more clearly
  * hw/arm/fsl-imx: Fix introspection problem with fsl-imx6 and fsl-imx7
  * hw/arm/allwinner-a10: Do not use nd_table in instance_init function
  * hw/sd/bcm2835_sdhost: Don't raise spurious interrupts
  * hw/sd/bcm2835_sdhost: Add tracepoints
  * target-arm: Check undefined opcodes for SWP in A32 decoder
  * hw/arm/integratorcp: Don't do things that could be fatal in the instance_init
  * hw/arm: Allow manually specified /psci node
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180410' into staging

target-arm queue:
 * fpu: Fix rounding mode for floatN_to_uintM_round_to_zero
 * tcg: Fix guest state corruption when running 64-bit Arm
   guests on a 32-bit host (especially when using icount)
 * linux-user/signal.c: Ensure AArch64 signal frame isn't too small
 * cpus.c: ensure running CPU recalculates icount deadlines on timer expiry
 * target/arm: Report unsupported MPU region sizes more clearly
 * hw/arm/fsl-imx: Fix introspection problem with fsl-imx6 and fsl-imx7
 * hw/arm/allwinner-a10: Do not use nd_table in instance_init function
 * hw/sd/bcm2835_sdhost: Don't raise spurious interrupts
 * hw/sd/bcm2835_sdhost: Add tracepoints
 * target-arm: Check undefined opcodes for SWP in A32 decoder
 * hw/arm/integratorcp: Don't do things that could be fatal in the instance_init
 * hw/arm: Allow manually specified /psci node

# gpg: Signature made Tue 10 Apr 2018 13:16:12 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180410:
  fpu: Fix rounding mode for floatN_to_uintM_round_to_zero
  tcg: Introduce tcg_set_insn_start_param
  linux-user/signal.c: Ensure AArch64 signal frame isn't too small
  cpus.c: ensure running CPU recalculates icount deadlines on timer expiry
  target/arm: Report unsupported MPU region sizes more clearly
  hw/arm/fsl-imx: Fix introspection problem with fsl-imx6 and fsl-imx7
  hw/arm/allwinner-a10: Do not use nd_table in instance_init function
  hw/sd/bcm2835_sdhost: Don't raise spurious interrupts
  hw/sd/bcm2835_sdhost: Add tracepoints
  target-arm: Check undefined opcodes for SWP in A32 decoder
  hw/arm/integratorcp: Don't do things that could be fatal in the instance_init
  hw/arm: Allow manually specified /psci node

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-04-10 15:18:58 +01:00
parent df6378eb0e bd49e6027c
commit f41ee66df0
14 changed files with 124 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
cpus.c
View File

@ -892,11 +892,19 @@ void qemu_timer_notify_cb(void *opaque, QEMUClockType type)
return;
}
if (!qemu_in_vcpu_thread() && first_cpu) {
if (qemu_in_vcpu_thread()) {
/* A CPU is currently running; kick it back out to the
* tcg_cpu_exec() loop so it will recalculate its
* icount deadline immediately.
*/
qemu_cpu_kick(current_cpu);
} else if (first_cpu) {
/* qemu_cpu_kick is not enough to kick a halted CPU out of
* qemu_tcg_wait_io_event. async_run_on_cpu, instead,
* causes cpu_thread_is_idle to return false. This way,
* handle_icount_deadline can run.
* If we have no CPUs at all for some reason, we don't
* need to do anything.
*/
async_run_on_cpu(first_cpu, do_nothing, RUN_ON_CPU_NULL);
}

4
fpu/softfloat.c
View File

@ -1486,8 +1486,8 @@ uint ## isz ## _t float ## fsz ## _to_uint ## isz ## _round_to_zero \
(float ## fsz a, float_status *s) \
{ \
FloatParts p = float ## fsz ## _unpack_canonical(a, s); \
return round_to_uint_and_pack(p, s->float_rounding_mode, \
UINT ## isz ## _MAX, s); \
return round_to_uint_and_pack(p, float_round_to_zero, \
UINT ## isz ## _MAX, s); \
}
FLOAT_TO_UINT(16, 16)

12
hw/arm/allwinner-a10.c
View File

@ -38,11 +38,6 @@ static void aw_a10_init(Object *obj)
object_initialize(&s->emac, sizeof(s->emac), TYPE_AW_EMAC);
qdev_set_parent_bus(DEVICE(&s->emac), sysbus_get_default());
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI);
qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
@ -91,6 +86,11 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
@ -118,7 +118,7 @@ static void aw_a10_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = aw_a10_realize;
/* Reason: Uses serial_hds in realize and nd_table in instance_init */
/* Reason: Uses serial_hds and nd_table in realize function */
dc->user_creatable = false;
}

10
hw/arm/boot.c
View File

@ -422,6 +422,7 @@ static void fdt_add_psci_node(void *fdt)
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
const char *psci_method;
int64_t psci_conduit;
int rc;
psci_conduit = object_property_get_int(OBJECT(armcpu),
"psci-conduit",
@ -439,6 +440,15 @@ static void fdt_add_psci_node(void *fdt)
g_assert_not_reached();
}
/*
* If /psci node is present in provided DTB, assume that no fixup
* is necessary and all PSCI configuration should be taken as-is
*/
rc = fdt_path_offset(fdt, "/psci");
if (rc >= 0) {
return;
}
qemu_fdt_add_subnode(fdt, "/psci");
if (armcpu->psci_version == 2) {
const char comp[] = "arm,psci-0.2\0arm,psci";

14
hw/arm/fsl-imx6.c
View File

@ -37,13 +37,7 @@ static void fsl_imx6_init(Object *obj)
char name[NAME_SIZE];
int i;
if (smp_cpus > FSL_IMX6_NUM_CPUS) {
error_report("%s: Only %d CPUs are supported (%d requested)",
TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
exit(1);
}
for (i = 0; i < smp_cpus; i++) {
for (i = 0; i < MIN(smp_cpus, FSL_IMX6_NUM_CPUS); i++) {
object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
"cortex-a9-" TYPE_ARM_CPU);
snprintf(name, NAME_SIZE, "cpu%d", i);
@ -119,6 +113,12 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
uint16_t i;
Error *err = NULL;
if (smp_cpus > FSL_IMX6_NUM_CPUS) {
error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
return;
}
for (i = 0; i < smp_cpus; i++) {
/* On uniprocessor, the CBAR is set to 0 */

13
hw/arm/fsl-imx7.c
View File

@ -35,13 +35,8 @@ static void fsl_imx7_init(Object *obj)
char name[NAME_SIZE];
int i;
if (smp_cpus > FSL_IMX7_NUM_CPUS) {
error_report("%s: Only %d CPUs are supported (%d requested)",
TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
exit(1);
}
for (i = 0; i < smp_cpus; i++) {
for (i = 0; i < MIN(smp_cpus, FSL_IMX7_NUM_CPUS); i++) {
object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
ARM_CPU_TYPE_NAME("cortex-a7"));
snprintf(name, NAME_SIZE, "cpu%d", i);
@ -197,6 +192,12 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
qemu_irq irq;
char name[NAME_SIZE];
if (smp_cpus > FSL_IMX7_NUM_CPUS) {
error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
return;
}
for (i = 0; i < smp_cpus; i++) {
o = OBJECT(&s->cpu[i]);

23
hw/arm/integratorcp.c
View File

@ -266,7 +266,6 @@ static const MemoryRegionOps integratorcm_ops = {
static void integratorcm_init(Object *obj)
{
IntegratorCMState *s = INTEGRATOR_CM(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
s->cm_osc = 0x01000048;
/* ??? What should the high bits of this value be? */
@ -276,20 +275,28 @@ static void integratorcm_init(Object *obj)
s->cm_init = 0x00000112;
s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
1000);
memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000,
&error_fatal);
memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s,
"integratorcm", 0x00800000);
sysbus_init_mmio(dev, &s->iomem);
integratorcm_do_remap(s);
/* ??? Save/restore. */
}
static void integratorcm_realize(DeviceState *d, Error **errp)
{
IntegratorCMState *s = INTEGRATOR_CM(d);
SysBusDevice *dev = SYS_BUS_DEVICE(d);
Error *local_err = NULL;
memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000,
&local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s,
"integratorcm", 0x00800000);
sysbus_init_mmio(dev, &s->iomem);
integratorcm_do_remap(s);
if (s->memsz >= 256) {
integrator_spd[31] = 64;

54
hw/sd/bcm2835_sdhost.c
View File

@ -15,6 +15,7 @@
#include "qemu/log.h"
#include "sysemu/blockdev.h"
#include "hw/sd/bcm2835_sdhost.h"
#include "trace.h"
#define TYPE_BCM2835_SDHOST_BUS "bcm2835-sdhost-bus"
#define BCM2835_SDHOST_BUS(obj) \
@ -99,6 +100,7 @@ static void bcm2835_sdhost_update_irq(BCM2835SDHostState *s)
{
uint32_t irq = s->status &
(SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | SDHSTS_SDIO_IRPT);
trace_bcm2835_sdhost_update_irq(irq);
qemu_set_irq(s->irq, !!irq);
}
@ -135,6 +137,12 @@ static void bcm2835_sdhost_send_command(BCM2835SDHostState *s)
}
#undef RWORD
}
/* We never really delay commands, so if this was a 'busywait' command
* then we've completed it now and can raise the interrupt.
*/
if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) {
s->status |= SDHSTS_BUSY_IRPT;
}
return;
error:
@ -185,18 +193,27 @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
n++;
if (n == 4) {
bcm2835_sdhost_fifo_push(s, value);
s->status |= SDHSTS_DATA_FLAG;
if (s->config & SDHCFG_DATA_IRPT_EN) {
s->status |= SDHSTS_SDIO_IRPT;
}
n = 0;
value = 0;
}
}
if (n != 0) {
bcm2835_sdhost_fifo_push(s, value);
s->status |= SDHSTS_DATA_FLAG;
}
} else { /* write */
n = 0;
while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) {
if (n == 0) {
value = bcm2835_sdhost_fifo_pop(s);
s->status |= SDHSTS_DATA_FLAG;
if (s->config & SDHCFG_DATA_IRPT_EN) {
s->status |= SDHSTS_SDIO_IRPT;
}
n = 4;
}
n--;
@ -205,30 +222,23 @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
value >>= 8;
}
}
if (s->datacnt == 0) {
s->edm &= ~SDEDM_FSM_MASK;
s->edm |= SDEDM_FSM_DATAMODE;
trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm);
if ((s->cmd & SDCMD_WRITE_CMD) &&
(s->config & SDHCFG_BLOCK_IRPT_EN)) {
s->status |= SDHSTS_BLOCK_IRPT;
}
}
}
if (s->datacnt == 0) {
s->status |= SDHSTS_DATA_FLAG;
s->edm &= ~0xf;
s->edm |= SDEDM_FSM_DATAMODE;
if (s->config & SDHCFG_DATA_IRPT_EN) {
s->status |= SDHSTS_SDIO_IRPT;
}
if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) {
s->status |= SDHSTS_BUSY_IRPT;
}
if ((s->cmd & SDCMD_WRITE_CMD) && (s->config & SDHCFG_BLOCK_IRPT_EN)) {
s->status |= SDHSTS_BLOCK_IRPT;
}
bcm2835_sdhost_update_irq(s);
}
bcm2835_sdhost_update_irq(s);
s->edm &= ~(0x1f << 4);
s->edm |= ((s->fifo_len & 0x1f) << 4);
trace_bcm2835_sdhost_edm_change("fifo run", s->edm);
}
static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset,
@ -280,6 +290,8 @@ static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset,
break;
}
trace_bcm2835_sdhost_read(offset, res, size);
return res;
}
@ -288,6 +300,8 @@ static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
{
BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
trace_bcm2835_sdhost_write(offset, value, size);
switch (offset) {
case SDCMD:
s->cmd = value;
@ -314,6 +328,7 @@ static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
value &= ~0xf;
}
s->edm = value;
trace_bcm2835_sdhost_edm_change("guest register write", s->edm);
break;
case SDHCFG:
s->config = value;
@ -390,6 +405,7 @@ static void bcm2835_sdhost_reset(DeviceState *dev)
s->cmd = 0;
s->cmdarg = 0;
s->edm = 0x0000c60f;
trace_bcm2835_sdhost_edm_change("device reset", s->edm);
s->config = 0;
s->hbct = 0;
s->hblc = 0;

6
hw/sd/trace-events
View File

@ -1,5 +1,11 @@
# See docs/devel/tracing.txt for syntax documentation.
# hw/sd/bcm2835_sdhost.c
bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
bcm2835_sdhost_edm_change(const char *why, uint32_t edm) "(%s) EDM now 0x%x"
bcm2835_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x\n"
# hw/sd/core.c
sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg, uint8_t crc) "@%s CMD%02d arg 0x%08x crc 0x%02x"
sdbus_read(const char *bus_name, uint8_t value) "@%s value 0x%02x"

6
linux-user/signal.c
View File

@ -1850,6 +1850,12 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
fr_ofs = layout.total_size;
layout.total_size += sizeof(struct target_rt_frame_record);
/* We must always provide at least the standard 4K reserved space,
* even if we don't use all of it (this is part of the ABI)
*/
layout.total_size = MAX(layout.total_size,
sizeof(struct target_rt_sigframe));
frame_addr = get_sigframe(ka, env, layout.total_size);
trace_user_setup_frame(env, frame_addr);
if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {

6
target/arm/helper.c
View File

@ -9625,9 +9625,9 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
}
if (rsize < TARGET_PAGE_BITS) {
qemu_log_mask(LOG_UNIMP,
"DRSR[%d]: No support for MPU (sub)region "
"alignment of %" PRIu32 " bits. Minimum is %d\n",
n, rsize, TARGET_PAGE_BITS);
"DRSR[%d]: No support for MPU (sub)region size of"
" %" PRIu32 " bytes. Minimum is %d.\n",
n, (1 << rsize), TARGET_PAGE_SIZE);
continue;
}
if (srdis) {

9
target/arm/translate.c
View File

@ -9237,11 +9237,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
}
tcg_temp_free_i32(addr);
} else {
} else if ((insn & 0x00300f00) == 0) {
/* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
* - SWP, SWPB
*/
TCGv taddr;
TCGMemOp opc = s->be_data;
/* SWP instruction */
rm = (insn) & 0xf;
if (insn & (1 << 22)) {
@ -9259,6 +9262,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
get_mem_index(s), opc);
tcg_temp_free(taddr);
store_reg(s, rd, tmp);
} else {
goto illegal_op;
}
}
} else {

2
target/arm/translate.h
View File

@ -120,7 +120,7 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
/* We check and clear insn_start_idx to catch multiple updates. */
assert(s->insn_start != NULL);
tcg_set_insn_param(s->insn_start, 2, syn);
tcg_set_insn_start_param(s->insn_start, 2, syn);
s->insn_start = NULL;
}

10
tcg/tcg.h
View File

@ -825,6 +825,16 @@ static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
op->args[arg] = v;
}
static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
{
#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
tcg_set_insn_param(op, arg, v);
#else
tcg_set_insn_param(op, arg * 2, v);
tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
#endif
}
/* The last op that was emitted. */
static inline TCGOp *tcg_last_op(void)
{