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target/mips: Fix TCG temporary leak in gen_cache_operation() 

Fix a TCG temporary leak when translating CACHE opcode.

Fixes: 0d74a222c2 ("make ITC Configuration Tags accessible to the CPU")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210406202857.1440744-1-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-04-06 22:26:21 +02:00
parent 62271205bc
commit f4349ba966
1 changed files with 2 additions and 0 deletions
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2
target/mips/translate.c
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@ -12804,6 +12804,8 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
TCGv t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t1, base, offset);
gen_helper_cache(cpu_env, t1, t0);
tcg_temp_free(t1);
tcg_temp_free_i32(t0);
}
#if defined(TARGET_MIPS64)