target/arm: Move define_debug_regs() to debug_helper.c
The target/arm/helper.c file is very long and is a grabbag of all kinds of functionality. We have already a debug_helper.c which has code for implementing architectural debug. Move the code which defines the debug-related system registers out to this file also. This affects the define_debug_regs() function and the various functions and arrays which are used only by it. The functions raw_write() and arm_mdcr_el2_eff() and define_debug_regs() now need to be global rather than local to helper.c; everything else is pure code movement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220630194116.3438513-3-peter.maydell@linaro.org
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@ -442,6 +442,9 @@ void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
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/* CPReadFn that can be used for read-as-zero behaviour */
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uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
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/* CPWriteFn that just writes the value to ri->fieldoffset */
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void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value);
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/*
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* CPResetFn that does nothing, for use if no reset is required even
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* if fieldoffset is non zero.
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@ -6,8 +6,10 @@
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "internals.h"
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#include "cpregs.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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@ -528,6 +530,529 @@ void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
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raise_exception_debug(env, EXCP_UDEF, syndrome);
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}
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/*
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* Check for traps to "powerdown debug" registers, which are controlled
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* by MDCR.TDOSA
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*/
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static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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int el = arm_current_el(env);
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uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
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bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) ||
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(arm_hcr_el2_eff(env) & HCR_TGE);
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if (el < 2 && mdcr_el2_tdosa) {
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return CP_ACCESS_TRAP_EL2;
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}
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if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
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return CP_ACCESS_TRAP_EL3;
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}
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return CP_ACCESS_OK;
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}
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/*
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* Check for traps to "debug ROM" registers, which are controlled
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* by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
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*/
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static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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int el = arm_current_el(env);
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uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
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bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) ||
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(arm_hcr_el2_eff(env) & HCR_TGE);
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if (el < 2 && mdcr_el2_tdra) {
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return CP_ACCESS_TRAP_EL2;
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}
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if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
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return CP_ACCESS_TRAP_EL3;
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}
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return CP_ACCESS_OK;
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}
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/*
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* Check for traps to general debug registers, which are controlled
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* by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
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*/
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static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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int el = arm_current_el(env);
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uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
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bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
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(arm_hcr_el2_eff(env) & HCR_TGE);
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if (el < 2 && mdcr_el2_tda) {
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return CP_ACCESS_TRAP_EL2;
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}
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if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
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return CP_ACCESS_TRAP_EL3;
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}
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return CP_ACCESS_OK;
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}
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static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/*
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* Writes to OSLAR_EL1 may update the OS lock status, which can be
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* read via a bit in OSLSR_EL1.
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*/
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int oslock;
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if (ri->state == ARM_CP_STATE_AA32) {
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oslock = (value == 0xC5ACCE55);
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} else {
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oslock = value & 1;
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}
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env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
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}
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static const ARMCPRegInfo debug_cp_reginfo[] = {
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/*
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* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
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* debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
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* unlike DBGDRAR it is never accessible from EL0.
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* DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
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* accessor.
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*/
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{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL0_R, .accessfn = access_tdra,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
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.access = PL1_R, .accessfn = access_tdra,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL0_R, .accessfn = access_tdra,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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/* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
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{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
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.access = PL1_RW, .accessfn = access_tda,
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.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
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.resetvalue = 0 },
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/*
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* MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external
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* Debug Communication Channel is not implemented.
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*/
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{ .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
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.access = PL0_R, .accessfn = access_tda,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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/*
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* DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
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* it is unlikely a guest will care.
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* We don't implement the configurable EL0 access.
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*/
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{ .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
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.cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
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.type = ARM_CP_ALIAS,
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.access = PL1_R, .accessfn = access_tda,
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.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
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{ .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.accessfn = access_tdosa,
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.writefn = oslar_write },
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{ .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
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.access = PL1_R, .resetvalue = 10,
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.accessfn = access_tdosa,
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.fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
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/* Dummy OSDLR_EL1: 32-bit Linux will read this */
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{ .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
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.access = PL1_RW, .accessfn = access_tdosa,
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.type = ARM_CP_NOP },
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/*
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* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
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* implement vector catch debug events yet.
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*/
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{ .name = "DBGVCR",
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.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tda,
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.type = ARM_CP_NOP },
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/*
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* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
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* to save and restore a 32-bit guest's DBGVCR)
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*/
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{ .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
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.access = PL2_RW, .accessfn = access_tda,
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.type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
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/*
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* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
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* Channel but Linux may try to access this register. The 32-bit
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* alias is DBGDCCINT.
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*/
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{ .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tda,
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.type = ARM_CP_NOP },
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};
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static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
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/* 64 bit access versions of the (dummy) debug registers */
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{ .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
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.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
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.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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};
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void hw_watchpoint_update(ARMCPU *cpu, int n)
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{
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CPUARMState *env = &cpu->env;
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vaddr len = 0;
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vaddr wvr = env->cp15.dbgwvr[n];
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uint64_t wcr = env->cp15.dbgwcr[n];
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int mask;
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int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
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if (env->cpu_watchpoint[n]) {
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cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
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env->cpu_watchpoint[n] = NULL;
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}
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if (!FIELD_EX64(wcr, DBGWCR, E)) {
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/* E bit clear : watchpoint disabled */
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return;
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}
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switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
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case 0:
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/* LSC 00 is reserved and must behave as if the wp is disabled */
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return;
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case 1:
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flags |= BP_MEM_READ;
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break;
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case 2:
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flags |= BP_MEM_WRITE;
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break;
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case 3:
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flags |= BP_MEM_ACCESS;
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break;
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}
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/*
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* Attempts to use both MASK and BAS fields simultaneously are
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* CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
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* thus generating a watchpoint for every byte in the masked region.
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*/
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mask = FIELD_EX64(wcr, DBGWCR, MASK);
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if (mask == 1 || mask == 2) {
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/*
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* Reserved values of MASK; we must act as if the mask value was
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* some non-reserved value, or as if the watchpoint were disabled.
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* We choose the latter.
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*/
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return;
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} else if (mask) {
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/* Watchpoint covers an aligned area up to 2GB in size */
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len = 1ULL << mask;
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/*
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* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
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* whether the watchpoint fires when the unmasked bits match; we opt
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* to generate the exceptions.
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*/
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wvr &= ~(len - 1);
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} else {
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/* Watchpoint covers bytes defined by the byte address select bits */
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int bas = FIELD_EX64(wcr, DBGWCR, BAS);
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int basstart;
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if (extract64(wvr, 2, 1)) {
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/*
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* Deprecated case of an only 4-aligned address. BAS[7:4] are
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* ignored, and BAS[3:0] define which bytes to watch.
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*/
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bas &= 0xf;
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}
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if (bas == 0) {
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/* This must act as if the watchpoint is disabled */
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return;
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}
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/*
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* The BAS bits are supposed to be programmed to indicate a contiguous
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* range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
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* we fire for each byte in the word/doubleword addressed by the WVR.
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* We choose to ignore any non-zero bits after the first range of 1s.
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*/
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basstart = ctz32(bas);
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len = cto32(bas >> basstart);
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wvr += basstart;
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}
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cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
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&env->cpu_watchpoint[n]);
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}
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void hw_watchpoint_update_all(ARMCPU *cpu)
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{
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int i;
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CPUARMState *env = &cpu->env;
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/*
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* Completely clear out existing QEMU watchpoints and our array, to
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* avoid possible stale entries following migration load.
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*/
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cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
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memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
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for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
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hw_watchpoint_update(cpu, i);
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}
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}
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static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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ARMCPU *cpu = env_archcpu(env);
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int i = ri->crm;
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/*
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* Bits [1:0] are RES0.
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*
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* It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
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* are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
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* they contain the value written. It is CONSTRAINED UNPREDICTABLE
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* whether the RESS bits are ignored when comparing an address.
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*
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* Therefore we are allowed to compare the entire register, which lets
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* us avoid considering whether or not FEAT_LVA is actually enabled.
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*/
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value &= ~3ULL;
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raw_write(env, ri, value);
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hw_watchpoint_update(cpu, i);
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}
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static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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ARMCPU *cpu = env_archcpu(env);
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int i = ri->crm;
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raw_write(env, ri, value);
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hw_watchpoint_update(cpu, i);
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}
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void hw_breakpoint_update(ARMCPU *cpu, int n)
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{
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CPUARMState *env = &cpu->env;
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uint64_t bvr = env->cp15.dbgbvr[n];
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uint64_t bcr = env->cp15.dbgbcr[n];
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vaddr addr;
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int bt;
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int flags = BP_CPU;
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if (env->cpu_breakpoint[n]) {
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cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
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env->cpu_breakpoint[n] = NULL;
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}
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if (!extract64(bcr, 0, 1)) {
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/* E bit clear : watchpoint disabled */
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return;
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}
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bt = extract64(bcr, 20, 4);
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switch (bt) {
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case 4: /* unlinked address mismatch (reserved if AArch64) */
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case 5: /* linked address mismatch (reserved if AArch64) */
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qemu_log_mask(LOG_UNIMP,
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"arm: address mismatch breakpoint types not implemented\n");
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return;
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case 0: /* unlinked address match */
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case 1: /* linked address match */
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{
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/*
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* Bits [1:0] are RES0.
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*
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* It is IMPLEMENTATION DEFINED whether bits [63:49]
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* ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
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* of the VA field ([48] or [52] for FEAT_LVA), or whether the
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* value is read as written. It is CONSTRAINED UNPREDICTABLE
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* whether the RESS bits are ignored when comparing an address.
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* Therefore we are allowed to compare the entire register, which
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* lets us avoid considering whether FEAT_LVA is actually enabled.
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*
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* The BAS field is used to allow setting breakpoints on 16-bit
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* wide instructions; it is CONSTRAINED UNPREDICTABLE whether
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* a bp will fire if the addresses covered by the bp and the addresses
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* covered by the insn overlap but the insn doesn't start at the
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* start of the bp address range. We choose to require the insn and
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* the bp to have the same address. The constraints on writing to
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* BAS enforced in dbgbcr_write mean we have only four cases:
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* 0b0000 => no breakpoint
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* 0b0011 => breakpoint on addr
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* 0b1100 => breakpoint on addr + 2
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* 0b1111 => breakpoint on addr
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* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
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*/
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int bas = extract64(bcr, 5, 4);
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addr = bvr & ~3ULL;
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if (bas == 0) {
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return;
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}
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if (bas == 0xc) {
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addr += 2;
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}
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break;
|
||||
}
|
||||
case 2: /* unlinked context ID match */
|
||||
case 8: /* unlinked VMID match (reserved if no EL2) */
|
||||
case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"arm: unlinked context breakpoint types not implemented\n");
|
||||
return;
|
||||
case 9: /* linked VMID match (reserved if no EL2) */
|
||||
case 11: /* linked context ID and VMID match (reserved if no EL2) */
|
||||
case 3: /* linked context ID match */
|
||||
default:
|
||||
/*
|
||||
* We must generate no events for Linked context matches (unless
|
||||
* they are linked to by some other bp/wp, which is handled in
|
||||
* updates for the linking bp/wp). We choose to also generate no events
|
||||
* for reserved values.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
|
||||
}
|
||||
|
||||
void hw_breakpoint_update_all(ARMCPU *cpu)
|
||||
{
|
||||
int i;
|
||||
CPUARMState *env = &cpu->env;
|
||||
|
||||
/*
|
||||
* Completely clear out existing QEMU breakpoints and our array, to
|
||||
* avoid possible stale entries following migration load.
|
||||
*/
|
||||
cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
|
||||
memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
|
||||
hw_breakpoint_update(cpu, i);
|
||||
}
|
||||
}
|
||||
|
||||
static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
ARMCPU *cpu = env_archcpu(env);
|
||||
int i = ri->crm;
|
||||
|
||||
raw_write(env, ri, value);
|
||||
hw_breakpoint_update(cpu, i);
|
||||
}
|
||||
|
||||
static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
ARMCPU *cpu = env_archcpu(env);
|
||||
int i = ri->crm;
|
||||
|
||||
/*
|
||||
* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
|
||||
* copy of BAS[0].
|
||||
*/
|
||||
value = deposit64(value, 6, 1, extract64(value, 5, 1));
|
||||
value = deposit64(value, 8, 1, extract64(value, 7, 1));
|
||||
|
||||
raw_write(env, ri, value);
|
||||
hw_breakpoint_update(cpu, i);
|
||||
}
|
||||
|
||||
void define_debug_regs(ARMCPU *cpu)
|
||||
{
|
||||
/*
|
||||
* Define v7 and v8 architectural debug registers.
|
||||
* These are just dummy implementations for now.
|
||||
*/
|
||||
int i;
|
||||
int wrps, brps, ctx_cmps;
|
||||
|
||||
/*
|
||||
* The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
|
||||
* use AArch32. Given that bit 15 is RES1, if the value is 0 then
|
||||
* the register must not exist for this cpu.
|
||||
*/
|
||||
if (cpu->isar.dbgdidr != 0) {
|
||||
ARMCPRegInfo dbgdidr = {
|
||||
.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
|
||||
.opc1 = 0, .opc2 = 0,
|
||||
.access = PL0_R, .accessfn = access_tda,
|
||||
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
|
||||
};
|
||||
define_one_arm_cp_reg(cpu, &dbgdidr);
|
||||
}
|
||||
|
||||
brps = arm_num_brps(cpu);
|
||||
wrps = arm_num_wrps(cpu);
|
||||
ctx_cmps = arm_num_ctx_cmps(cpu);
|
||||
|
||||
assert(ctx_cmps <= brps);
|
||||
|
||||
define_arm_cp_regs(cpu, debug_cp_reginfo);
|
||||
|
||||
if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
|
||||
define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
|
||||
}
|
||||
|
||||
for (i = 0; i < brps; i++) {
|
||||
char *dbgbvr_el1_name = g_strdup_printf("DBGBVR%d_EL1", i);
|
||||
char *dbgbcr_el1_name = g_strdup_printf("DBGBCR%d_EL1", i);
|
||||
ARMCPRegInfo dbgregs[] = {
|
||||
{ .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
|
||||
.writefn = dbgbvr_write, .raw_writefn = raw_write
|
||||
},
|
||||
{ .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
|
||||
.writefn = dbgbcr_write, .raw_writefn = raw_write
|
||||
},
|
||||
};
|
||||
define_arm_cp_regs(cpu, dbgregs);
|
||||
g_free(dbgbvr_el1_name);
|
||||
g_free(dbgbcr_el1_name);
|
||||
}
|
||||
|
||||
for (i = 0; i < wrps; i++) {
|
||||
char *dbgwvr_el1_name = g_strdup_printf("DBGWVR%d_EL1", i);
|
||||
char *dbgwcr_el1_name = g_strdup_printf("DBGWCR%d_EL1", i);
|
||||
ARMCPRegInfo dbgregs[] = {
|
||||
{ .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
|
||||
.writefn = dbgwvr_write, .raw_writefn = raw_write
|
||||
},
|
||||
{ .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
|
||||
.writefn = dbgwcr_write, .raw_writefn = raw_write
|
||||
},
|
||||
};
|
||||
define_arm_cp_regs(cpu, dbgregs);
|
||||
g_free(dbgwvr_el1_name);
|
||||
g_free(dbgwcr_el1_name);
|
||||
}
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
|
||||
|
|
|
@ -51,8 +51,7 @@ static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
|
|||
}
|
||||
}
|
||||
|
||||
static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
|
||||
{
|
||||
assert(ri->fieldoffset);
|
||||
if (cpreg_field_is_64bit(ri)) {
|
||||
|
@ -302,74 +301,6 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
|
|||
return CP_ACCESS_TRAP_UNCATEGORIZED;
|
||||
}
|
||||
|
||||
static uint64_t arm_mdcr_el2_eff(CPUARMState *env)
|
||||
{
|
||||
return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check for traps to "powerdown debug" registers, which are controlled
|
||||
* by MDCR.TDOSA
|
||||
*/
|
||||
static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
bool isread)
|
||||
{
|
||||
int el = arm_current_el(env);
|
||||
uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
|
||||
bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) ||
|
||||
(arm_hcr_el2_eff(env) & HCR_TGE);
|
||||
|
||||
if (el < 2 && mdcr_el2_tdosa) {
|
||||
return CP_ACCESS_TRAP_EL2;
|
||||
}
|
||||
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
|
||||
return CP_ACCESS_TRAP_EL3;
|
||||
}
|
||||
return CP_ACCESS_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check for traps to "debug ROM" registers, which are controlled
|
||||
* by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
|
||||
*/
|
||||
static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
bool isread)
|
||||
{
|
||||
int el = arm_current_el(env);
|
||||
uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
|
||||
bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) ||
|
||||
(arm_hcr_el2_eff(env) & HCR_TGE);
|
||||
|
||||
if (el < 2 && mdcr_el2_tdra) {
|
||||
return CP_ACCESS_TRAP_EL2;
|
||||
}
|
||||
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
|
||||
return CP_ACCESS_TRAP_EL3;
|
||||
}
|
||||
return CP_ACCESS_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check for traps to general debug registers, which are controlled
|
||||
* by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
|
||||
*/
|
||||
static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
bool isread)
|
||||
{
|
||||
int el = arm_current_el(env);
|
||||
uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
|
||||
bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
|
||||
(arm_hcr_el2_eff(env) & HCR_TGE);
|
||||
|
||||
if (el < 2 && mdcr_el2_tda) {
|
||||
return CP_ACCESS_TRAP_EL2;
|
||||
}
|
||||
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
|
||||
return CP_ACCESS_TRAP_EL3;
|
||||
}
|
||||
return CP_ACCESS_OK;
|
||||
}
|
||||
|
||||
/* Check for traps to performance monitor registers, which are controlled
|
||||
* by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
|
||||
*/
|
||||
|
@ -5982,116 +5913,6 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
|
|||
return CP_ACCESS_OK;
|
||||
}
|
||||
|
||||
static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
/*
|
||||
* Writes to OSLAR_EL1 may update the OS lock status, which can be
|
||||
* read via a bit in OSLSR_EL1.
|
||||
*/
|
||||
int oslock;
|
||||
|
||||
if (ri->state == ARM_CP_STATE_AA32) {
|
||||
oslock = (value == 0xC5ACCE55);
|
||||
} else {
|
||||
oslock = value & 1;
|
||||
}
|
||||
|
||||
env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
|
||||
}
|
||||
|
||||
static const ARMCPRegInfo debug_cp_reginfo[] = {
|
||||
/*
|
||||
* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
|
||||
* debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
|
||||
* unlike DBGDRAR it is never accessible from EL0.
|
||||
* DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
|
||||
* accessor.
|
||||
*/
|
||||
{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
|
||||
.access = PL0_R, .accessfn = access_tdra,
|
||||
.type = ARM_CP_CONST, .resetvalue = 0 },
|
||||
{ .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
|
||||
.access = PL1_R, .accessfn = access_tdra,
|
||||
.type = ARM_CP_CONST, .resetvalue = 0 },
|
||||
{ .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
|
||||
.access = PL0_R, .accessfn = access_tdra,
|
||||
.type = ARM_CP_CONST, .resetvalue = 0 },
|
||||
/* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
|
||||
{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
|
||||
.resetvalue = 0 },
|
||||
/*
|
||||
* MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external
|
||||
* Debug Communication Channel is not implemented.
|
||||
*/
|
||||
{ .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
|
||||
.access = PL0_R, .accessfn = access_tda,
|
||||
.type = ARM_CP_CONST, .resetvalue = 0 },
|
||||
/*
|
||||
* DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
|
||||
* it is unlikely a guest will care.
|
||||
* We don't implement the configurable EL0 access.
|
||||
*/
|
||||
{ .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
|
||||
.cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
|
||||
.type = ARM_CP_ALIAS,
|
||||
.access = PL1_R, .accessfn = access_tda,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
|
||||
{ .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
|
||||
.access = PL1_W, .type = ARM_CP_NO_RAW,
|
||||
.accessfn = access_tdosa,
|
||||
.writefn = oslar_write },
|
||||
{ .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
|
||||
.access = PL1_R, .resetvalue = 10,
|
||||
.accessfn = access_tdosa,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
|
||||
/* Dummy OSDLR_EL1: 32-bit Linux will read this */
|
||||
{ .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
|
||||
.access = PL1_RW, .accessfn = access_tdosa,
|
||||
.type = ARM_CP_NOP },
|
||||
/*
|
||||
* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
|
||||
* implement vector catch debug events yet.
|
||||
*/
|
||||
{ .name = "DBGVCR",
|
||||
.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.type = ARM_CP_NOP },
|
||||
/*
|
||||
* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
|
||||
* to save and restore a 32-bit guest's DBGVCR)
|
||||
*/
|
||||
{ .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
|
||||
.access = PL2_RW, .accessfn = access_tda,
|
||||
.type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
|
||||
/*
|
||||
* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
|
||||
* Channel but Linux may try to access this register. The 32-bit
|
||||
* alias is DBGDCCINT.
|
||||
*/
|
||||
{ .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.type = ARM_CP_NOP },
|
||||
};
|
||||
|
||||
static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
|
||||
/* 64 bit access versions of the (dummy) debug registers */
|
||||
{ .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
|
||||
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
|
||||
{ .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
|
||||
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
|
||||
};
|
||||
|
||||
/*
|
||||
* Check for traps to RAS registers, which are controlled
|
||||
* by HCR_EL2.TERR and SCR_EL3.TERR.
|
||||
|
@ -6470,356 +6291,6 @@ static const ARMCPRegInfo sme_reginfo[] = {
|
|||
};
|
||||
#endif /* TARGET_AARCH64 */
|
||||
|
||||
void hw_watchpoint_update(ARMCPU *cpu, int n)
|
||||
{
|
||||
CPUARMState *env = &cpu->env;
|
||||
vaddr len = 0;
|
||||
vaddr wvr = env->cp15.dbgwvr[n];
|
||||
uint64_t wcr = env->cp15.dbgwcr[n];
|
||||
int mask;
|
||||
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
|
||||
|
||||
if (env->cpu_watchpoint[n]) {
|
||||
cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
|
||||
env->cpu_watchpoint[n] = NULL;
|
||||
}
|
||||
|
||||
if (!FIELD_EX64(wcr, DBGWCR, E)) {
|
||||
/* E bit clear : watchpoint disabled */
|
||||
return;
|
||||
}
|
||||
|
||||
switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
|
||||
case 0:
|
||||
/* LSC 00 is reserved and must behave as if the wp is disabled */
|
||||
return;
|
||||
case 1:
|
||||
flags |= BP_MEM_READ;
|
||||
break;
|
||||
case 2:
|
||||
flags |= BP_MEM_WRITE;
|
||||
break;
|
||||
case 3:
|
||||
flags |= BP_MEM_ACCESS;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Attempts to use both MASK and BAS fields simultaneously are
|
||||
* CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
|
||||
* thus generating a watchpoint for every byte in the masked region.
|
||||
*/
|
||||
mask = FIELD_EX64(wcr, DBGWCR, MASK);
|
||||
if (mask == 1 || mask == 2) {
|
||||
/*
|
||||
* Reserved values of MASK; we must act as if the mask value was
|
||||
* some non-reserved value, or as if the watchpoint were disabled.
|
||||
* We choose the latter.
|
||||
*/
|
||||
return;
|
||||
} else if (mask) {
|
||||
/* Watchpoint covers an aligned area up to 2GB in size */
|
||||
len = 1ULL << mask;
|
||||
/*
|
||||
* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
|
||||
* whether the watchpoint fires when the unmasked bits match; we opt
|
||||
* to generate the exceptions.
|
||||
*/
|
||||
wvr &= ~(len - 1);
|
||||
} else {
|
||||
/* Watchpoint covers bytes defined by the byte address select bits */
|
||||
int bas = FIELD_EX64(wcr, DBGWCR, BAS);
|
||||
int basstart;
|
||||
|
||||
if (extract64(wvr, 2, 1)) {
|
||||
/*
|
||||
* Deprecated case of an only 4-aligned address. BAS[7:4] are
|
||||
* ignored, and BAS[3:0] define which bytes to watch.
|
||||
*/
|
||||
bas &= 0xf;
|
||||
}
|
||||
|
||||
if (bas == 0) {
|
||||
/* This must act as if the watchpoint is disabled */
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* The BAS bits are supposed to be programmed to indicate a contiguous
|
||||
* range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
|
||||
* we fire for each byte in the word/doubleword addressed by the WVR.
|
||||
* We choose to ignore any non-zero bits after the first range of 1s.
|
||||
*/
|
||||
basstart = ctz32(bas);
|
||||
len = cto32(bas >> basstart);
|
||||
wvr += basstart;
|
||||
}
|
||||
|
||||
cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
|
||||
&env->cpu_watchpoint[n]);
|
||||
}
|
||||
|
||||
void hw_watchpoint_update_all(ARMCPU *cpu)
|
||||
{
|
||||
int i;
|
||||
CPUARMState *env = &cpu->env;
|
||||
|
||||
/*
|
||||
* Completely clear out existing QEMU watchpoints and our array, to
|
||||
* avoid possible stale entries following migration load.
|
||||
*/
|
||||
cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
|
||||
memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
|
||||
hw_watchpoint_update(cpu, i);
|
||||
}
|
||||
}
|
||||
|
||||
static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
ARMCPU *cpu = env_archcpu(env);
|
||||
int i = ri->crm;
|
||||
|
||||
/*
|
||||
* Bits [1:0] are RES0.
|
||||
*
|
||||
* It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
|
||||
* are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
|
||||
* they contain the value written. It is CONSTRAINED UNPREDICTABLE
|
||||
* whether the RESS bits are ignored when comparing an address.
|
||||
*
|
||||
* Therefore we are allowed to compare the entire register, which lets
|
||||
* us avoid considering whether or not FEAT_LVA is actually enabled.
|
||||
*/
|
||||
value &= ~3ULL;
|
||||
|
||||
raw_write(env, ri, value);
|
||||
hw_watchpoint_update(cpu, i);
|
||||
}
|
||||
|
||||
static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
ARMCPU *cpu = env_archcpu(env);
|
||||
int i = ri->crm;
|
||||
|
||||
raw_write(env, ri, value);
|
||||
hw_watchpoint_update(cpu, i);
|
||||
}
|
||||
|
||||
void hw_breakpoint_update(ARMCPU *cpu, int n)
|
||||
{
|
||||
CPUARMState *env = &cpu->env;
|
||||
uint64_t bvr = env->cp15.dbgbvr[n];
|
||||
uint64_t bcr = env->cp15.dbgbcr[n];
|
||||
vaddr addr;
|
||||
int bt;
|
||||
int flags = BP_CPU;
|
||||
|
||||
if (env->cpu_breakpoint[n]) {
|
||||
cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
|
||||
env->cpu_breakpoint[n] = NULL;
|
||||
}
|
||||
|
||||
if (!extract64(bcr, 0, 1)) {
|
||||
/* E bit clear : watchpoint disabled */
|
||||
return;
|
||||
}
|
||||
|
||||
bt = extract64(bcr, 20, 4);
|
||||
|
||||
switch (bt) {
|
||||
case 4: /* unlinked address mismatch (reserved if AArch64) */
|
||||
case 5: /* linked address mismatch (reserved if AArch64) */
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"arm: address mismatch breakpoint types not implemented\n");
|
||||
return;
|
||||
case 0: /* unlinked address match */
|
||||
case 1: /* linked address match */
|
||||
{
|
||||
/*
|
||||
* Bits [1:0] are RES0.
|
||||
*
|
||||
* It is IMPLEMENTATION DEFINED whether bits [63:49]
|
||||
* ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
|
||||
* of the VA field ([48] or [52] for FEAT_LVA), or whether the
|
||||
* value is read as written. It is CONSTRAINED UNPREDICTABLE
|
||||
* whether the RESS bits are ignored when comparing an address.
|
||||
* Therefore we are allowed to compare the entire register, which
|
||||
* lets us avoid considering whether FEAT_LVA is actually enabled.
|
||||
*
|
||||
* The BAS field is used to allow setting breakpoints on 16-bit
|
||||
* wide instructions; it is CONSTRAINED UNPREDICTABLE whether
|
||||
* a bp will fire if the addresses covered by the bp and the addresses
|
||||
* covered by the insn overlap but the insn doesn't start at the
|
||||
* start of the bp address range. We choose to require the insn and
|
||||
* the bp to have the same address. The constraints on writing to
|
||||
* BAS enforced in dbgbcr_write mean we have only four cases:
|
||||
* 0b0000 => no breakpoint
|
||||
* 0b0011 => breakpoint on addr
|
||||
* 0b1100 => breakpoint on addr + 2
|
||||
* 0b1111 => breakpoint on addr
|
||||
* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
|
||||
*/
|
||||
int bas = extract64(bcr, 5, 4);
|
||||
addr = bvr & ~3ULL;
|
||||
if (bas == 0) {
|
||||
return;
|
||||
}
|
||||
if (bas == 0xc) {
|
||||
addr += 2;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 2: /* unlinked context ID match */
|
||||
case 8: /* unlinked VMID match (reserved if no EL2) */
|
||||
case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"arm: unlinked context breakpoint types not implemented\n");
|
||||
return;
|
||||
case 9: /* linked VMID match (reserved if no EL2) */
|
||||
case 11: /* linked context ID and VMID match (reserved if no EL2) */
|
||||
case 3: /* linked context ID match */
|
||||
default:
|
||||
/*
|
||||
* We must generate no events for Linked context matches (unless
|
||||
* they are linked to by some other bp/wp, which is handled in
|
||||
* updates for the linking bp/wp). We choose to also generate no events
|
||||
* for reserved values.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
|
||||
}
|
||||
|
||||
void hw_breakpoint_update_all(ARMCPU *cpu)
|
||||
{
|
||||
int i;
|
||||
CPUARMState *env = &cpu->env;
|
||||
|
||||
/*
|
||||
* Completely clear out existing QEMU breakpoints and our array, to
|
||||
* avoid possible stale entries following migration load.
|
||||
*/
|
||||
cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
|
||||
memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
|
||||
hw_breakpoint_update(cpu, i);
|
||||
}
|
||||
}
|
||||
|
||||
static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
ARMCPU *cpu = env_archcpu(env);
|
||||
int i = ri->crm;
|
||||
|
||||
raw_write(env, ri, value);
|
||||
hw_breakpoint_update(cpu, i);
|
||||
}
|
||||
|
||||
static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
ARMCPU *cpu = env_archcpu(env);
|
||||
int i = ri->crm;
|
||||
|
||||
/*
|
||||
* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
|
||||
* copy of BAS[0].
|
||||
*/
|
||||
value = deposit64(value, 6, 1, extract64(value, 5, 1));
|
||||
value = deposit64(value, 8, 1, extract64(value, 7, 1));
|
||||
|
||||
raw_write(env, ri, value);
|
||||
hw_breakpoint_update(cpu, i);
|
||||
}
|
||||
|
||||
static void define_debug_regs(ARMCPU *cpu)
|
||||
{
|
||||
/*
|
||||
* Define v7 and v8 architectural debug registers.
|
||||
* These are just dummy implementations for now.
|
||||
*/
|
||||
int i;
|
||||
int wrps, brps, ctx_cmps;
|
||||
|
||||
/*
|
||||
* The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
|
||||
* use AArch32. Given that bit 15 is RES1, if the value is 0 then
|
||||
* the register must not exist for this cpu.
|
||||
*/
|
||||
if (cpu->isar.dbgdidr != 0) {
|
||||
ARMCPRegInfo dbgdidr = {
|
||||
.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
|
||||
.opc1 = 0, .opc2 = 0,
|
||||
.access = PL0_R, .accessfn = access_tda,
|
||||
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
|
||||
};
|
||||
define_one_arm_cp_reg(cpu, &dbgdidr);
|
||||
}
|
||||
|
||||
brps = arm_num_brps(cpu);
|
||||
wrps = arm_num_wrps(cpu);
|
||||
ctx_cmps = arm_num_ctx_cmps(cpu);
|
||||
|
||||
assert(ctx_cmps <= brps);
|
||||
|
||||
define_arm_cp_regs(cpu, debug_cp_reginfo);
|
||||
|
||||
if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
|
||||
define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
|
||||
}
|
||||
|
||||
for (i = 0; i < brps; i++) {
|
||||
char *dbgbvr_el1_name = g_strdup_printf("DBGBVR%d_EL1", i);
|
||||
char *dbgbcr_el1_name = g_strdup_printf("DBGBCR%d_EL1", i);
|
||||
ARMCPRegInfo dbgregs[] = {
|
||||
{ .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
|
||||
.writefn = dbgbvr_write, .raw_writefn = raw_write
|
||||
},
|
||||
{ .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
|
||||
.writefn = dbgbcr_write, .raw_writefn = raw_write
|
||||
},
|
||||
};
|
||||
define_arm_cp_regs(cpu, dbgregs);
|
||||
g_free(dbgbvr_el1_name);
|
||||
g_free(dbgbcr_el1_name);
|
||||
}
|
||||
|
||||
for (i = 0; i < wrps; i++) {
|
||||
char *dbgwvr_el1_name = g_strdup_printf("DBGWVR%d_EL1", i);
|
||||
char *dbgwcr_el1_name = g_strdup_printf("DBGWCR%d_EL1", i);
|
||||
ARMCPRegInfo dbgregs[] = {
|
||||
{ .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
|
||||
.writefn = dbgwvr_write, .raw_writefn = raw_write
|
||||
},
|
||||
{ .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
|
||||
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
|
||||
.access = PL1_RW, .accessfn = access_tda,
|
||||
.fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
|
||||
.writefn = dbgwcr_write, .raw_writefn = raw_write
|
||||
},
|
||||
};
|
||||
define_arm_cp_regs(cpu, dbgregs);
|
||||
g_free(dbgwvr_el1_name);
|
||||
g_free(dbgwcr_el1_name);
|
||||
}
|
||||
}
|
||||
|
||||
static void define_pmu_regs(ARMCPU *cpu)
|
||||
{
|
||||
/*
|
||||
|
|
|
@ -1307,6 +1307,15 @@ int exception_target_el(CPUARMState *env);
|
|||
bool arm_singlestep_active(CPUARMState *env);
|
||||
bool arm_generate_debug_exceptions(CPUARMState *env);
|
||||
|
||||
/* Add the cpreg definitions for debug related system registers */
|
||||
void define_debug_regs(ARMCPU *cpu);
|
||||
|
||||
/* Effective value of MDCR_EL2 */
|
||||
static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
|
||||
{
|
||||
return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0;
|
||||
}
|
||||
|
||||
/* Powers of 2 for sve_vq_map et al. */
|
||||
#define SVE_VQ_POW2_MAP \
|
||||
((1 << (1 - 1)) | (1 << (2 - 1)) | \
|
||||
|
|
Loading…
Reference in New Issue