Pull request m68k-20210212
Move bootinfo headers to include/standard-headers/asm-m68k Add M68K_FEATURE_MSP, M68K_FEATURE_MOVEC, M68K_FEATURE_M68010 Add 68060 CR BUSCR and PCR (unimplemented) CPU types and features cleanup -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmAm77QSHGxhdXJlbnRA dml2aWVyLmV1AAoJEPMMOL0/L748RCUP/2OzWc0B+q7p8JClOhzFALhz0GgiH0z9 r+OWTsyFJRK17zmqeL88w6RdLPaU0VJOoOu/tgBFLy0UtQfLaxuetbM1KCsMQyiM hq5ZG5Syi+Vb4bFfwk3b6skibEkdhwcRPXSNRtCdkSbqqvwLAJYHqjtwwEmBZDhe 9ZsjE+VMAbBRSMJfj4K9Vyter9iBxiZnJB71sJsEKy2WRKJjMSvQaLTBV1ocTL+p UNROsUNK0O4G/0hOLxgAy5Azb6z+A9ln67RsaseCWgRkMERf7DZb2XpDOrKB1gau g6KFweInDw2s4kabg+30Oyh8yQVw7o89Atg8d57Kgub7GDJTReUtJVtc+X3CXdIv 630k1kDsx7h5prZJ8aTPZQXkjfOcJiritzb+Ivb0DtDz/hM6QDKtgZ8OHWJ7/ZTp x8RGIZzFaHmV+6nMTRQlUmZyjfmyPEpGpIRiY+IHyogZ7b1MOInIKboC4Ewq4KgS SdscFT8uiT8F3EdfFvIkBYbV04JNL/JILgEv9fmLsdvBDSXY5DF1Tv6qiG2yJkH3 d4w9FaFtZpQdFiU95TBJ048imjda6JlxCdAOA3wCT5GrVNd3yEZMbR7ATS8dcxw5 cPRTidnKSC9ScUzyRlyPg00/u0hAwrcL20cCt7HYN3duNk1CZCdtbdTS8urIkKy6 SqoBn0pUdtsU =RnpD -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' into staging Pull request m68k-20210212 Move bootinfo headers to include/standard-headers/asm-m68k Add M68K_FEATURE_MSP, M68K_FEATURE_MOVEC, M68K_FEATURE_M68010 Add 68060 CR BUSCR and PCR (unimplemented) CPU types and features cleanup # gpg: Signature made Fri 12 Feb 2021 21:14:28 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-6.0-pull-request: m68k: import bootinfo headers from linux m68k: add MSP detection support for stack pointer swap helpers m68k: MOVEC insn. should generate exception if wrong CR is accessed m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to m68k_move_to/from m68k: improve comments on m68k_move_to/from helpers m68k: cascade m68k_features by m680xx_cpu_initfn() to improve readability m68k: improve cpu instantiation comments Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
f4ceebdec5
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@ -1107,6 +1107,8 @@ F: hw/nubus/*
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F: hw/display/macfb.c
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F: hw/block/swim.c
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F: hw/m68k/bootinfo.h
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F: include/standard-headers/asm-m68k/bootinfo.h
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F: include/standard-headers/asm-m68k/bootinfo-mac.h
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F: include/hw/misc/mac_via.h
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F: include/hw/nubus/*
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F: include/hw/display/macfb.h
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@ -11,61 +11,6 @@
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#ifndef HW_M68K_BOOTINFO_H
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#define HW_M68K_BOOTINFO_H
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struct bi_record {
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uint16_t tag; /* tag ID */
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uint16_t size; /* size of record */
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uint32_t data[]; /* data */
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};
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/* machine independent tags */
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#define BI_LAST 0x0000 /* last record */
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#define BI_MACHTYPE 0x0001 /* machine type (u_long) */
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#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */
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#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */
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#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */
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#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */
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/* (struct mem_info) */
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#define BI_RAMDISK 0x0006 /* ramdisk address and size */
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/* (struct mem_info) */
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#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */
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/* (string) */
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/* Macintosh-specific tags (all u_long) */
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#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
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#define BI_MAC_VADDR 0x8001 /* Mac video base address */
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#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
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#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
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#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
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#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
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#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
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#define BI_MAC_BTIME 0x8007 /* Mac boot time */
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#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */
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#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */
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#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */
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#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */
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/* Macintosh hardware profile data */
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#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */
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#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */
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#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */
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#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */
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#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */
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#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */
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#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */
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#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */
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#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */
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#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */
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#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */
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#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */
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#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */
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#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */
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#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */
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#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */
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#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */
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#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */
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#define BOOTINFO0(as, base, id) \
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do { \
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@ -37,6 +37,8 @@
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#include "hw/char/escc.h"
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#include "hw/sysbus.h"
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#include "hw/scsi/esp.h"
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#include "standard-headers/asm-m68k/bootinfo.h"
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#include "standard-headers/asm-m68k/bootinfo-mac.h"
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#include "bootinfo.h"
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#include "hw/misc/mac_via.h"
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#include "hw/input/adb.h"
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@ -55,14 +57,6 @@
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#define MACROM_FILENAME "MacROM.bin"
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#define Q800_MACHINE_ID 35
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#define Q800_CPU_ID (1 << 2)
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#define Q800_FPU_ID (1 << 2)
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#define Q800_MMU_ID (1 << 2)
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#define MACH_MAC 3
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#define Q800_MAC_CPU_ID 2
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#define IO_BASE 0x50000000
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#define IO_SLICE 0x00040000
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#define IO_SIZE 0x04000000
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@ -415,11 +409,11 @@ static void q800_init(MachineState *machine)
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parameters_base = (high + 1) & ~1;
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BOOTINFO1(cs->as, parameters_base, BI_MACHTYPE, MACH_MAC);
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BOOTINFO1(cs->as, parameters_base, BI_FPUTYPE, Q800_FPU_ID);
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BOOTINFO1(cs->as, parameters_base, BI_MMUTYPE, Q800_MMU_ID);
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BOOTINFO1(cs->as, parameters_base, BI_CPUTYPE, Q800_CPU_ID);
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BOOTINFO1(cs->as, parameters_base, BI_MAC_CPUID, Q800_MAC_CPU_ID);
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BOOTINFO1(cs->as, parameters_base, BI_MAC_MODEL, Q800_MACHINE_ID);
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BOOTINFO1(cs->as, parameters_base, BI_FPUTYPE, FPU_68040);
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BOOTINFO1(cs->as, parameters_base, BI_MMUTYPE, MMU_68040);
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BOOTINFO1(cs->as, parameters_base, BI_CPUTYPE, CPU_68040);
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BOOTINFO1(cs->as, parameters_base, BI_MAC_CPUID, CPUB_68040);
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BOOTINFO1(cs->as, parameters_base, BI_MAC_MODEL, MAC_MODEL_Q800);
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BOOTINFO1(cs->as, parameters_base,
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BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */
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BOOTINFO2(cs->as, parameters_base, BI_MEMCHUNK, 0, ram_size);
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@ -0,0 +1,120 @@
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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** asm/bootinfo-mac.h -- Macintosh-specific boot information definitions
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*/
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#ifndef _UAPI_ASM_M68K_BOOTINFO_MAC_H
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#define _UAPI_ASM_M68K_BOOTINFO_MAC_H
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/*
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* Macintosh-specific tags (all __be32)
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*/
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#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
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#define BI_MAC_VADDR 0x8001 /* Mac video base address */
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#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
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#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
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#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
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#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
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#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
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#define BI_MAC_BTIME 0x8007 /* Mac boot time */
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#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */
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#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */
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#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */
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#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */
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/*
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* Macintosh hardware profile data - unused, see macintosh.h for
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* reasonable type values
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*/
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#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */
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#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */
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#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */
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#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */
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#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */
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#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */
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#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */
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#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */
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#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */
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#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */
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#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */
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#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */
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#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */
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#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */
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#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */
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#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */
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#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */
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#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */
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/*
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* Macintosh Gestalt numbers (BI_MAC_MODEL)
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*/
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#define MAC_MODEL_II 6
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#define MAC_MODEL_IIX 7
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#define MAC_MODEL_IICX 8
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#define MAC_MODEL_SE30 9
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#define MAC_MODEL_IICI 11
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#define MAC_MODEL_IIFX 13 /* And well numbered it is too */
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#define MAC_MODEL_IISI 18
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#define MAC_MODEL_LC 19
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#define MAC_MODEL_Q900 20
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#define MAC_MODEL_PB170 21
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#define MAC_MODEL_Q700 22
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#define MAC_MODEL_CLII 23 /* aka: P200 */
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#define MAC_MODEL_PB140 25
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#define MAC_MODEL_Q950 26 /* aka: WGS95 */
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#define MAC_MODEL_LCIII 27 /* aka: P450 */
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#define MAC_MODEL_PB210 29
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#define MAC_MODEL_C650 30
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#define MAC_MODEL_PB230 32
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#define MAC_MODEL_PB180 33
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#define MAC_MODEL_PB160 34
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#define MAC_MODEL_Q800 35 /* aka: WGS80 */
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#define MAC_MODEL_Q650 36
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#define MAC_MODEL_LCII 37 /* aka: P400/405/410/430 */
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#define MAC_MODEL_PB250 38
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#define MAC_MODEL_IIVI 44
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#define MAC_MODEL_P600 45 /* aka: P600CD */
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#define MAC_MODEL_IIVX 48
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#define MAC_MODEL_CCL 49 /* aka: P250 */
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#define MAC_MODEL_PB165C 50
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#define MAC_MODEL_C610 52 /* aka: WGS60 */
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#define MAC_MODEL_Q610 53
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#define MAC_MODEL_PB145 54 /* aka: PB145B */
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#define MAC_MODEL_P520 56 /* aka: LC520 */
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#define MAC_MODEL_C660 60
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#define MAC_MODEL_P460 62 /* aka: LCIII+, P466/P467 */
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#define MAC_MODEL_PB180C 71
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#define MAC_MODEL_PB520 72 /* aka: PB520C, PB540, PB540C, PB550C */
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#define MAC_MODEL_PB270C 77
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#define MAC_MODEL_Q840 78
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#define MAC_MODEL_P550 80 /* aka: LC550, P560 */
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#define MAC_MODEL_CCLII 83 /* aka: P275 */
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#define MAC_MODEL_PB165 84
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#define MAC_MODEL_PB190 85 /* aka: PB190CS */
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#define MAC_MODEL_TV 88
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#define MAC_MODEL_P475 89 /* aka: LC475, P476 */
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#define MAC_MODEL_P475F 90 /* aka: P475 w/ FPU (no LC040) */
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#define MAC_MODEL_P575 92 /* aka: LC575, P577/P578 */
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#define MAC_MODEL_Q605 94
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#define MAC_MODEL_Q605_ACC 95 /* Q605 accelerated to 33 MHz */
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#define MAC_MODEL_Q630 98 /* aka: LC630, P630/631/635/636/637/638/640 */
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#define MAC_MODEL_P588 99 /* aka: LC580, P580 */
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#define MAC_MODEL_PB280 102
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#define MAC_MODEL_PB280C 103
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#define MAC_MODEL_PB150 115
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/*
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* Latest Macintosh bootinfo version
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*/
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#define MAC_BOOTI_VERSION MK_BI_VERSION(2, 0)
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#endif /* _UAPI_ASM_M68K_BOOTINFO_MAC_H */
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@ -0,0 +1,166 @@
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* asm/bootinfo.h -- Definition of the Linux/m68k boot information structure
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*
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* Copyright 1992 by Greg Harp
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#ifndef _UAPI_ASM_M68K_BOOTINFO_H
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#define _UAPI_ASM_M68K_BOOTINFO_H
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/*
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* Bootinfo definitions
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*
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* This is an easily parsable and extendable structure containing all
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* information to be passed from the bootstrap to the kernel.
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*
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* This way I hope to keep all future changes back/forewards compatible.
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* Thus, keep your fingers crossed...
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*
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* This structure is copied right after the kernel by the bootstrap
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* routine.
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*/
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struct bi_record {
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uint16_t tag; /* tag ID */
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uint16_t size; /* size of record (in bytes) */
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uint32_t data[0]; /* data */
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};
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struct mem_info {
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uint32_t addr; /* physical address of memory chunk */
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uint32_t size; /* length of memory chunk (in bytes) */
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};
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/*
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* Tag Definitions
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*
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* Machine independent tags start counting from 0x0000
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* Machine dependent tags start counting from 0x8000
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*/
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#define BI_LAST 0x0000 /* last record (sentinel) */
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#define BI_MACHTYPE 0x0001 /* machine type (uint32_t) */
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#define BI_CPUTYPE 0x0002 /* cpu type (uint32_t) */
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#define BI_FPUTYPE 0x0003 /* fpu type (uint32_t) */
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#define BI_MMUTYPE 0x0004 /* mmu type (uint32_t) */
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#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */
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/* (struct mem_info) */
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#define BI_RAMDISK 0x0006 /* ramdisk address and size */
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/* (struct mem_info) */
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#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */
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/* (string) */
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/*
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* Linux/m68k Architectures (BI_MACHTYPE)
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*/
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#define MACH_AMIGA 1
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#define MACH_ATARI 2
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#define MACH_MAC 3
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#define MACH_APOLLO 4
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#define MACH_SUN3 5
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#define MACH_MVME147 6
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#define MACH_MVME16x 7
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#define MACH_BVME6000 8
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#define MACH_HP300 9
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#define MACH_Q40 10
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#define MACH_SUN3X 11
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#define MACH_M54XX 12
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#define MACH_M5441X 13
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#define MACH_VIRT 14
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/*
|
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* CPU, FPU and MMU types (BI_CPUTYPE, BI_FPUTYPE, BI_MMUTYPE)
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*
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* Note: we may rely on the following equalities:
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*
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* CPU_68020 == MMU_68851
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* CPU_68030 == MMU_68030
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* CPU_68040 == FPU_68040 == MMU_68040
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* CPU_68060 == FPU_68060 == MMU_68060
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*/
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#define CPUB_68020 0
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#define CPUB_68030 1
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#define CPUB_68040 2
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#define CPUB_68060 3
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#define CPUB_COLDFIRE 4
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||||
|
||||
#define CPU_68020 (1 << CPUB_68020)
|
||||
#define CPU_68030 (1 << CPUB_68030)
|
||||
#define CPU_68040 (1 << CPUB_68040)
|
||||
#define CPU_68060 (1 << CPUB_68060)
|
||||
#define CPU_COLDFIRE (1 << CPUB_COLDFIRE)
|
||||
|
||||
#define FPUB_68881 0
|
||||
#define FPUB_68882 1
|
||||
#define FPUB_68040 2 /* Internal FPU */
|
||||
#define FPUB_68060 3 /* Internal FPU */
|
||||
#define FPUB_SUNFPA 4 /* Sun-3 FPA */
|
||||
#define FPUB_COLDFIRE 5 /* ColdFire FPU */
|
||||
|
||||
#define FPU_68881 (1 << FPUB_68881)
|
||||
#define FPU_68882 (1 << FPUB_68882)
|
||||
#define FPU_68040 (1 << FPUB_68040)
|
||||
#define FPU_68060 (1 << FPUB_68060)
|
||||
#define FPU_SUNFPA (1 << FPUB_SUNFPA)
|
||||
#define FPU_COLDFIRE (1 << FPUB_COLDFIRE)
|
||||
|
||||
#define MMUB_68851 0
|
||||
#define MMUB_68030 1 /* Internal MMU */
|
||||
#define MMUB_68040 2 /* Internal MMU */
|
||||
#define MMUB_68060 3 /* Internal MMU */
|
||||
#define MMUB_APOLLO 4 /* Custom Apollo */
|
||||
#define MMUB_SUN3 5 /* Custom Sun-3 */
|
||||
#define MMUB_COLDFIRE 6 /* Internal MMU */
|
||||
|
||||
#define MMU_68851 (1 << MMUB_68851)
|
||||
#define MMU_68030 (1 << MMUB_68030)
|
||||
#define MMU_68040 (1 << MMUB_68040)
|
||||
#define MMU_68060 (1 << MMUB_68060)
|
||||
#define MMU_SUN3 (1 << MMUB_SUN3)
|
||||
#define MMU_APOLLO (1 << MMUB_APOLLO)
|
||||
#define MMU_COLDFIRE (1 << MMUB_COLDFIRE)
|
||||
|
||||
|
||||
/*
|
||||
* Stuff for bootinfo interface versioning
|
||||
*
|
||||
* At the start of kernel code, a 'struct bootversion' is located.
|
||||
* bootstrap checks for a matching version of the interface before booting
|
||||
* a kernel, to avoid user confusion if kernel and bootstrap don't work
|
||||
* together :-)
|
||||
*
|
||||
* If incompatible changes are made to the bootinfo interface, the major
|
||||
* number below should be stepped (and the minor reset to 0) for the
|
||||
* appropriate machine. If a change is backward-compatible, the minor
|
||||
* should be stepped. "Backwards-compatible" means that booting will work,
|
||||
* but certain features may not.
|
||||
*/
|
||||
|
||||
#define BOOTINFOV_MAGIC 0x4249561A /* 'BIV^Z' */
|
||||
#define MK_BI_VERSION(major, minor) (((major) << 16) + (minor))
|
||||
#define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff)
|
||||
#define BI_VERSION_MINOR(v) ((v) & 0xffff)
|
||||
|
||||
struct bootversion {
|
||||
uint16_t branch;
|
||||
uint32_t magic;
|
||||
struct {
|
||||
uint32_t machtype;
|
||||
uint32_t version;
|
||||
} machversions[0];
|
||||
} QEMU_PACKED;
|
||||
|
||||
|
||||
#endif /* _UAPI_ASM_M68K_BOOTINFO_H */
|
||||
|
|
@ -41,6 +41,11 @@ static void m68k_set_feature(CPUM68KState *env, int feature)
|
|||
env->features |= (1u << feature);
|
||||
}
|
||||
|
||||
static void m68k_unset_feature(CPUM68KState *env, int feature)
|
||||
{
|
||||
env->features &= (-1u - (1u << feature));
|
||||
}
|
||||
|
||||
static void m68k_cpu_reset(DeviceState *dev)
|
||||
{
|
||||
CPUState *s = CPU(dev);
|
||||
|
|
@ -103,6 +108,7 @@ static void m5206_cpu_initfn(Object *obj)
|
|||
m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
|
||||
}
|
||||
|
||||
/* Base feature set, including isns. for m68k family */
|
||||
static void m68000_cpu_initfn(Object *obj)
|
||||
{
|
||||
M68kCPU *cpu = M68K_CPU(obj);
|
||||
|
|
@ -114,12 +120,36 @@ static void m68000_cpu_initfn(Object *obj)
|
|||
m68k_set_feature(env, M68K_FEATURE_MOVEP);
|
||||
}
|
||||
|
||||
/* common features for 68020, 68030 and 68040 */
|
||||
static void m680x0_cpu_common(CPUM68KState *env)
|
||||
/*
|
||||
* Adds BKPT, MOVE-from-SR *now priv instr, and MOVEC, MOVES, RTD
|
||||
*/
|
||||
static void m68010_cpu_initfn(Object *obj)
|
||||
{
|
||||
m68k_set_feature(env, M68K_FEATURE_M68000);
|
||||
m68k_set_feature(env, M68K_FEATURE_USP);
|
||||
m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);
|
||||
M68kCPU *cpu = M68K_CPU(obj);
|
||||
CPUM68KState *env = &cpu->env;
|
||||
|
||||
m68000_cpu_initfn(obj);
|
||||
m68k_set_feature(env, M68K_FEATURE_M68010);
|
||||
m68k_set_feature(env, M68K_FEATURE_RTD);
|
||||
m68k_set_feature(env, M68K_FEATURE_BKPT);
|
||||
m68k_set_feature(env, M68K_FEATURE_MOVEC);
|
||||
}
|
||||
|
||||
/*
|
||||
* Adds BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST, CAS, CAS2,
|
||||
* CHK2, CMP2, DIVSL, DIVUL, EXTB, PACK, TRAPcc, UNPK.
|
||||
*
|
||||
* 68020/30 only:
|
||||
* CALLM, cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc
|
||||
*/
|
||||
static void m68020_cpu_initfn(Object *obj)
|
||||
{
|
||||
M68kCPU *cpu = M68K_CPU(obj);
|
||||
CPUM68KState *env = &cpu->env;
|
||||
|
||||
m68010_cpu_initfn(obj);
|
||||
m68k_unset_feature(env, M68K_FEATURE_M68010);
|
||||
m68k_set_feature(env, M68K_FEATURE_M68020);
|
||||
m68k_set_feature(env, M68K_FEATURE_QUAD_MULDIV);
|
||||
m68k_set_feature(env, M68K_FEATURE_BRAL);
|
||||
m68k_set_feature(env, M68K_FEATURE_BCCL);
|
||||
|
|
@ -129,59 +159,78 @@ static void m680x0_cpu_common(CPUM68KState *env)
|
|||
m68k_set_feature(env, M68K_FEATURE_LONG_MULDIV);
|
||||
m68k_set_feature(env, M68K_FEATURE_FPU);
|
||||
m68k_set_feature(env, M68K_FEATURE_CAS);
|
||||
m68k_set_feature(env, M68K_FEATURE_BKPT);
|
||||
m68k_set_feature(env, M68K_FEATURE_RTD);
|
||||
m68k_set_feature(env, M68K_FEATURE_CHK2);
|
||||
m68k_set_feature(env, M68K_FEATURE_MOVEP);
|
||||
}
|
||||
|
||||
static void m68020_cpu_initfn(Object *obj)
|
||||
{
|
||||
M68kCPU *cpu = M68K_CPU(obj);
|
||||
CPUM68KState *env = &cpu->env;
|
||||
|
||||
m680x0_cpu_common(env);
|
||||
m68k_set_feature(env, M68K_FEATURE_M68020);
|
||||
m68k_set_feature(env, M68K_FEATURE_MSP);
|
||||
}
|
||||
|
||||
/*
|
||||
* Adds: PFLUSH (*5)
|
||||
* 68030 Only: PFLUSHA (*5), PLOAD (*5), PMOVE
|
||||
* 68030/40 Only: PTEST
|
||||
*
|
||||
* NOTES:
|
||||
* 5. Not valid on MC68EC030
|
||||
*/
|
||||
static void m68030_cpu_initfn(Object *obj)
|
||||
{
|
||||
M68kCPU *cpu = M68K_CPU(obj);
|
||||
CPUM68KState *env = &cpu->env;
|
||||
|
||||
m680x0_cpu_common(env);
|
||||
m68020_cpu_initfn(obj);
|
||||
m68k_unset_feature(env, M68K_FEATURE_M68020);
|
||||
m68k_set_feature(env, M68K_FEATURE_M68030);
|
||||
}
|
||||
|
||||
/*
|
||||
* Adds: CINV, CPUSH
|
||||
* Adds all with Note *2: FABS, FSABS, FDABS, FADD, FSADD, FDADD, FBcc, FCMP,
|
||||
* FDBcc, FDIV, FSDIV, FDDIV, FMOVE, FSMOVE, FDMOVE,
|
||||
* FMOVEM, FMUL, FSMUL, FDMUL, FNEG, FSNEG, FDNEG, FNOP,
|
||||
* FRESTORE, FSAVE, FScc, FSQRT, FSSQRT, FDSQRT, FSUB,
|
||||
* FSSUB, FDSUB, FTRAPcc, FTST
|
||||
*
|
||||
* Adds with Notes *2, and *3: FACOS, FASIN, FATAN, FATANH, FCOS, FCOSH, FETOX,
|
||||
* FETOXM, FGETEXP, FGETMAN, FINT, FINTRZ, FLOG10,
|
||||
* FLOG2, FLOGN, FLOGNP1, FMOD, FMOVECR, FREM,
|
||||
* FSCALE, FSGLDIV, FSGLMUL, FSIN, FSINCOS, FSINH,
|
||||
* FTAN, FTANH, FTENTOX, FTWOTOX
|
||||
* NOTES:
|
||||
* 2. Not applicable to the MC68EC040, MC68LC040, MC68EC060, and MC68LC060.
|
||||
* 3. These are software-supported instructions on the MC68040 and MC68060.
|
||||
*/
|
||||
static void m68040_cpu_initfn(Object *obj)
|
||||
{
|
||||
M68kCPU *cpu = M68K_CPU(obj);
|
||||
CPUM68KState *env = &cpu->env;
|
||||
|
||||
m680x0_cpu_common(env);
|
||||
m68030_cpu_initfn(obj);
|
||||
m68k_unset_feature(env, M68K_FEATURE_M68030);
|
||||
m68k_set_feature(env, M68K_FEATURE_M68040);
|
||||
}
|
||||
|
||||
/*
|
||||
* Adds: PLPA
|
||||
* Adds all with Note *2: CAS, CAS2, MULS, MULU, CHK2, CMP2, DIVS, DIVU
|
||||
* All Fxxxx instructions are as per m68040 with exception to; FMOVEM NOTE3
|
||||
*
|
||||
* Does NOT implement MOVEP
|
||||
*
|
||||
* NOTES:
|
||||
* 2. Not applicable to the MC68EC040, MC68LC040, MC68EC060, and MC68LC060.
|
||||
* 3. These are software-supported instructions on the MC68040 and MC68060.
|
||||
*/
|
||||
static void m68060_cpu_initfn(Object *obj)
|
||||
{
|
||||
M68kCPU *cpu = M68K_CPU(obj);
|
||||
CPUM68KState *env = &cpu->env;
|
||||
|
||||
m68k_set_feature(env, M68K_FEATURE_M68000);
|
||||
m68k_set_feature(env, M68K_FEATURE_USP);
|
||||
m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);
|
||||
m68k_set_feature(env, M68K_FEATURE_BRAL);
|
||||
m68k_set_feature(env, M68K_FEATURE_BCCL);
|
||||
m68k_set_feature(env, M68K_FEATURE_BITFIELD);
|
||||
m68k_set_feature(env, M68K_FEATURE_EXT_FULL);
|
||||
m68k_set_feature(env, M68K_FEATURE_SCALED_INDEX);
|
||||
m68k_set_feature(env, M68K_FEATURE_LONG_MULDIV);
|
||||
m68k_set_feature(env, M68K_FEATURE_FPU);
|
||||
m68k_set_feature(env, M68K_FEATURE_CAS);
|
||||
m68k_set_feature(env, M68K_FEATURE_BKPT);
|
||||
m68k_set_feature(env, M68K_FEATURE_RTD);
|
||||
m68k_set_feature(env, M68K_FEATURE_CHK2);
|
||||
m68040_cpu_initfn(obj);
|
||||
m68k_unset_feature(env, M68K_FEATURE_M68040);
|
||||
m68k_set_feature(env, M68K_FEATURE_M68060);
|
||||
m68k_unset_feature(env, M68K_FEATURE_MOVEP);
|
||||
|
||||
/* Implemented as a software feature */
|
||||
m68k_unset_feature(env, M68K_FEATURE_QUAD_MULDIV);
|
||||
}
|
||||
|
||||
static void m5208_cpu_initfn(Object *obj)
|
||||
|
|
@ -533,6 +582,7 @@ static const TypeInfo m68k_cpus_type_infos[] = {
|
|||
.class_init = m68k_cpu_class_init,
|
||||
},
|
||||
DEFINE_M68K_CPU_TYPE_M68K(m68000),
|
||||
DEFINE_M68K_CPU_TYPE_M68K(m68010),
|
||||
DEFINE_M68K_CPU_TYPE_M68K(m68020),
|
||||
DEFINE_M68K_CPU_TYPE_M68K(m68030),
|
||||
DEFINE_M68K_CPU_TYPE_M68K(m68040),
|
||||
|
|
|
|||
|
|
@ -85,7 +85,13 @@ typedef struct CPUM68KState {
|
|||
uint32_t pc;
|
||||
uint32_t sr;
|
||||
|
||||
/* SSP and USP. The current_sp is stored in aregs[7], the other here. */
|
||||
/*
|
||||
* The 68020/30/40 support two supervisor stacks, ISP and MSP.
|
||||
* The 68000/10, Coldfire, and CPU32 only have USP/SSP.
|
||||
*
|
||||
* The current_sp is stored in aregs[7], the other here.
|
||||
* The USP, SSP, and if used the additional ISP for 68020/30/40.
|
||||
*/
|
||||
int current_sp;
|
||||
uint32_t sp[3];
|
||||
|
||||
|
|
@ -393,6 +399,10 @@ typedef enum {
|
|||
#define M68K_CR_DACR0 0x006
|
||||
#define M68K_CR_DACR1 0x007
|
||||
|
||||
/* MC68060 */
|
||||
#define M68K_CR_BUSCR 0x008
|
||||
#define M68K_CR_PCR 0x808
|
||||
|
||||
#define M68K_FPIAR_SHIFT 0
|
||||
#define M68K_FPIAR (1 << M68K_FPIAR_SHIFT)
|
||||
#define M68K_FPSR_SHIFT 1
|
||||
|
|
@ -450,39 +460,51 @@ void m68k_switch_sp(CPUM68KState *env);
|
|||
void do_m68k_semihosting(CPUM68KState *env, int nr);
|
||||
|
||||
/*
|
||||
* The 68000 family is defined in six main CPU classes, the 680[012346]0.
|
||||
* Generally each successive CPU adds enhanced data/stack/instructions.
|
||||
* However, some features are only common to one, or a few classes.
|
||||
* The features covers those subsets of instructons.
|
||||
*
|
||||
* CPU32/32+ are basically 680010 compatible with some 68020 class instructons,
|
||||
* and some additional CPU32 instructions. Mostly Supervisor state differences.
|
||||
*
|
||||
* The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu.
|
||||
* There are 4 ColdFire core ISA revisions: A, A+, B and C.
|
||||
* Each feature covers the subset of instructions common to the
|
||||
* ISA revisions mentioned.
|
||||
*/
|
||||
|
||||
enum m68k_features {
|
||||
M68K_FEATURE_M68000,
|
||||
M68K_FEATURE_M68000, /* Base m68k instruction set */
|
||||
M68K_FEATURE_M68010,
|
||||
M68K_FEATURE_M68020,
|
||||
M68K_FEATURE_M68030,
|
||||
M68K_FEATURE_M68040,
|
||||
M68K_FEATURE_M68060,
|
||||
M68K_FEATURE_CF_ISA_A,
|
||||
M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
|
||||
M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
|
||||
M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
|
||||
M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */
|
||||
M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
|
||||
M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
|
||||
M68K_FEATURE_BRAL, /* BRA with Long branch. (680[2346]0, ISA A+ or B). */
|
||||
M68K_FEATURE_CF_FPU,
|
||||
M68K_FEATURE_CF_MAC,
|
||||
M68K_FEATURE_CF_EMAC,
|
||||
M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
|
||||
M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
|
||||
M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
|
||||
M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
|
||||
M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
|
||||
M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
|
||||
M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
|
||||
M68K_FEATURE_BCCL, /* Long conditional branches. */
|
||||
M68K_FEATURE_BITFIELD, /* Bit field insns. */
|
||||
M68K_FEATURE_FPU,
|
||||
M68K_FEATURE_CAS,
|
||||
M68K_FEATURE_BKPT,
|
||||
M68K_FEATURE_RTD,
|
||||
M68K_FEATURE_CHK2,
|
||||
M68K_FEATURE_MOVEP,
|
||||
M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
|
||||
M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C).*/
|
||||
M68K_FEATURE_MSP, /* Master Stack Pointer. (680[234]0) */
|
||||
M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
|
||||
M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
|
||||
M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
|
||||
M68K_FEATURE_LONG_MULDIV, /* 32 bit mul/div. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_QUAD_MULDIV, /* 64 bit mul/div. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_BCCL, /* Bcc with Long branches. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_BITFIELD, /* BFxxx Bit field insns. (680[2346]0) */
|
||||
M68K_FEATURE_FPU, /* fpu insn. (680[46]0) */
|
||||
M68K_FEATURE_CAS, /* CAS/CAS2[WL] insns. (680[2346]0) */
|
||||
M68K_FEATURE_BKPT, /* BKPT insn. (680[12346]0, and CPU32) */
|
||||
M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */
|
||||
M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */
|
||||
M68K_FEATURE_MOVEC, /* MOVEC insn. (from 68010) */
|
||||
};
|
||||
|
||||
static inline int m68k_feature(CPUM68KState *env, int feature)
|
||||
|
|
|
|||
|
|
@ -184,16 +184,26 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
|
|||
}
|
||||
}
|
||||
|
||||
static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
|
||||
cs->exception_index = tt;
|
||||
cpu_loop_exit_restore(cs, raddr);
|
||||
}
|
||||
|
||||
void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
|
||||
{
|
||||
switch (reg) {
|
||||
/* MC680[1234]0 */
|
||||
/* MC680[12346]0 */
|
||||
case M68K_CR_SFC:
|
||||
env->sfc = val & 7;
|
||||
return;
|
||||
/* MC680[12346]0 */
|
||||
case M68K_CR_DFC:
|
||||
env->dfc = val & 7;
|
||||
return;
|
||||
/* MC680[12346]0 */
|
||||
case M68K_CR_VBR:
|
||||
env->vbr = val;
|
||||
return;
|
||||
|
|
@ -207,90 +217,209 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
|
|||
env->cacr = val & 0x80008000;
|
||||
} else if (m68k_feature(env, M68K_FEATURE_M68060)) {
|
||||
env->cacr = val & 0xf8e0e000;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
m68k_switch_sp(env);
|
||||
return;
|
||||
/* MC680[34]0 */
|
||||
/* MC680[46]0 */
|
||||
case M68K_CR_TC:
|
||||
env->mmu.tcr = val;
|
||||
return;
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68060)) {
|
||||
env->mmu.tcr = val;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
/* MC68040 */
|
||||
case M68K_CR_MMUSR:
|
||||
env->mmu.mmusr = val;
|
||||
return;
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
env->mmu.mmusr = val;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
/* MC680[46]0 */
|
||||
case M68K_CR_SRP:
|
||||
env->mmu.srp = val;
|
||||
return;
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68060)) {
|
||||
env->mmu.srp = val;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
/* MC680[46]0 */
|
||||
case M68K_CR_URP:
|
||||
env->mmu.urp = val;
|
||||
return;
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68060)) {
|
||||
env->mmu.urp = val;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
/* MC680[12346]0 */
|
||||
case M68K_CR_USP:
|
||||
env->sp[M68K_USP] = val;
|
||||
return;
|
||||
/* MC680[234]0 */
|
||||
case M68K_CR_MSP:
|
||||
env->sp[M68K_SSP] = val;
|
||||
return;
|
||||
if (m68k_feature(env, M68K_FEATURE_M68020)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68030)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
env->sp[M68K_SSP] = val;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
/* MC680[234]0 */
|
||||
case M68K_CR_ISP:
|
||||
env->sp[M68K_ISP] = val;
|
||||
return;
|
||||
if (m68k_feature(env, M68K_FEATURE_M68020)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68030)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
env->sp[M68K_ISP] = val;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
/* MC68040/MC68LC040 */
|
||||
case M68K_CR_ITT0:
|
||||
env->mmu.ttr[M68K_ITTR0] = val;
|
||||
return;
|
||||
case M68K_CR_ITT1:
|
||||
env->mmu.ttr[M68K_ITTR1] = val;
|
||||
return;
|
||||
case M68K_CR_DTT0:
|
||||
env->mmu.ttr[M68K_DTTR0] = val;
|
||||
return;
|
||||
case M68K_CR_DTT1:
|
||||
env->mmu.ttr[M68K_DTTR1] = val;
|
||||
return;
|
||||
case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
env->mmu.ttr[M68K_ITTR0] = val;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
/* MC68040/MC68LC040 */
|
||||
case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
env->mmu.ttr[M68K_ITTR1] = val;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
/* MC68040/MC68LC040 */
|
||||
case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
env->mmu.ttr[M68K_DTTR0] = val;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
/* MC68040/MC68LC040 */
|
||||
case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
env->mmu.ttr[M68K_DTTR1] = val;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
/* Unimplemented Registers */
|
||||
case M68K_CR_CAAR:
|
||||
case M68K_CR_PCR:
|
||||
case M68K_CR_BUSCR:
|
||||
cpu_abort(env_cpu(env),
|
||||
"Unimplemented control register write 0x%x = 0x%x\n",
|
||||
reg, val);
|
||||
}
|
||||
cpu_abort(env_cpu(env),
|
||||
"Unimplemented control register write 0x%x = 0x%x\n",
|
||||
reg, val);
|
||||
|
||||
/* Invalid control registers will generate an exception. */
|
||||
raise_exception_ra(env, EXCP_ILLEGAL, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
|
||||
{
|
||||
switch (reg) {
|
||||
/* MC680[1234]0 */
|
||||
/* MC680[12346]0 */
|
||||
case M68K_CR_SFC:
|
||||
return env->sfc;
|
||||
/* MC680[12346]0 */
|
||||
case M68K_CR_DFC:
|
||||
return env->dfc;
|
||||
/* MC680[12346]0 */
|
||||
case M68K_CR_VBR:
|
||||
return env->vbr;
|
||||
/* MC680[234]0 */
|
||||
/* MC680[2346]0 */
|
||||
case M68K_CR_CACR:
|
||||
return env->cacr;
|
||||
/* MC680[34]0 */
|
||||
if (m68k_feature(env, M68K_FEATURE_M68020)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68030)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68040)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68060)) {
|
||||
return env->cacr;
|
||||
}
|
||||
break;
|
||||
/* MC680[46]0 */
|
||||
case M68K_CR_TC:
|
||||
return env->mmu.tcr;
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68060)) {
|
||||
return env->mmu.tcr;
|
||||
}
|
||||
break;
|
||||
/* MC68040 */
|
||||
case M68K_CR_MMUSR:
|
||||
return env->mmu.mmusr;
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
return env->mmu.mmusr;
|
||||
}
|
||||
break;
|
||||
/* MC680[46]0 */
|
||||
case M68K_CR_SRP:
|
||||
return env->mmu.srp;
|
||||
case M68K_CR_USP:
|
||||
return env->sp[M68K_USP];
|
||||
case M68K_CR_MSP:
|
||||
return env->sp[M68K_SSP];
|
||||
case M68K_CR_ISP:
|
||||
return env->sp[M68K_ISP];
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68060)) {
|
||||
return env->mmu.srp;
|
||||
}
|
||||
break;
|
||||
/* MC68040/MC68LC040 */
|
||||
case M68K_CR_URP:
|
||||
return env->mmu.urp;
|
||||
case M68K_CR_ITT0:
|
||||
return env->mmu.ttr[M68K_ITTR0];
|
||||
case M68K_CR_ITT1:
|
||||
return env->mmu.ttr[M68K_ITTR1];
|
||||
case M68K_CR_DTT0:
|
||||
return env->mmu.ttr[M68K_DTTR0];
|
||||
case M68K_CR_DTT1:
|
||||
return env->mmu.ttr[M68K_DTTR1];
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68060)) {
|
||||
return env->mmu.urp;
|
||||
}
|
||||
break;
|
||||
/* MC680[46]0 */
|
||||
case M68K_CR_USP:
|
||||
return env->sp[M68K_USP];
|
||||
/* MC680[234]0 */
|
||||
case M68K_CR_MSP:
|
||||
if (m68k_feature(env, M68K_FEATURE_M68020)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68030)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
return env->sp[M68K_SSP];
|
||||
}
|
||||
break;
|
||||
/* MC680[234]0 */
|
||||
case M68K_CR_ISP:
|
||||
if (m68k_feature(env, M68K_FEATURE_M68020)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68030)
|
||||
|| m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
return env->sp[M68K_ISP];
|
||||
}
|
||||
break;
|
||||
/* MC68040/MC68LC040 */
|
||||
case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
return env->mmu.ttr[M68K_ITTR0];
|
||||
}
|
||||
break;
|
||||
/* MC68040/MC68LC040 */
|
||||
case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
return env->mmu.ttr[M68K_ITTR1];
|
||||
}
|
||||
break;
|
||||
/* MC68040/MC68LC040 */
|
||||
case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
return env->mmu.ttr[M68K_DTTR0];
|
||||
}
|
||||
break;
|
||||
/* MC68040/MC68LC040 */
|
||||
case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
return env->mmu.ttr[M68K_DTTR1];
|
||||
}
|
||||
break;
|
||||
/* Unimplemented Registers */
|
||||
case M68K_CR_CAAR:
|
||||
case M68K_CR_PCR:
|
||||
case M68K_CR_BUSCR:
|
||||
cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
|
||||
reg);
|
||||
}
|
||||
cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
|
||||
reg);
|
||||
|
||||
/* Invalid control registers will generate an exception. */
|
||||
raise_exception_ra(env, EXCP_ILLEGAL, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void HELPER(set_macsr)(CPUM68KState *env, uint32_t val)
|
||||
|
|
@ -334,7 +463,8 @@ void m68k_switch_sp(CPUM68KState *env)
|
|||
env->sp[env->current_sp] = env->aregs[7];
|
||||
if (m68k_feature(env, M68K_FEATURE_M68000)) {
|
||||
if (env->sr & SR_S) {
|
||||
if (env->sr & SR_M) {
|
||||
/* SR:Master-Mode bit unimplemented then ISP is not available */
|
||||
if (!m68k_feature(env, M68K_FEATURE_MSP) || env->sr & SR_M) {
|
||||
new_sp = M68K_SSP;
|
||||
} else {
|
||||
new_sp = M68K_ISP;
|
||||
|
|
|
|||
|
|
@ -6010,7 +6010,7 @@ void register_m68k_insns (CPUM68KState *env)
|
|||
BASE(stop, 4e72, ffff);
|
||||
BASE(rte, 4e73, ffff);
|
||||
INSN(cf_movec, 4e7b, ffff, CF_ISA_A);
|
||||
INSN(m68k_movec, 4e7a, fffe, M68000);
|
||||
INSN(m68k_movec, 4e7a, fffe, MOVEC);
|
||||
#endif
|
||||
BASE(nop, 4e71, ffff);
|
||||
INSN(rtd, 4e74, ffff, RTD);
|
||||
|
|
|
|||
Loading…
Reference in New Issue