OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/riscv/cpu.c: export set_misa() 

We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
patch and set_misa() needs to be usable from there.

Rename it to riscv_cpu_set_misa() and make it public.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-09-25 14:57:04 -03:00 committed by Alistair Francis
parent efa365b711
commit f51d03b01f
2 changed files with 19 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
target/riscv/cpu.c
View File

@ -294,7 +294,7 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
} }
} }
static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
{ {
env->misa_mxl_max = env->misa_mxl = mxl; env->misa_mxl_max = env->misa_mxl = mxl;
env->misa_ext_mask = env->misa_ext = ext; env->misa_ext_mask = env->misa_ext = ext;
@ -399,9 +399,9 @@ static void riscv_any_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
#if defined(TARGET_RISCV32) #if defined(TARGET_RISCV32)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#elif defined(TARGET_RISCV64) #elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif #endif
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -428,7 +428,7 @@ static void riscv_max_cpu_init(Object *obj)
#ifdef TARGET_RISCV32 #ifdef TARGET_RISCV32
mlx = MXL_RV32; mlx = MXL_RV32;
#endif #endif
set_misa(env, mlx, 0); riscv_cpu_set_misa(env, mlx, 0);
env->priv_ver = PRIV_VERSION_LATEST; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ? set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@ -441,7 +441,7 @@ static void rv64_base_cpu_init(Object *obj)
{ {
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */ /* We set this in the realise function */
set_misa(env, MXL_RV64, 0); riscv_cpu_set_misa(env, MXL_RV64, 0);
/* Set latest version of privileged specification */ /* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -453,7 +453,8 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{ {
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); riscv_cpu_set_misa(env, MXL_RV64,
RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0; env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@ -471,7 +472,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0; env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE); set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@ -488,7 +489,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_11_0; env->priv_ver = PRIV_VERSION_1_11_0;
cpu->cfg.ext_zfa = true; cpu->cfg.ext_zfa = true;
@ -519,7 +520,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
env->priv_ver = PRIV_VERSION_1_12_0; env->priv_ver = PRIV_VERSION_1_12_0;
/* Enable ISA extensions */ /* Enable ISA extensions */
@ -564,7 +565,7 @@ static void rv128_base_cpu_init(Object *obj)
} }
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */ /* We set this in the realise function */
set_misa(env, MXL_RV128, 0); riscv_cpu_set_misa(env, MXL_RV128, 0);
/* Set latest version of privileged specification */ /* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -576,7 +577,7 @@ static void rv32_base_cpu_init(Object *obj)
{ {
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */ /* We set this in the realise function */
set_misa(env, MXL_RV32, 0); riscv_cpu_set_misa(env, MXL_RV32, 0);
/* Set latest version of privileged specification */ /* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -588,7 +589,8 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{ {
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); riscv_cpu_set_misa(env, MXL_RV32,
RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0; env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
@ -606,7 +608,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0; env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE); set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@ -623,7 +625,7 @@ static void rv32_ibex_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_11_0; env->priv_ver = PRIV_VERSION_1_11_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE); set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@ -641,7 +643,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0; env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE); set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@ -1614,7 +1616,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
const RISCVCPUMultiExtConfig *prop; const RISCVCPUMultiExtConfig *prop;
/* Enable RVG, RVJ and RVV that are disabled by default */ /* Enable RVG, RVJ and RVV that are disabled by default */
set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
isa_ext_update_enabled(cpu, prop->offset, true); isa_ext_update_enabled(cpu, prop->offset, true);

1
target/riscv/cpu.h
View File

@ -713,6 +713,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
int cpu_cfg_ext_get_min_version(uint32_t ext_offset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
typedef struct RISCVCPUMultiExtConfig { typedef struct RISCVCPUMultiExtConfig {