target-ppc: Add xscvdphp, xscvhpdp
xscvdphp: VSX Scalar round & Convert Double-Precision format to
Half-Precision format
xscvhpdp: VSX Scalar Convert Half-Precision format to
Double-Precision format
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Bharata B Rao
David Gibson
parent
ffc67420f9
commit
f566c0474a
@ -356,6 +356,26 @@ static inline int float16_is_any_nan(float16 a)
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return ((float16_val(a) & ~0x8000) > 0x7c00);
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}
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static inline int float16_is_neg(float16 a)
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{
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return float16_val(a) >> 15;
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}
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static inline int float16_is_infinity(float16 a)
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{
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return (float16_val(a) & 0x7fff) == 0x7c00;
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}
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static inline int float16_is_zero(float16 a)
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{
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return (float16_val(a) & 0x7fff) == 0;
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}
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static inline int float16_is_zero_or_denormal(float16 a)
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{
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return (float16_val(a) & 0x7c00) == 0;
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}
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/*----------------------------------------------------------------------------
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| The pattern for a default generated half-precision NaN.
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*----------------------------------------------------------------------------*/
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@ -24,6 +24,7 @@
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#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
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#define float32_snan_to_qnan(x) ((x) | 0x00400000)
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#define float16_snan_to_qnan(x) ((x) | 0x0200)
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/*****************************************************************************/
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/* Floating point operations helpers */
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@ -107,6 +108,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
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env->fpscr |= fprf << FPSCR_FPRF; \
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}
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COMPUTE_FPRF(float16)
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COMPUTE_FPRF(float64)
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/* Floating-point invalid operations exception */
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@ -2664,6 +2666,37 @@ VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
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VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0)
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VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0)
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/* VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
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* involving one half precision value
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* op - instruction mnemonic
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* stp - source type
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* ttp - target type
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* sfld - source vsr_t field
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* tfld - target vsr_t field
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*/
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#define VSX_CVT_FP_TO_FP_HP(op, stp, ttp, sfld, tfld) \
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void helper_##op(CPUPPCState *env, uint32_t opcode) \
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{ \
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ppc_vsr_t xt, xb; \
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\
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getVSR(xB(opcode), &xb, env); \
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memset(&xt, 0, sizeof(xt)); \
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\
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xt.tfld = stp##_to_##ttp(xb.sfld, 1, &env->fp_status); \
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if (unlikely(stp##_is_signaling_nan(xb.sfld, \
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&env->fp_status))) { \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
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xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
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} \
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helper_compute_fprf_##ttp(env, xt.tfld); \
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\
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putVSR(xT(opcode), &xt, env); \
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float_check_status(env); \
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}
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VSX_CVT_FP_TO_FP_HP(xscvdphp, float64, float16, VsrD(0), VsrH(3))
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VSX_CVT_FP_TO_FP_HP(xscvhpdp, float16, float64, VsrH(3), VsrD(0))
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uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
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{
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float_status tstat = env->fp_status;
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@ -423,8 +423,10 @@ DEF_HELPER_2(xscmpoqp, void, env, i32)
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DEF_HELPER_2(xscmpuqp, void, env, i32)
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DEF_HELPER_2(xsmaxdp, void, env, i32)
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DEF_HELPER_2(xsmindp, void, env, i32)
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DEF_HELPER_2(xscvdphp, void, env, i32)
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DEF_HELPER_2(xscvdpsp, void, env, i32)
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DEF_HELPER_2(xscvdpspn, i64, env, i64)
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DEF_HELPER_2(xscvhpdp, void, env, i32)
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DEF_HELPER_2(xscvspdp, void, env, i32)
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DEF_HELPER_2(xscvspdpn, i64, env, i64)
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DEF_HELPER_2(xscvdpsxds, void, env, i32)
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@ -211,10 +211,12 @@ typedef union _ppc_vsr_t {
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#if defined(HOST_WORDS_BIGENDIAN)
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#define VsrB(i) u8[i]
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#define VsrH(i) u16[i]
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#define VsrW(i) u32[i]
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#define VsrD(i) u64[i]
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#else
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#define VsrB(i) u8[15 - (i)]
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#define VsrH(i) u16[7 - (i)]
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#define VsrW(i) u32[3 - (i)]
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#define VsrD(i) u64[1 - (i)]
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#endif
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@ -241,4 +243,5 @@ static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
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}
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}
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void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
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#endif /* PPC_INTERNAL_H */
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@ -805,8 +805,10 @@ GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
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GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
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GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
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GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
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GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
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@ -151,8 +151,10 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
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GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
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GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
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GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
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GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
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GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
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GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
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GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300),
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GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
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GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
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GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
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