hw/mem/cxl-type3: Add CXL CDAT Data Object Exchange
The CDAT can be specified in two ways. One is to add ",cdat=<filename>" in "-device cxl-type3"'s command option. The file is required to provide the whole CDAT table in binary mode. The other is to use the default that provides some 'reasonable' numbers based on type of memory and size. The DOE capability supporting CDAT is added to hw/mem/cxl_type3.c with capability offset 0x190. The config read/write to this capability range can be generated in the OS to request the CDAT data. Signed-off-by: Huai-Cheng Kuo <hchkuo@avery-design.com.tw> Signed-off-by: Chris Browy <cbrowy@avery-design.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20221014151045.24781-5-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Huai-Cheng Kuo
Michael S. Tsirkin
parent
aba578bdac
commit
f5ee7413d5
@ -12,9 +12,246 @@
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#include "qemu/range.h"
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#include "qemu/rcu.h"
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#include "sysemu/hostmem.h"
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#include "sysemu/numa.h"
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#include "hw/cxl/cxl.h"
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#include "hw/pci/msix.h"
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#define DWORD_BYTE 4
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/* Default CDAT entries for a memory region */
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enum {
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CT3_CDAT_DSMAS,
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CT3_CDAT_DSLBIS0,
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CT3_CDAT_DSLBIS1,
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CT3_CDAT_DSLBIS2,
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CT3_CDAT_DSLBIS3,
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CT3_CDAT_DSEMTS,
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CT3_CDAT_NUM_ENTRIES
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};
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static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
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int dsmad_handle, MemoryRegion *mr)
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{
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g_autofree CDATDsmas *dsmas = NULL;
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g_autofree CDATDslbis *dslbis0 = NULL;
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g_autofree CDATDslbis *dslbis1 = NULL;
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g_autofree CDATDslbis *dslbis2 = NULL;
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g_autofree CDATDslbis *dslbis3 = NULL;
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g_autofree CDATDsemts *dsemts = NULL;
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dsmas = g_malloc(sizeof(*dsmas));
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if (!dsmas) {
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return -ENOMEM;
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}
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*dsmas = (CDATDsmas) {
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.header = {
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.type = CDAT_TYPE_DSMAS,
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.length = sizeof(*dsmas),
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},
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.DSMADhandle = dsmad_handle,
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.flags = CDAT_DSMAS_FLAG_NV,
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.DPA_base = 0,
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.DPA_length = int128_get64(mr->size),
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};
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/* For now, no memory side cache, plausiblish numbers */
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dslbis0 = g_malloc(sizeof(*dslbis0));
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if (!dslbis0) {
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return -ENOMEM;
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}
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*dslbis0 = (CDATDslbis) {
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.header = {
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.type = CDAT_TYPE_DSLBIS,
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.length = sizeof(*dslbis0),
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},
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.handle = dsmad_handle,
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.flags = HMAT_LB_MEM_MEMORY,
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.data_type = HMAT_LB_DATA_READ_LATENCY,
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.entry_base_unit = 10000, /* 10ns base */
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.entry[0] = 15, /* 150ns */
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};
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dslbis1 = g_malloc(sizeof(*dslbis1));
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if (!dslbis1) {
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return -ENOMEM;
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}
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*dslbis1 = (CDATDslbis) {
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.header = {
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.type = CDAT_TYPE_DSLBIS,
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.length = sizeof(*dslbis1),
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},
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.handle = dsmad_handle,
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.flags = HMAT_LB_MEM_MEMORY,
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.data_type = HMAT_LB_DATA_WRITE_LATENCY,
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.entry_base_unit = 10000,
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.entry[0] = 25, /* 250ns */
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};
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dslbis2 = g_malloc(sizeof(*dslbis2));
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if (!dslbis2) {
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return -ENOMEM;
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}
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*dslbis2 = (CDATDslbis) {
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.header = {
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.type = CDAT_TYPE_DSLBIS,
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.length = sizeof(*dslbis2),
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},
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.handle = dsmad_handle,
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.flags = HMAT_LB_MEM_MEMORY,
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.data_type = HMAT_LB_DATA_READ_BANDWIDTH,
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.entry_base_unit = 1000, /* GB/s */
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.entry[0] = 16,
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};
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dslbis3 = g_malloc(sizeof(*dslbis3));
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if (!dslbis3) {
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return -ENOMEM;
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}
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*dslbis3 = (CDATDslbis) {
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.header = {
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.type = CDAT_TYPE_DSLBIS,
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.length = sizeof(*dslbis3),
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},
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.handle = dsmad_handle,
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.flags = HMAT_LB_MEM_MEMORY,
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.data_type = HMAT_LB_DATA_WRITE_BANDWIDTH,
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.entry_base_unit = 1000, /* GB/s */
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.entry[0] = 16,
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};
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dsemts = g_malloc(sizeof(*dsemts));
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if (!dsemts) {
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return -ENOMEM;
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}
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*dsemts = (CDATDsemts) {
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.header = {
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.type = CDAT_TYPE_DSEMTS,
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.length = sizeof(*dsemts),
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},
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.DSMAS_handle = dsmad_handle,
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/* Reserved - the non volatile from DSMAS matters */
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.EFI_memory_type_attr = 2,
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.DPA_offset = 0,
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.DPA_length = int128_get64(mr->size),
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};
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/* Header always at start of structure */
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cdat_table[CT3_CDAT_DSMAS] = g_steal_pointer(&dsmas);
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cdat_table[CT3_CDAT_DSLBIS0] = g_steal_pointer(&dslbis0);
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cdat_table[CT3_CDAT_DSLBIS1] = g_steal_pointer(&dslbis1);
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cdat_table[CT3_CDAT_DSLBIS2] = g_steal_pointer(&dslbis2);
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cdat_table[CT3_CDAT_DSLBIS3] = g_steal_pointer(&dslbis3);
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cdat_table[CT3_CDAT_DSEMTS] = g_steal_pointer(&dsemts);
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return 0;
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}
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static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
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{
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g_autofree CDATSubHeader **table = NULL;
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MemoryRegion *nonvolatile_mr;
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CXLType3Dev *ct3d = priv;
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int dsmad_handle = 0;
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int rc;
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if (!ct3d->hostmem) {
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return 0;
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}
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nonvolatile_mr = host_memory_backend_get_memory(ct3d->hostmem);
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if (!nonvolatile_mr) {
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return -EINVAL;
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}
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table = g_malloc0(CT3_CDAT_NUM_ENTRIES * sizeof(*table));
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if (!table) {
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return -ENOMEM;
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}
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rc = ct3_build_cdat_entries_for_mr(table, dsmad_handle++, nonvolatile_mr);
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if (rc < 0) {
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return rc;
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}
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*cdat_table = g_steal_pointer(&table);
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return CT3_CDAT_NUM_ENTRIES;
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}
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static void ct3_free_cdat_table(CDATSubHeader **cdat_table, int num, void *priv)
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{
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int i;
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for (i = 0; i < num; i++) {
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g_free(cdat_table[i]);
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}
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g_free(cdat_table);
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}
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static bool cxl_doe_cdat_rsp(DOECap *doe_cap)
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{
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CDATObject *cdat = &CXL_TYPE3(doe_cap->pdev)->cxl_cstate.cdat;
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uint16_t ent;
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void *base;
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uint32_t len;
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CDATReq *req = pcie_doe_get_write_mbox_ptr(doe_cap);
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CDATRsp rsp;
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assert(cdat->entry_len);
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/* Discard if request length mismatched */
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if (pcie_doe_get_obj_len(req) <
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DIV_ROUND_UP(sizeof(CDATReq), DWORD_BYTE)) {
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return false;
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}
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ent = req->entry_handle;
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base = cdat->entry[ent].base;
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len = cdat->entry[ent].length;
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rsp = (CDATRsp) {
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.header = {
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.vendor_id = CXL_VENDOR_ID,
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.data_obj_type = CXL_DOE_TABLE_ACCESS,
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.reserved = 0x0,
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.length = DIV_ROUND_UP((sizeof(rsp) + len), DWORD_BYTE),
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},
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.rsp_code = CXL_DOE_TAB_RSP,
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.table_type = CXL_DOE_TAB_TYPE_CDAT,
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.entry_handle = (ent < cdat->entry_len - 1) ?
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ent + 1 : CXL_DOE_TAB_ENT_MAX,
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};
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memcpy(doe_cap->read_mbox, &rsp, sizeof(rsp));
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memcpy(doe_cap->read_mbox + DIV_ROUND_UP(sizeof(rsp), DWORD_BYTE),
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base, len);
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doe_cap->read_mbox_len += rsp.header.length;
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return true;
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}
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static uint32_t ct3d_config_read(PCIDevice *pci_dev, uint32_t addr, int size)
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{
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CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
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uint32_t val;
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if (pcie_doe_read_config(&ct3d->doe_cdat, addr, size, &val)) {
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return val;
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}
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return pci_default_read_config(pci_dev, addr, size);
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}
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static void ct3d_config_write(PCIDevice *pci_dev, uint32_t addr, uint32_t val,
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int size)
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{
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CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
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pcie_doe_write_config(&ct3d->doe_cdat, addr, val, size);
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pci_default_write_config(pci_dev, addr, val, size);
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}
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/*
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* Null value of all Fs suggested by IEEE RA guidelines for use of
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* EU, OUI and CID
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@ -140,6 +377,11 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
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return true;
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}
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static DOEProtocol doe_cdat_prot[] = {
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{ CXL_VENDOR_ID, CXL_DOE_TABLE_ACCESS, cxl_doe_cdat_rsp },
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{ }
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};
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static void ct3_realize(PCIDevice *pci_dev, Error **errp)
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{
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CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
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@ -189,6 +431,14 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
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for (i = 0; i < msix_num; i++) {
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msix_vector_use(pci_dev, i);
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}
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/* DOE Initailization */
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pcie_doe_init(pci_dev, &ct3d->doe_cdat, 0x190, doe_cdat_prot, true, 0);
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cxl_cstate->cdat.build_cdat_table = ct3_build_cdat_table;
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cxl_cstate->cdat.free_cdat_table = ct3_free_cdat_table;
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cxl_cstate->cdat.private = ct3d;
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cxl_doe_cdat_init(cxl_cstate, errp);
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}
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static void ct3_exit(PCIDevice *pci_dev)
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@ -197,6 +447,7 @@ static void ct3_exit(PCIDevice *pci_dev)
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CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
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ComponentRegisters *regs = &cxl_cstate->crb;
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cxl_doe_cdat_release(cxl_cstate);
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g_free(regs->special_ops);
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address_space_destroy(&ct3d->hostmem_as);
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}
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@ -296,6 +547,7 @@ static Property ct3_props[] = {
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DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND,
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HostMemoryBackend *),
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DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL),
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DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -361,6 +613,9 @@ static void ct3_class_init(ObjectClass *oc, void *data)
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pc->device_id = 0xd93; /* LVF for now */
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pc->revision = 1;
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pc->config_write = ct3d_config_write;
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pc->config_read = ct3d_config_read;
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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dc->desc = "CXL PMEM Device (Type 3)";
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dc->reset = ct3d_reset;
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