tests/tcg/aarch64: add system boot.S
This provides the bootstrap and low level helper functions for an aarch64 kernel. We use semihosting to handle test output and exiting the emulation. semihosting's parameter passing is a little funky so we end up using the stack and pointing to that as the parameter block. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Alex Bennée
parent
9699e5fb5a
commit
f6482872f3
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#
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# Aarch64 system tests
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#
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AARCH64_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/aarch64/system
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VPATH+=$(AARCH64_SYSTEM_SRC)
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# These objects provide the basic boot code and helper functions for all tests
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CRT_OBJS=boot.o
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AARCH64_TEST_SRCS=$(wildcard $(AARCH64_SYSTEM_SRC)/*.c)
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AARCH64_TESTS = $(patsubst $(AARCH64_SYSTEM_SRC)/%.c, %, $(AARCH64_TEST_SRCS))
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CRT_PATH=$(AARCH64_SYSTEM_SRC)
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LINK_SCRIPT=$(AARCH64_SYSTEM_SRC)/kernel.ld
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LDFLAGS=-Wl,-T$(LINK_SCRIPT)
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TESTS+=$(AARCH64_TESTS) $(MULTIARCH_TESTS)
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CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC)
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LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc
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# building head blobs
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.PRECIOUS: $(CRT_OBJS)
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%.o: $(CRT_PATH)/%.S
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$(CC) $(CFLAGS) -x assembler-with-cpp -c $< -o $@
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# Build and link the tests
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%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
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$(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)
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# Running
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QEMU_OPTS+=-M virt -cpu max -display none -semihosting-config enable=on,target=native,chardev=output -kernel
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/*
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* Minimal AArch64 system boot code.
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*
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* Copyright Linaro Ltd 2019
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*
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* Loosely based on the newlib/libgloss setup stubs. Using semihosting
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* for serial output and exit functions.
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*/
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/*
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* Semihosting interface on ARM AArch64
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* See "Semihosting for AArch32 and AArch64 Relase 2.0" by ARM
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* w0 - semihosting call number
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* x1 - semihosting parameter
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*/
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#define semihosting_call hlt 0xf000
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#define SYS_WRITEC 0x03 /* character to debug channel */
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#define SYS_WRITE0 0x04 /* string to debug channel */
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#define SYS_EXIT 0x18
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.align 12
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.macro ventry label
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.align 7
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b \label
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.endm
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vector_table:
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/* Current EL with SP0. */
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ventry curr_sp0_sync /* Synchronous */
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ventry curr_sp0_irq /* Irq/vIRQ */
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ventry curr_sp0_fiq /* Fiq/vFIQ */
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ventry curr_sp0_serror /* SError/VSError */
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/* Current EL with SPx. */
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ventry curr_spx_sync /* Synchronous */
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ventry curr_spx_irq /* IRQ/vIRQ */
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ventry curr_spx_fiq /* FIQ/vFIQ */
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ventry curr_spx_serror /* SError/VSError */
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/* Lower EL using AArch64. */
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ventry lower_a64_sync /* Synchronous */
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ventry lower_a64_irq /* IRQ/vIRQ */
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ventry lower_a64_fiq /* FIQ/vFIQ */
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ventry lower_a64_serror /* SError/VSError */
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/* Lower EL using AArch32. */
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ventry lower_a32_sync /* Synchronous */
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ventry lower_a32_irq /* IRQ/vIRQ */
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ventry lower_a32_fiq /* FIQ/vFIQ */
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ventry lower_a32_serror /* SError/VSError */
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.text
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.align 4
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/* Common vector handling for now */
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curr_sp0_sync:
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curr_sp0_irq:
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curr_sp0_fiq:
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curr_sp0_serror:
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curr_spx_sync:
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curr_spx_irq:
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curr_spx_fiq:
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curr_spx_serror:
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lower_a64_sync:
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lower_a64_irq:
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lower_a64_fiq:
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lower_a64_serror:
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lower_a32_sync:
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lower_a32_irq:
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lower_a32_fiq:
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lower_a32_serror:
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mov x0, SYS_WRITE0
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adr x1, .error
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semihosting_call
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mov x0, SYS_EXIT
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mov x1, 1
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semihosting_call
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/* never returns */
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.section .rodata
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.error:
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.string "Terminated by exception.\n"
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.text
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.align 4
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.global __start
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__start:
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/* Installs a table of exception vectors to catch and handle all
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exceptions by terminating the process with a diagnostic. */
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adr x0, vector_table
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msr vbar_el1, x0
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/* Page table setup (identity mapping). */
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adrp x0, ttb
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add x0, x0, :lo12:ttb
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msr ttbr0_el1, x0
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/*
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* Setup a flat address mapping page-tables. Stage one simply
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* maps RAM to the first Gb. The stage2 tables have two 2mb
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* translation block entries covering a series of adjacent
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* 4k pages.
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*/
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/* Stage 1 entry: indexed by IA[38:30] */
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adr x1, . /* phys address */
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bic x1, x1, #(1 << 30) - 1 /* 1GB alignment*/
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add x2, x0, x1, lsr #(30 - 3) /* offset in l1 page table */
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/* point to stage 2 table [47:12] */
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adrp x0, ttb_stage2
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orr x1, x0, #3 /* ptr to stage 2 */
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str x1, [x2]
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/* Stage 2 entries: indexed by IA[29:21] */
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ldr x5, =(((1 << 9) - 1) << 21)
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/* First block: .text/RO/execute enabled */
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adr x1, . /* phys address */
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bic x1, x1, #(1 << 21) - 1 /* 2mb block alignment */
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and x4, x1, x5 /* IA[29:21] */
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add x2, x0, x4, lsr #(21 - 3) /* offset in l2 page table */
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ldr x3, =0x401 /* attr(AF, block) */
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orr x1, x1, x3
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str x1, [x2] /* 1st 2mb (.text & rodata) */
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/* Second block: .data/RW/no execute */
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adrp x1, .data
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add x1, x1, :lo12:.data
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bic x1, x1, #(1 << 21) - 1 /* 2mb block alignment */
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and x4, x1, x5 /* IA[29:21] */
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add x2, x0, x4, lsr #(21 - 3) /* offset in l2 page table */
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ldr x3, =(3 << 53) | 0x401 /* attr(AF, NX, block) */
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orr x1, x1, x3
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str x1, [x2] /* 2nd 2mb (.data & .bss)*/
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/* Setup/enable the MMU. */
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/*
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* TCR_EL1 - Translation Control Registers
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*
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* IPS[34:32] = 40-bit PA, 1TB
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* TG0[14:15] = b00 => 4kb granuale
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* ORGN0[11:10] = Outer: Normal, WB Read-Alloc No Write-Alloc Cacheable
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* IRGN0[9:8] = Inner: Normal, WB Read-Alloc No Write-Alloc Cacheable
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* T0SZ[5:0] = 2^(64 - 25)
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*
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* The size of T0SZ controls what the initial lookup level. It
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* would be nice to start at level 2 but unfortunatly for a
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* flat-mapping on the virt machine we need to handle IA's
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* with at least 1gb range to see RAM. So we start with a
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* level 1 lookup.
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*/
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ldr x0, = (2 << 32) | 25 | (3 << 10) | (3 << 8)
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msr tcr_el1, x0
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mov x0, #0xee /* Inner/outer cacheable WB */
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msr mair_el1, x0
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isb
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/*
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* SCTLR_EL1 - System Control Register
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*
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* WXN[19] = 0 = no effect, Write does not imply XN (execute never)
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* I[12] = Instruction cachability control
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* SA[3] = SP alignment check
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* C[2] = Data cachability control
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* M[0] = 1, enable stage 1 address translation for EL0/1
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*/
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mrs x0, sctlr_el1
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ldr x1, =0x100d /* bits I(12) SA(3) C(2) M(0) */
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bic x0, x0, #(1 << 1) /* clear bit A(1) */
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bic x0, x0, #(1 << 19) /* clear WXN */
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orr x0, x0, x1 /* set bits */
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dsb sy
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msr sctlr_el1, x0
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isb
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/*
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* Enable FP registers. The standard C pre-amble will be
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* saving these and A-profile compilers will use AdvSIMD
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* registers unless we tell it not to.
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*/
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mrs x0, cpacr_el1
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orr x0, x0, #(3 << 20)
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msr cpacr_el1, x0
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/* Setup some stack space and enter the test code.
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* Assume everthing except the return value is garbage when we
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* return, we won't need it.
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*/
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adrp x0, stack_end
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add x0, x0, :lo12:stack_end
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mov sp, x0
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bl main
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/* pass return value to sys exit */
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mov x1, x0
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ldr x0, =0x20026 /* ADP_Stopped_ApplicationExit */
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stp x0, x1, [sp, #-16]!
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mov x1, sp
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mov x0, SYS_EXIT
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semihosting_call
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/* never returns */
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/*
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* Helper Functions
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*/
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/* Output a single character to serial port */
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.global __sys_outc
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__sys_outc:
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stp x0, x1, [sp, #-16]!
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/* pass address of c on stack */
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mov x1, sp
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mov x0, SYS_WRITEC
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semihosting_call
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ldp x0, x1, [sp], #16
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ret
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.data
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.align 12
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/* Translation table
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* @4k granuale: 9 bit lookup, 512 entries
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*/
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ttb:
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.space 4096, 0
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.align 12
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ttb_stage2:
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.space 4096, 0
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.align 12
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stack:
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.space 65536, 0
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stack_end:
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@ -0,0 +1,24 @@
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ENTRY(__start)
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SECTIONS
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{
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/* virt machine, RAM starts at 1gb */
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. = (1 << 30);
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.text : {
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*(.text)
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}
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.rodata : {
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*(.rodata)
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}
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/* align r/w section to next 2mb */
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. = ALIGN(1 << 21);
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.data : {
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*(.data)
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}
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.bss : {
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*(.bss)
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}
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/DISCARD/ : {
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*(.ARM.attributes)
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}
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}
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