ETRAX: Add support for the ethernet receivers dest addr filters.
* Support the station address filters MA0 and MA1. * Model the group address bloom filter. * Indentation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4487 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
57e49b4074
commit
f6953f1345
207
hw/etraxfs_eth.c
207
hw/etraxfs_eth.c
@ -53,13 +53,13 @@ static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req)
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switch (regnum) {
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case 1:
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/* MR1. */
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/* MR1. */
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/* Speeds and modes. */
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r |= (1 << 13) | (1 << 14);
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r |= (1 << 11) | (1 << 12);
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r |= (1 << 5); /* Autoneg complete. */
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r |= (1 << 3); /* Autoneg able. */
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r |= (1 << 2); /* Link. */
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r |= (1 << 3); /* Autoneg able. */
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r |= (1 << 2); /* Link. */
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break;
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case 5:
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/* Link partner ability.
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@ -123,7 +123,7 @@ tdk_init(struct qemu_phy *phy)
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struct qemu_mdio
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{
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/* bus. */
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/* bus. */
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int mdc;
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int mdio;
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@ -285,19 +285,30 @@ static void mdio_cycle(struct qemu_mdio *bus)
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/* ETRAX-FS Ethernet MAC block starts here. */
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#define R_STAT 0x2c
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#define RW_MGM_CTRL 0x28
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#define FS_ETH_MAX_REGS 0x5c
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#define RW_MA0_LO 0x00
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#define RW_MA0_HI 0x04
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#define RW_MA1_LO 0x08
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#define RW_MA1_HI 0x0c
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#define RW_GA_LO 0x10
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#define RW_GA_HI 0x14
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#define RW_GEN_CTRL 0x18
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#define RW_REC_CTRL 0x1c
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#define RW_TR_CTRL 0x20
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#define RW_CLR_ERR 0x24
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#define RW_MGM_CTRL 0x28
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#define R_STAT 0x2c
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#define FS_ETH_MAX_REGS 0x5c
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struct fs_eth
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{
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CPUState *env;
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CPUState *env;
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qemu_irq *irq;
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target_phys_addr_t base;
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target_phys_addr_t base;
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VLANClientState *vc;
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uint8_t macaddr[6];
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int ethregs;
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/* Two addrs in the filter. */
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uint8_t macaddr[2][6];
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uint32_t regs[FS_ETH_MAX_REGS];
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unsigned char rx_fifo[1536];
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@ -309,59 +320,100 @@ struct fs_eth
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/* MDIO bus. */
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struct qemu_mdio mdio_bus;
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/* PHY. */
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/* PHY. */
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struct qemu_phy phy;
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};
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static uint32_t eth_rinvalid (void *opaque, target_phys_addr_t addr)
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{
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struct fs_eth *eth = opaque;
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CPUState *env = eth->env;
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cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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addr, env->pc);
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return 0;
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struct fs_eth *eth = opaque;
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CPUState *env = eth->env;
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cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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addr, env->pc);
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return 0;
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}
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static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
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{
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struct fs_eth *eth = opaque;
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D(CPUState *env = eth->env);
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uint32_t r = 0;
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struct fs_eth *eth = opaque;
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D(CPUState *env = eth->env);
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uint32_t r = 0;
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/* Make addr relative to this instances base. */
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addr -= eth->base;
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switch (addr) {
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/* Make addr relative to this instances base. */
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addr -= eth->base;
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switch (addr) {
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case R_STAT:
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/* Attach an MDIO/PHY abstraction. */
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r = eth->mdio_bus.mdio & 1;
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break;
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default:
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default:
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r = eth->regs[addr];
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D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
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break;
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}
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return r;
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D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
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break;
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}
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return r;
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}
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static void
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eth_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct fs_eth *eth = opaque;
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CPUState *env = eth->env;
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cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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addr, env->pc);
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struct fs_eth *eth = opaque;
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CPUState *env = eth->env;
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cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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addr, env->pc);
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}
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static void eth_update_ma(struct fs_eth *eth, int ma)
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{
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int reg;
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int i = 0;
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ma &= 1;
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reg = RW_MA0_LO;
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if (ma)
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reg = RW_MA1_LO;
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eth->macaddr[ma][i++] = eth->regs[reg];
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eth->macaddr[ma][i++] = eth->regs[reg] >> 8;
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eth->macaddr[ma][i++] = eth->regs[reg] >> 16;
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eth->macaddr[ma][i++] = eth->regs[reg] >> 24;
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eth->macaddr[ma][i++] = eth->regs[reg + 4];
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eth->macaddr[ma][i++] = eth->regs[reg + 4] >> 8;
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D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma,
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eth->macaddr[ma][0], eth->macaddr[ma][1],
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eth->macaddr[ma][2], eth->macaddr[ma][3],
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eth->macaddr[ma][4], eth->macaddr[ma][5]));
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}
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static void
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eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct fs_eth *eth = opaque;
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CPUState *env = eth->env;
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struct fs_eth *eth = opaque;
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CPUState *env = eth->env;
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/* Make addr relative to this instances base. */
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addr -= eth->base;
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switch (addr)
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{
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case RW_MA0_LO:
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eth->regs[addr] = value;
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eth_update_ma(eth, 0);
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break;
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case RW_MA0_HI:
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eth->regs[addr] = value;
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eth_update_ma(eth, 0);
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break;
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case RW_MA1_LO:
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eth->regs[addr] = value;
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eth_update_ma(eth, 1);
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break;
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case RW_MA1_HI:
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eth->regs[addr] = value;
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eth_update_ma(eth, 1);
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break;
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/* Make addr relative to this instances base. */
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addr -= eth->base;
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switch (addr)
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{
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case RW_MGM_CTRL:
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/* Attach an MDIO/PHY abstraction. */
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if (value & 2)
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@ -371,11 +423,56 @@ eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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eth->mdio_bus.mdc = !!(value & 4);
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break;
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default:
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printf ("%s %x %x pc=%x\n",
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__func__, addr, value, env->pc);
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break;
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}
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default:
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eth->regs[addr] = value;
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printf ("%s %x %x pc=%x\n",
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__func__, addr, value, env->pc);
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break;
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}
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}
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/* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
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filter dropping group addresses we have not joined. The filter has 64
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bits (m). The has function is a simple nible xor of the group addr. */
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static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa)
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{
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unsigned int hsh;
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int m_individual = eth->regs[RW_REC_CTRL] & 4;
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int match;
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/* First bit on the wire of a MAC address signals multicast or
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physical address. */
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if (!m_individual && !sa[0] & 1)
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return 0;
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/* Calculate the hash index for the GA registers. */
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hsh = 0;
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hsh ^= (*sa) & 0x3f;
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hsh ^= ((*sa) >> 6) & 0x03;
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++sa;
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hsh ^= ((*sa) << 2) & 0x03c;
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hsh ^= ((*sa) >> 4) & 0xf;
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++sa;
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hsh ^= ((*sa) << 4) & 0x30;
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hsh ^= ((*sa) >> 2) & 0x3f;
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++sa;
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hsh ^= (*sa) & 0x3f;
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hsh ^= ((*sa) >> 6) & 0x03;
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++sa;
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hsh ^= ((*sa) << 2) & 0x03c;
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hsh ^= ((*sa) >> 4) & 0xf;
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++sa;
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hsh ^= ((*sa) << 4) & 0x30;
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hsh ^= ((*sa) >> 2) & 0x3f;
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hsh &= 63;
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if (hsh > 31)
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match = eth->regs[RW_GA_HI] & (1 << (hsh - 32));
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else
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match = eth->regs[RW_GA_LO] & (1 << hsh);
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D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh,
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eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match));
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return match;
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}
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static int eth_can_receive(void *opaque)
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@ -393,12 +490,33 @@ static int eth_can_receive(void *opaque)
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static void eth_receive(void *opaque, const uint8_t *buf, int size)
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{
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unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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struct fs_eth *eth = opaque;
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int use_ma0 = eth->regs[RW_REC_CTRL] & 1;
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int use_ma1 = eth->regs[RW_REC_CTRL] & 2;
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int r_bcast = eth->regs[RW_REC_CTRL] & 8;
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if (size < 12)
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return;
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D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
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buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
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use_ma0, use_ma1, r_bcast));
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/* Does the frame get through the address filters? */
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if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6))
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&& (!use_ma1 || memcmp(buf, eth->macaddr[1], 6))
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&& (!r_bcast || memcmp(buf, sa_bcast, 6))
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&& !eth_match_groupaddr(eth, buf))
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return;
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if (size > sizeof(eth->rx_fifo)) {
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/* TODO: signal error. */
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/* TODO: signal error. */
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} else if (eth->rx_fifo_len) {
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/* FIFO overrun. */
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} else {
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memcpy(eth->rx_fifo, buf, size);
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/* +4, HW passes the CRC to sw. */
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/* +4, HW passes the CRC to sw. */
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eth->rx_fifo_len = size + 4;
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eth->rx_fifo_pos = 0;
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}
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@ -471,7 +589,6 @@ void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
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eth->irq = irq;
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eth->dma_out = dma;
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eth->dma_in = dma + 1;
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memcpy(eth->macaddr, nd->macaddr, 6);
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/* Connect the phy. */
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tdk_init(ð->phy);
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