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hw/char/stm32f2xx_usart: fix TXE/TC bit handling 

I/O currently being synchronous, there is no reason to ever clear the
SR_TXE bit. However the SR_TC bit may be cleared by software writing
to the SR register, so set it on each write.

In addition, fix the reset value of the USART status register.

Signed-off-by: Richard Braun <rbraun@sceen.net>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
[PMM: removed XXX tag from comment, since it isn't something
 we need to come back and fix in QEMU]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Braun 2018-02-22 15:12:51 +00:00 committed by Peter Maydell
parent 1c3db49d39
commit f6bfe45af2
2 changed files with 14 additions and 5 deletions
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12
hw/char/stm32f2xx_usart.c
View File

@ -96,12 +96,10 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
switch (addr) {
case USART_SR:
retvalue = s->usart_sr;
s->usart_sr &= ~USART_SR_TC;
qemu_chr_fe_accept_input(&s->chr);
return retvalue;
case USART_DR:
DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
s->usart_sr |= USART_SR_TXE;
s->usart_sr &= ~USART_SR_RXNE;
qemu_chr_fe_accept_input(&s->chr);
qemu_set_irq(s->irq, 0);
@ -137,7 +135,9 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
switch (addr) {
case USART_SR:
if (value <= 0x3FF) {
s->usart_sr = value;
/* I/O being synchronous, TXE is always set. In addition, it may
only be set by hardware, so keep it set here. */
s->usart_sr = value | USART_SR_TXE;
} else {
s->usart_sr &= value;
}
@ -151,8 +151,12 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
/* XXX I/O are currently synchronous, making it impossible for
software to observe transient states where TXE or TC aren't
set. Unlike TXE however, which is read-only, software may
clear TC by writing 0 to the SR register, so set it again
on each write. */
s->usart_sr |= USART_SR_TC;
s->usart_sr &= ~USART_SR_TXE;
}
return;
case USART_BRR:

7
include/hw/char/stm32f2xx_usart.h
View File

@ -37,7 +37,12 @@
#define USART_CR3 0x14
#define USART_GTPR 0x18
#define USART_SR_RESET 0x00C00000
/*
* NB: The reset value mentioned in "24.6.1 Status register" seems bogus.
* Looking at "Table 98 USART register map and reset values", it seems it
* should be 0xc0, and that's how real hardware behaves.
*/
#define USART_SR_RESET (USART_SR_TXE | USART_SR_TC)
#define USART_SR_TXE (1 << 7)
#define USART_SR_TC (1 << 6)