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pl011: fix incorrect logic to set the RXFF flag 

The receive fifo full bit should be set when 1 character is received and
the fifo is disabled or when 16 characters are in the fifo.

Signed-off-by: Rob Herring <rob.herring@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1395166721-15716-4-git-send-email-robherring2@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Rob Herring 2014-03-18 13:18:41 -05:00 committed by Peter Maydell
parent ce8f0905a5
commit f72dbf3d26
1 changed files with 1 additions and 1 deletions
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2
hw/char/pl011.c
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@ -221,7 +221,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value)
s->read_fifo[slot] = value;
s->read_count++;
s->flags &= ~PL011_FLAG_RXFE;
if (s->cr & 0x10 || s->read_count == 16) {
if (!(s->lcr & 0x10) || s->read_count == 16) {
s->flags |= PL011_FLAG_RXFF;
}
if (s->read_count == s->read_trigger) {