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target/loongarch: Convert to 3-phase reset 

Convert the loongarch CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-id: 20221124115023.2437291-8-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-11-24 11:50:10 +00:00
parent e86787d33b
commit f78b49ae8d
2 changed files with 10 additions and 6 deletions
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12
target/loongarch/cpu.c
View File

@ -450,14 +450,16 @@ void loongarch_cpu_list(void)
g_slist_free(list); g_slist_free(list);
} }
static void loongarch_cpu_reset(DeviceState *dev) static void loongarch_cpu_reset_hold(Object *obj)
{ {
CPUState *cs = CPU(dev); CPUState *cs = CPU(obj);
LoongArchCPU *cpu = LOONGARCH_CPU(cs); LoongArchCPU *cpu = LOONGARCH_CPU(cs);
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
CPULoongArchState *env = &cpu->env; CPULoongArchState *env = &cpu->env;
lacc->parent_reset(dev); if (lacc->parent_phases.hold) {
lacc->parent_phases.hold(obj);
}
env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
env->fcsr0 = 0x0; env->fcsr0 = 0x0;
@ -694,10 +696,12 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c); DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_parent_realize(dc, loongarch_cpu_realizefn, device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
&lacc->parent_realize); &lacc->parent_realize);
device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset); resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL,
&lacc->parent_phases);
cc->class_by_name = loongarch_cpu_class_by_name; cc->class_by_name = loongarch_cpu_class_by_name;
cc->has_work = loongarch_cpu_has_work; cc->has_work = loongarch_cpu_has_work;

4
target/loongarch/cpu.h
View File

@ -356,7 +356,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
/** /**
* LoongArchCPUClass: * LoongArchCPUClass:
* @parent_realize: The parent class' realize handler. * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler. * @parent_phases: The parent class' reset phase handlers.
* *
* A LoongArch CPU model. * A LoongArch CPU model.
*/ */
@ -366,7 +366,7 @@ struct LoongArchCPUClass {
/*< public >*/ /*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; ResettablePhases parent_phases;
}; };
/* /*