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Merge remote-tracking branch 'stefanha/block' into staging 

# By Alex Bligh (32) and others
# Via Stefan Hajnoczi
* stefanha/block: (42 commits)
  win32-aio: drop win32_aio_flush_cb()
  aio-win32: replace incorrect AioHandler->opaque usage with ->e
  aio / timers: remove dummy_io_handler_flush from tests/test-aio.c
  aio / timers: Remove legacy interface
  aio / timers: Switch entire codebase to the new timer API
  aio / timers: Add scripts/switch-timer-api
  aio / timers: Add test harness for AioContext timers
  aio / timers: convert block_job_sleep_ns and co_sleep_ns to new API
  aio / timers: Convert rtc_clock to be a QEMUClockType
  aio / timers: Remove main_loop_timerlist
  aio / timers: Rearrange timer.h & make legacy functions call non-legacy
  aio / timers: Add qemu_clock_get_ms and qemu_clock_get_ms
  aio / timers: Remove legacy qemu_clock_deadline & qemu_timerlist_deadline
  aio / timers: Remove alarm timers
  aio / timers: Add documentation and new format calls
  aio / timers: Use all timerlists in icount warp calculations
  aio / timers: Introduce new API timer_new and friends
  aio / timers: On timer modification, qemu_notify or aio_notify
  aio / timers: Convert mainloop to use timeout
  aio / timers: Convert aio_poll to use AioContext timers' deadline
  ...

Message-id: 1377202298-22896-1-git-send-email-stefanha@redhat.com
Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
This commit is contained in:
Anthony Liguori 2013-08-26 09:19:50 -05:00
parent e3f024aec2 b10577df13
commit f7ad538e1e
177 changed files with 2373 additions and 1514 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
aio-posix.c
View File

@ -165,6 +165,10 @@ static bool aio_dispatch(AioContext *ctx)
g_free(tmp);
}
}
/* Run our timers */
progress |= timerlistgroup_run_timers(&ctx->tlg);
return progress;
}
@ -219,9 +223,9 @@ bool aio_poll(AioContext *ctx, bool blocking)
}
/* wait until next event */
ret = g_poll((GPollFD *)ctx->pollfds->data,
ctx->pollfds->len,
blocking ? -1 : 0);
ret = qemu_poll_ns((GPollFD *)ctx->pollfds->data,
ctx->pollfds->len,
blocking ? timerlistgroup_deadline_ns(&ctx->tlg) : 0);
/* if we have any readable fds, dispatch event */
if (ret > 0) {
@ -232,9 +236,11 @@ bool aio_poll(AioContext *ctx, bool blocking)
node->pfd.revents = pfd->revents;
}
}
if (aio_dispatch(ctx)) {
progress = true;
}
}
/* Run dispatch even if there were no readable fds to run timers */
if (aio_dispatch(ctx)) {
progress = true;
}
return progress;

24
aio-win32.c
View File

@ -95,6 +95,7 @@ bool aio_poll(AioContext *ctx, bool blocking)
HANDLE events[MAXIMUM_WAIT_OBJECTS + 1];
bool progress;
int count;
int timeout;
progress = false;
@ -108,6 +109,9 @@ bool aio_poll(AioContext *ctx, bool blocking)
progress = true;
}
/* Run timers */
progress |= timerlistgroup_run_timers(&ctx->tlg);
/*
* Then dispatch any pending callbacks from the GSource.
*
@ -125,7 +129,7 @@ bool aio_poll(AioContext *ctx, bool blocking)
node->io_notify(node->e);
/* aio_notify() does not count as progress */
if (node->opaque != &ctx->notifier) {
if (node->e != &ctx->notifier) {
progress = true;
}
}
@ -164,8 +168,11 @@ bool aio_poll(AioContext *ctx, bool blocking)
/* wait until next event */
while (count > 0) {
int timeout = blocking ? INFINITE : 0;
int ret = WaitForMultipleObjects(count, events, FALSE, timeout);
int ret;
timeout = blocking ?
qemu_timeout_ns_to_ms(timerlistgroup_deadline_ns(&ctx->tlg)) : 0;
ret = WaitForMultipleObjects(count, events, FALSE, timeout);
/* if we have any signaled events, dispatch event */
if ((DWORD) (ret - WAIT_OBJECT_0) >= count) {
@ -188,7 +195,7 @@ bool aio_poll(AioContext *ctx, bool blocking)
node->io_notify(node->e);
/* aio_notify() does not count as progress */
if (node->opaque != &ctx->notifier) {
if (node->e != &ctx->notifier) {
progress = true;
}
}
@ -208,5 +215,14 @@ bool aio_poll(AioContext *ctx, bool blocking)
events[ret - WAIT_OBJECT_0] = events[--count];
}
if (blocking) {
/* Run the timers a second time. We do this because otherwise aio_wait
* will not note progress - and will stop a drain early - if we have
* a timer that was not ready to run entering g_poll but is ready
* after g_poll. This will only do anything if a timer has expired.
*/
progress |= timerlistgroup_run_timers(&ctx->tlg);
}
return progress;
}

12
arch_init.c
View File

@ -392,7 +392,7 @@ static void migration_bitmap_sync(void)
}
if (!start_time) {
start_time = qemu_get_clock_ms(rt_clock);
start_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
}
trace_migration_bitmap_sync_start();
@ -410,7 +410,7 @@ static void migration_bitmap_sync(void)
trace_migration_bitmap_sync_end(migration_dirty_pages
- num_dirty_pages_init);
num_dirty_pages_period += migration_dirty_pages - num_dirty_pages_init;
end_time = qemu_get_clock_ms(rt_clock);
end_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
/* more than 1 second = 1000 millisecons */
if (end_time > start_time + 1000) {
@ -672,7 +672,7 @@ static int ram_save_iterate(QEMUFile *f, void *opaque)
ram_control_before_iterate(f, RAM_CONTROL_ROUND);
t0 = qemu_get_clock_ns(rt_clock);
t0 = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
i = 0;
while ((ret = qemu_file_rate_limit(f)) == 0) {
int bytes_sent;
@ -691,7 +691,7 @@ static int ram_save_iterate(QEMUFile *f, void *opaque)
iterations
*/
if ((i & 63) == 0) {
uint64_t t1 = (qemu_get_clock_ns(rt_clock) - t0) / 1000000;
uint64_t t1 = (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - t0) / 1000000;
if (t1 > MAX_WAIT) {
DPRINTF("big wait: %" PRIu64 " milliseconds, %d iterations\n",
t1, i);
@ -1217,11 +1217,11 @@ static void check_guest_throttling(void)
}
if (!t0) {
t0 = qemu_get_clock_ns(rt_clock);
t0 = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
return;
}
t1 = qemu_get_clock_ns(rt_clock);
t1 = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
/* If it has been more than 40 ms since the last time the guest
* was throttled then do it again.

20
async.c
View File

@ -150,7 +150,10 @@ aio_ctx_prepare(GSource *source, gint *timeout)
{
AioContext *ctx = (AioContext *) source;
QEMUBH *bh;
int deadline;
/* We assume there is no timeout already supplied */
*timeout = -1;
for (bh = ctx->first_bh; bh; bh = bh->next) {
if (!bh->deleted && bh->scheduled) {
if (bh->idle) {
@ -166,6 +169,14 @@ aio_ctx_prepare(GSource *source, gint *timeout)
}
}
deadline = qemu_timeout_ns_to_ms(timerlistgroup_deadline_ns(&ctx->tlg));
if (deadline == 0) {
*timeout = 0;
return true;
} else {
*timeout = qemu_soonest_timeout(*timeout, deadline);
}
return false;
}
@ -180,7 +191,7 @@ aio_ctx_check(GSource *source)
return true;
}
}
return aio_pending(ctx);
return aio_pending(ctx) || (timerlistgroup_deadline_ns(&ctx->tlg) == 0);
}
static gboolean
@ -205,6 +216,7 @@ aio_ctx_finalize(GSource *source)
event_notifier_cleanup(&ctx->notifier);
qemu_mutex_destroy(&ctx->bh_lock);
g_array_free(ctx->pollfds, TRUE);
timerlistgroup_deinit(&ctx->tlg);
}
static GSourceFuncs aio_source_funcs = {
@ -233,6 +245,11 @@ void aio_notify(AioContext *ctx)
event_notifier_set(&ctx->notifier);
}
static void aio_timerlist_notify(void *opaque)
{
aio_notify(opaque);
}
AioContext *aio_context_new(void)
{
AioContext *ctx;
@ -244,6 +261,7 @@ AioContext *aio_context_new(void)
aio_set_event_notifier(ctx, &ctx->notifier,
(EventNotifierHandler *)
event_notifier_test_and_clear);
timerlistgroup_init(&ctx->tlg, aio_timerlist_notify, ctx);
return ctx;
}

6
audio/audio.c
View File

@ -1124,10 +1124,10 @@ static int audio_is_timer_needed (void)
static void audio_reset_timer (AudioState *s)
{
if (audio_is_timer_needed ()) {
qemu_mod_timer (s->ts, qemu_get_clock_ns (vm_clock) + 1);
timer_mod (s->ts, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1);
}
else {
qemu_del_timer (s->ts);
timer_del (s->ts);
}
}
@ -1834,7 +1834,7 @@ static void audio_init (void)
QLIST_INIT (&s->cap_head);
atexit (audio_atexit);
s->ts = qemu_new_timer_ns (vm_clock, audio_timer, s);
s->ts = timer_new_ns(QEMU_CLOCK_VIRTUAL, audio_timer, s);
if (!s->ts) {
hw_error("Could not create audio timer\n");
}

4
audio/noaudio.c
View File

@ -46,7 +46,7 @@ static int no_run_out (HWVoiceOut *hw, int live)
int64_t ticks;
int64_t bytes;
now = qemu_get_clock_ns (vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ticks = now - no->old_ticks;
bytes = muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ());
bytes = audio_MIN (bytes, INT_MAX);
@ -102,7 +102,7 @@ static int no_run_in (HWVoiceIn *hw)
int samples = 0;
if (dead) {
int64_t now = qemu_get_clock_ns (vm_clock);
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int64_t ticks = now - no->old_ticks;
int64_t bytes =
muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ());

4
audio/spiceaudio.c
View File

@ -81,7 +81,7 @@ static void spice_audio_fini (void *opaque)
static void rate_start (SpiceRateCtl *rate)
{
memset (rate, 0, sizeof (*rate));
rate->start_ticks = qemu_get_clock_ns (vm_clock);
rate->start_ticks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
static int rate_get_samples (struct audio_pcm_info *info, SpiceRateCtl *rate)
@ -91,7 +91,7 @@ static int rate_get_samples (struct audio_pcm_info *info, SpiceRateCtl *rate)
int64_t bytes;
int64_t samples;
now = qemu_get_clock_ns (vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ticks = now - rate->start_ticks;
bytes = muldiv64 (ticks, info->bytes_per_second, get_ticks_per_sec ());
samples = (bytes - rate->bytes_sent) >> info->shift;

2
audio/wavaudio.c
View File

@ -52,7 +52,7 @@ static int wav_run_out (HWVoiceOut *hw, int live)
int rpos, decr, samples;
uint8_t *dst;
struct st_sample *src;
int64_t now = qemu_get_clock_ns (vm_clock);
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int64_t ticks = now - wav->old_ticks;
int64_t bytes =
muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ());

16
backends/baum.c
View File

@ -314,9 +314,9 @@ static int baum_eat_packet(BaumDriverState *baum, const uint8_t *buf, int len)
return 0; \
if (*cur++ != ESC) { \
DPRINTF("Broken packet %#2x, tossing\n", req); \
if (qemu_timer_pending(baum->cellCount_timer)) { \
qemu_del_timer(baum->cellCount_timer); \
baum_cellCount_timer_cb(baum); \
if (timer_pending(baum->cellCount_timer)) { \
timer_del(baum->cellCount_timer); \
baum_cellCount_timer_cb(baum); \
} \
return (cur - 2 - buf); \
} \
@ -334,7 +334,7 @@ static int baum_eat_packet(BaumDriverState *baum, const uint8_t *buf, int len)
int i;
/* Allow 100ms to complete the DisplayData packet */
qemu_mod_timer(baum->cellCount_timer, qemu_get_clock_ns(vm_clock) +
timer_mod(baum->cellCount_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec() / 10);
for (i = 0; i < baum->x * baum->y ; i++) {
EAT(c);
@ -348,7 +348,7 @@ static int baum_eat_packet(BaumDriverState *baum, const uint8_t *buf, int len)
c = '?';
text[i] = c;
}
qemu_del_timer(baum->cellCount_timer);
timer_del(baum->cellCount_timer);
memset(zero, 0, sizeof(zero));
@ -553,7 +553,7 @@ static void baum_close(struct CharDriverState *chr)
{
BaumDriverState *baum = chr->opaque;
qemu_free_timer(baum->cellCount_timer);
timer_free(baum->cellCount_timer);
if (baum->brlapi) {
brlapi__closeConnection(baum->brlapi);
g_free(baum->brlapi);
@ -588,7 +588,7 @@ CharDriverState *chr_baum_init(void)
goto fail_handle;
}
baum->cellCount_timer = qemu_new_timer_ns(vm_clock, baum_cellCount_timer_cb, baum);
baum->cellCount_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, baum_cellCount_timer_cb, baum);
if (brlapi__getDisplaySize(handle, &baum->x, &baum->y) == -1) {
brlapi_perror("baum_init: brlapi_getDisplaySize");
@ -614,7 +614,7 @@ CharDriverState *chr_baum_init(void)
return chr;
fail:
qemu_free_timer(baum->cellCount_timer);
timer_free(baum->cellCount_timer);
brlapi__closeConnection(handle);
fail_handle:
g_free(handle);

46
block.c
View File

@ -130,8 +130,8 @@ void bdrv_io_limits_disable(BlockDriverState *bs)
do {} while (qemu_co_enter_next(&bs->throttled_reqs));
if (bs->block_timer) {
qemu_del_timer(bs->block_timer);
qemu_free_timer(bs->block_timer);
timer_del(bs->block_timer);
timer_free(bs->block_timer);
bs->block_timer = NULL;
}
@ -148,7 +148,7 @@ static void bdrv_block_timer(void *opaque)
void bdrv_io_limits_enable(BlockDriverState *bs)
{
bs->block_timer = qemu_new_timer_ns(vm_clock, bdrv_block_timer, bs);
bs->block_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, bdrv_block_timer, bs);
bs->io_limits_enabled = true;
}
@ -180,8 +180,8 @@ static void bdrv_io_limits_intercept(BlockDriverState *bs,
*/
while (bdrv_exceed_io_limits(bs, nb_sectors, is_write, &wait_time)) {
qemu_mod_timer(bs->block_timer,
wait_time + qemu_get_clock_ns(vm_clock));
timer_mod(bs->block_timer,
wait_time + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
qemu_co_queue_wait_insert_head(&bs->throttled_reqs);
}
@ -706,6 +706,7 @@ static int bdrv_open_common(BlockDriverState *bs, BlockDriverState *file,
bs->open_flags = flags;
bs->buffer_alignment = 512;
bs->zero_beyond_eof = true;
open_flags = bdrv_open_flags(bs, flags);
bs->read_only = !(open_flags & BDRV_O_RDWR);
@ -1402,6 +1403,7 @@ void bdrv_close(BlockDriverState *bs)
bs->valid_key = 0;
bs->sg = 0;
bs->growable = 0;
bs->zero_beyond_eof = false;
QDECREF(bs->options);
bs->options = NULL;
@ -2569,7 +2571,35 @@ static int coroutine_fn bdrv_co_do_readv(BlockDriverState *bs,
}
}
ret = drv->bdrv_co_readv(bs, sector_num, nb_sectors, qiov);
if (!(bs->zero_beyond_eof && bs->growable)) {
ret = drv->bdrv_co_readv(bs, sector_num, nb_sectors, qiov);
} else {
/* Read zeros after EOF of growable BDSes */
int64_t len, total_sectors, max_nb_sectors;
len = bdrv_getlength(bs);
if (len < 0) {
ret = len;
goto out;
}
total_sectors = len >> BDRV_SECTOR_BITS;
max_nb_sectors = MAX(0, total_sectors - sector_num);
if (max_nb_sectors > 0) {
ret = drv->bdrv_co_readv(bs, sector_num,
MIN(nb_sectors, max_nb_sectors), qiov);
} else {
ret = 0;
}
/* Reading beyond end of file is supposed to produce zeroes */
if (ret == 0 && total_sectors < sector_num + nb_sectors) {
uint64_t offset = MAX(0, total_sectors - sector_num);
uint64_t bytes = (sector_num + nb_sectors - offset) *
BDRV_SECTOR_SIZE;
qemu_iovec_memset(qiov, offset * BDRV_SECTOR_SIZE, 0, bytes);
}
}
out:
tracked_request_end(&req);
@ -3717,7 +3747,7 @@ static bool bdrv_exceed_io_limits(BlockDriverState *bs, int nb_sectors,
double elapsed_time;
int bps_ret, iops_ret;
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (now > bs->slice_end) {
bs->slice_start = now;
bs->slice_end = now + BLOCK_IO_SLICE_TIME;
@ -3737,7 +3767,7 @@ static bool bdrv_exceed_io_limits(BlockDriverState *bs, int nb_sectors,
*wait = max_wait;
}
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (bs->slice_end < now + max_wait) {
bs->slice_end = now + max_wait;
}

4
block/backup.c
View File

@ -272,9 +272,9 @@ static void coroutine_fn backup_run(void *opaque)
uint64_t delay_ns = ratelimit_calculate_delay(
&job->limit, job->sectors_read);
job->sectors_read = 0;
block_job_sleep_ns(&job->common, rt_clock, delay_ns);
block_job_sleep_ns(&job->common, QEMU_CLOCK_REALTIME, delay_ns);
} else {
block_job_sleep_ns(&job->common, rt_clock, 0);
block_job_sleep_ns(&job->common, QEMU_CLOCK_REALTIME, 0);
}
if (block_job_is_cancelled(&job->common)) {

2
block/commit.c
View File

@ -103,7 +103,7 @@ wait:
/* Note that even when no rate limit is applied we need to yield
* with no pending I/O here so that bdrv_drain_all() returns.
*/
block_job_sleep_ns(&s->common, rt_clock, delay_ns);
block_job_sleep_ns(&s->common, QEMU_CLOCK_REALTIME, delay_ns);
if (block_job_is_cancelled(&s->common)) {
break;
}

14
block/iscsi.c
View File

@ -960,7 +960,7 @@ static void iscsi_nop_timed_event(void *opaque)
return;
}
qemu_mod_timer(iscsilun->nop_timer, qemu_get_clock_ms(rt_clock) + NOP_INTERVAL);
timer_mod(iscsilun->nop_timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + NOP_INTERVAL);
iscsi_set_events(iscsilun);
}
#endif
@ -1173,8 +1173,8 @@ static int iscsi_open(BlockDriverState *bs, QDict *options, int flags)
#if defined(LIBISCSI_FEATURE_NOP_COUNTER)
/* Set up a timer for sending out iSCSI NOPs */
iscsilun->nop_timer = qemu_new_timer_ms(rt_clock, iscsi_nop_timed_event, iscsilun);
qemu_mod_timer(iscsilun->nop_timer, qemu_get_clock_ms(rt_clock) + NOP_INTERVAL);
iscsilun->nop_timer = timer_new_ms(QEMU_CLOCK_REALTIME, iscsi_nop_timed_event, iscsilun);
timer_mod(iscsilun->nop_timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + NOP_INTERVAL);
#endif
out:
@ -1204,8 +1204,8 @@ static void iscsi_close(BlockDriverState *bs)
struct iscsi_context *iscsi = iscsilun->iscsi;
if (iscsilun->nop_timer) {
qemu_del_timer(iscsilun->nop_timer);
qemu_free_timer(iscsilun->nop_timer);
timer_del(iscsilun->nop_timer);
timer_free(iscsilun->nop_timer);
}
qemu_aio_set_fd_handler(iscsi_get_fd(iscsi), NULL, NULL, NULL);
iscsi_destroy_context(iscsi);
@ -1267,8 +1267,8 @@ static int iscsi_create(const char *filename, QEMUOptionParameter *options)
goto out;
}
if (iscsilun->nop_timer) {
qemu_del_timer(iscsilun->nop_timer);
qemu_free_timer(iscsilun->nop_timer);
timer_del(iscsilun->nop_timer);
timer_free(iscsilun->nop_timer);
}
if (iscsilun->type != TYPE_DISK) {
ret = -ENODEV;

10
block/mirror.c
View File

@ -356,7 +356,7 @@ static void coroutine_fn mirror_run(void *opaque)
}
bdrv_dirty_iter_init(bs, &s->hbi);
last_pause_ns = qemu_get_clock_ns(rt_clock);
last_pause_ns = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
for (;;) {
uint64_t delay_ns;
int64_t cnt;
@ -374,7 +374,7 @@ static void coroutine_fn mirror_run(void *opaque)
* We do so every SLICE_TIME nanoseconds, or when there is an error,
* or when the source is clean, whichever comes first.
*/
if (qemu_get_clock_ns(rt_clock) - last_pause_ns < SLICE_TIME &&
if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - last_pause_ns < SLICE_TIME &&
s->common.iostatus == BLOCK_DEVICE_IO_STATUS_OK) {
if (s->in_flight == MAX_IN_FLIGHT || s->buf_free_count == 0 ||
(cnt == 0 && s->in_flight > 0)) {
@ -439,13 +439,13 @@ static void coroutine_fn mirror_run(void *opaque)
delay_ns = 0;
}
block_job_sleep_ns(&s->common, rt_clock, delay_ns);
block_job_sleep_ns(&s->common, QEMU_CLOCK_REALTIME, delay_ns);
if (block_job_is_cancelled(&s->common)) {
break;
}
} else if (!should_complete) {
delay_ns = (s->in_flight == 0 && cnt == 0 ? SLICE_TIME : 0);
block_job_sleep_ns(&s->common, rt_clock, delay_ns);
block_job_sleep_ns(&s->common, QEMU_CLOCK_REALTIME, delay_ns);
} else if (cnt == 0) {
/* The two disks are in sync. Exit and report successful
* completion.
@ -454,7 +454,7 @@ static void coroutine_fn mirror_run(void *opaque)
s->common.cancelled = false;
break;
}
last_pause_ns = qemu_get_clock_ns(rt_clock);
last_pause_ns = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
}
immediate_exit:

5
block/qcow2.c
View File

@ -1402,7 +1402,7 @@ static int qcow2_create(const char *filename, QEMUOptionParameter *options)
int flags = 0;
size_t cluster_size = DEFAULT_CLUSTER_SIZE;
int prealloc = 0;
int version = 2;
int version = 3;
/* Read out options */
while (options && options->name) {
@ -1722,12 +1722,15 @@ static int qcow2_load_vmstate(BlockDriverState *bs, uint8_t *buf,
{
BDRVQcowState *s = bs->opaque;
int growable = bs->growable;
bool zero_beyond_eof = bs->zero_beyond_eof;
int ret;
BLKDBG_EVENT(bs->file, BLKDBG_VMSTATE_LOAD);
bs->growable = 1;
bs->zero_beyond_eof = false;
ret = bdrv_pread(bs, qcow2_vm_state_offset(s) + pos, buf, size);
bs->growable = growable;
bs->zero_beyond_eof = zero_beyond_eof;
return ret;
}

10
block/qed.c
View File

@ -353,10 +353,10 @@ static void qed_start_need_check_timer(BDRVQEDState *s)
{
trace_qed_start_need_check_timer(s);
/* Use vm_clock so we don't alter the image file while suspended for
/* Use QEMU_CLOCK_VIRTUAL so we don't alter the image file while suspended for
* migration.
*/
qemu_mod_timer(s->need_check_timer, qemu_get_clock_ns(vm_clock) +
timer_mod(s->need_check_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec() * QED_NEED_CHECK_TIMEOUT);
}
@ -364,7 +364,7 @@ static void qed_start_need_check_timer(BDRVQEDState *s)
static void qed_cancel_need_check_timer(BDRVQEDState *s)
{
trace_qed_cancel_need_check_timer(s);
qemu_del_timer(s->need_check_timer);
timer_del(s->need_check_timer);
}
static void bdrv_qed_rebind(BlockDriverState *bs)
@ -494,7 +494,7 @@ static int bdrv_qed_open(BlockDriverState *bs, QDict *options, int flags)
}
}
s->need_check_timer = qemu_new_timer_ns(vm_clock,
s->need_check_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
qed_need_check_timer_cb, s);
out:
@ -518,7 +518,7 @@ static void bdrv_qed_close(BlockDriverState *bs)
BDRVQEDState *s = bs->opaque;
qed_cancel_need_check_timer(s);
qemu_free_timer(s->need_check_timer);
timer_free(s->need_check_timer);
/* Ensure writes reach stable storage */
bdrv_flush(bs->file);

2
block/stream.c
View File

@ -114,7 +114,7 @@ wait:
/* Note that even when no rate limit is applied we need to yield
* with no pending I/O here so that bdrv_drain_all() returns.
*/
block_job_sleep_ns(&s->common, rt_clock, delay_ns);
block_job_sleep_ns(&s->common, QEMU_CLOCK_REALTIME, delay_ns);
if (block_job_is_cancelled(&s->common)) {
break;
}

52
block/vmdk.c
View File

@ -401,6 +401,14 @@ static int vmdk_add_extent(BlockDriverState *bs,
error_report("invalid granularity, image may be corrupt");
return -EINVAL;
}
if (l1_size > 512 * 1024 * 1024) {
/* Although with big capacity and small l1_entry_sectors, we can get a
* big l1_size, we don't want unbounded value to allocate the table.
* Limit it to 512M, which is 16PB for default cluster and L2 table
* size */
error_report("L1 size too big");
return -EFBIG;
}
s->extents = g_realloc(s->extents,
(s->num_extents + 1) * sizeof(VmdkExtent));
@ -473,9 +481,9 @@ static int vmdk_init_tables(BlockDriverState *bs, VmdkExtent *extent)
return ret;
}
static int vmdk_open_vmdk3(BlockDriverState *bs,
BlockDriverState *file,
int flags)
static int vmdk_open_vmfs_sparse(BlockDriverState *bs,
BlockDriverState *file,
int flags)
{
int ret;
uint32_t magic;
@ -486,14 +494,14 @@ static int vmdk_open_vmdk3(BlockDriverState *bs,
if (ret < 0) {
return ret;
}
ret = vmdk_add_extent(bs,
bs->file, false,
le32_to_cpu(header.disk_sectors),
le32_to_cpu(header.l1dir_offset) << 9,
0, 1 << 6, 1 << 9,
le32_to_cpu(header.granularity),
&extent);
ret = vmdk_add_extent(bs, file, false,
le32_to_cpu(header.disk_sectors),
le32_to_cpu(header.l1dir_offset) << 9,
0,
le32_to_cpu(header.l1dir_size),
4096,
le32_to_cpu(header.granularity),
&extent);
if (ret < 0) {
return ret;
}
@ -598,14 +606,6 @@ static int vmdk_open_vmdk4(BlockDriverState *bs,
}
l1_size = (le64_to_cpu(header.capacity) + l1_entry_sectors - 1)
/ l1_entry_sectors;
if (l1_size > 512 * 1024 * 1024) {
/* although with big capacity and small l1_entry_sectors, we can get a
* big l1_size, we don't want unbounded value to allocate the table.
* Limit it to 512M, which is 16PB for default cluster and L2 table
* size */
error_report("L1 size too big");
return -EFBIG;
}
if (le32_to_cpu(header.flags) & VMDK4_FLAG_RGD) {
l1_backup_offset = le64_to_cpu(header.rgd_offset) << 9;
}
@ -674,7 +674,7 @@ static int vmdk_open_sparse(BlockDriverState *bs,
magic = be32_to_cpu(magic);
switch (magic) {
case VMDK3_MAGIC:
return vmdk_open_vmdk3(bs, file, flags);
return vmdk_open_vmfs_sparse(bs, file, flags);
break;
case VMDK4_MAGIC:
return vmdk_open_vmdk4(bs, file, flags);
@ -718,7 +718,8 @@ static int vmdk_parse_extents(const char *desc, BlockDriverState *bs,
}
if (sectors <= 0 ||
(strcmp(type, "FLAT") && strcmp(type, "SPARSE")) ||
(strcmp(type, "FLAT") && strcmp(type, "SPARSE") &&
strcmp(type, "VMFS") && strcmp(type, "VMFSSPARSE")) ||
(strcmp(access, "RW"))) {
goto next_line;
}
@ -731,7 +732,7 @@ static int vmdk_parse_extents(const char *desc, BlockDriverState *bs,
}
/* save to extents array */
if (!strcmp(type, "FLAT")) {
if (!strcmp(type, "FLAT") || !strcmp(type, "VMFS")) {
/* FLAT extent */
VmdkExtent *extent;
@ -741,8 +742,8 @@ static int vmdk_parse_extents(const char *desc, BlockDriverState *bs,
return ret;
}
extent->flat_start_offset = flat_offset << 9;
} else if (!strcmp(type, "SPARSE")) {
/* SPARSE extent */
} else if (!strcmp(type, "SPARSE") || !strcmp(type, "VMFSSPARSE")) {
/* SPARSE extent and VMFSSPARSE extent are both "COWD" sparse file*/
ret = vmdk_open_sparse(bs, extent_file, bs->open_flags);
if (ret) {
bdrv_delete(extent_file);
@ -789,6 +790,8 @@ static int vmdk_open_desc_file(BlockDriverState *bs, int flags,
goto exit;
}
if (strcmp(ct, "monolithicFlat") &&
strcmp(ct, "vmfs") &&
strcmp(ct, "vmfsSparse") &&
strcmp(ct, "twoGbMaxExtentSparse") &&
strcmp(ct, "twoGbMaxExtentFlat")) {
fprintf(stderr,
@ -1381,7 +1384,6 @@ static int coroutine_fn vmdk_co_write_zeroes(BlockDriverState *bs,
return ret;
}
static int vmdk_create_extent(const char *filename, int64_t filesize,
bool flat, bool compress, bool zeroed_grain)
{

10
block/win32-aio.c
View File

@ -105,13 +105,6 @@ static void win32_aio_completion_cb(EventNotifier *e)
}
}
static int win32_aio_flush_cb(EventNotifier *e)
{
QEMUWin32AIOState *s = container_of(e, QEMUWin32AIOState, e);
return (s->count > 0) ? 1 : 0;
}
static void win32_aio_cancel(BlockDriverAIOCB *blockacb)
{
QEMUWin32AIOCB *waiocb = (QEMUWin32AIOCB *)blockacb;
@ -201,8 +194,7 @@ QEMUWin32AIOState *win32_aio_init(void)
goto out_close_efd;
}
qemu_aio_set_event_notifier(&s->e, win32_aio_completion_cb,
win32_aio_flush_cb);
qemu_aio_set_event_notifier(&s->e, win32_aio_completion_cb);
return s;

8
blockdev.c
View File

@ -487,7 +487,11 @@ static DriveInfo *blockdev_init(QemuOpts *all_opts,
drv = bdrv_find_whitelisted_format(buf, ro);
if (!drv) {
error_report("'%s' invalid format", buf);
if (!ro && bdrv_find_whitelisted_format(buf, !ro)) {
error_report("'%s' can be only used as read-only device.", buf);
} else {
error_report("'%s' invalid format", buf);
}
return NULL;
}
}
@ -1295,7 +1299,7 @@ void qmp_block_set_io_throttle(const char *device, int64_t bps, int64_t bps_rd,
bdrv_io_limits_disable(bs);
} else {
if (bs->block_timer) {
qemu_mod_timer(bs->block_timer, qemu_get_clock_ns(vm_clock));
timer_mod(bs->block_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}
}
}

4
blockjob.c
View File

@ -187,7 +187,7 @@ int block_job_cancel_sync(BlockJob *job)
return (data.cancelled && data.ret == 0) ? -ECANCELED : data.ret;
}
void block_job_sleep_ns(BlockJob *job, QEMUClock *clock, int64_t ns)
void block_job_sleep_ns(BlockJob *job, QEMUClockType type, int64_t ns)
{
assert(job->busy);
@ -200,7 +200,7 @@ void block_job_sleep_ns(BlockJob *job, QEMUClock *clock, int64_t ns)
if (block_job_is_paused(job)) {
qemu_coroutine_yield();
} else {
co_sleep_ns(clock, ns);
co_sleep_ns(type, ns);
}
job->busy = true;
}

37
configure vendored
View File

@ -2818,6 +2818,37 @@ if compile_prog "" "" ; then
dup3=yes
fi
# check for ppoll support
ppoll=no
cat > $TMPC << EOF
#include <poll.h>
int main(void)
{
struct pollfd pfd = { .fd = 0, .events = 0, .revents = 0 };
ppoll(&pfd, 1, 0, 0);
return 0;
}
EOF
if compile_prog "" "" ; then
ppoll=yes
fi
# check for prctl(PR_SET_TIMERSLACK , ... ) support
prctl_pr_set_timerslack=no
cat > $TMPC << EOF
#include <sys/prctl.h>
int main(void)
{
prctl(PR_SET_TIMERSLACK, 1, 0, 0, 0);
return 0;
}
EOF
if compile_prog "" "" ; then
prctl_pr_set_timerslack=yes
fi
# check for epoll support
epoll=no
cat > $TMPC << EOF
@ -3814,6 +3845,12 @@ fi
if test "$dup3" = "yes" ; then
echo "CONFIG_DUP3=y" >> $config_host_mak
fi
if test "$ppoll" = "yes" ; then
echo "CONFIG_PPOLL=y" >> $config_host_mak
fi
if test "$prctl_pr_set_timerslack" = "yes" ; then
echo "CONFIG_PRCTL_PR_SET_TIMERSLACK=y" >> $config_host_mak
fi
if test "$epoll" = "yes" ; then
echo "CONFIG_EPOLL=y" >> $config_host_mak
fi

138
cpus.c
View File

@ -207,7 +207,7 @@ static void icount_adjust(void)
return;
}
cur_time = cpu_get_clock();
cur_icount = qemu_get_clock_ns(vm_clock);
cur_icount = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
delta = cur_icount - cur_time;
/* FIXME: This is a very crude algorithm, somewhat prone to oscillation. */
if (delta > 0
@ -228,15 +228,16 @@ static void icount_adjust(void)
static void icount_adjust_rt(void *opaque)
{
qemu_mod_timer(icount_rt_timer,
qemu_get_clock_ms(rt_clock) + 1000);
timer_mod(icount_rt_timer,
qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + 1000);
icount_adjust();
}
static void icount_adjust_vm(void *opaque)
{
qemu_mod_timer(icount_vm_timer,
qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 10);
timer_mod(icount_vm_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec() / 10);
icount_adjust();
}
@ -252,22 +253,22 @@ static void icount_warp_rt(void *opaque)
}
if (runstate_is_running()) {
int64_t clock = qemu_get_clock_ns(rt_clock);
int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
int64_t warp_delta = clock - vm_clock_warp_start;
if (use_icount == 1) {
qemu_icount_bias += warp_delta;
} else {
/*
* In adaptive mode, do not let the vm_clock run too
* In adaptive mode, do not let QEMU_CLOCK_VIRTUAL run too
* far ahead of real time.
*/
int64_t cur_time = cpu_get_clock();
int64_t cur_icount = qemu_get_clock_ns(vm_clock);
int64_t cur_icount = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int64_t delta = cur_time - cur_icount;
qemu_icount_bias += MIN(warp_delta, delta);
}
if (qemu_clock_expired(vm_clock)) {
qemu_notify_event();
if (qemu_clock_expired(QEMU_CLOCK_VIRTUAL)) {
qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
}
}
vm_clock_warp_start = -1;
@ -275,19 +276,19 @@ static void icount_warp_rt(void *opaque)
void qtest_clock_warp(int64_t dest)
{
int64_t clock = qemu_get_clock_ns(vm_clock);
int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
assert(qtest_enabled());
while (clock < dest) {
int64_t deadline = qemu_clock_deadline(vm_clock);
int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
int64_t warp = MIN(dest - clock, deadline);
qemu_icount_bias += warp;
qemu_run_timers(vm_clock);
clock = qemu_get_clock_ns(vm_clock);
qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
qemu_notify_event();
qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
}
void qemu_clock_warp(QEMUClock *clock)
void qemu_clock_warp(QEMUClockType type)
{
int64_t deadline;
@ -296,20 +297,20 @@ void qemu_clock_warp(QEMUClock *clock)
* applicable to other clocks. But a clock argument removes the
* need for if statements all over the place.
*/
if (clock != vm_clock || !use_icount) {
if (type != QEMU_CLOCK_VIRTUAL || !use_icount) {
return;
}
/*
* If the CPUs have been sleeping, advance the vm_clock timer now. This
* ensures that the deadline for the timer is computed correctly below.
* If the CPUs have been sleeping, advance QEMU_CLOCK_VIRTUAL timer now.
* This ensures that the deadline for the timer is computed correctly below.
* This also makes sure that the insn counter is synchronized before the
* CPU starts running, in case the CPU is woken by an event other than
* the earliest vm_clock timer.
* the earliest QEMU_CLOCK_VIRTUAL timer.
*/
icount_warp_rt(NULL);
if (!all_cpu_threads_idle() || !qemu_clock_has_timers(vm_clock)) {
qemu_del_timer(icount_warp_timer);
if (!all_cpu_threads_idle() || !qemu_clock_has_timers(QEMU_CLOCK_VIRTUAL)) {
timer_del(icount_warp_timer);
return;
}
@ -318,28 +319,40 @@ void qemu_clock_warp(QEMUClock *clock)
return;
}
vm_clock_warp_start = qemu_get_clock_ns(rt_clock);
deadline = qemu_clock_deadline(vm_clock);
vm_clock_warp_start = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
/* We want to use the earliest deadline from ALL vm_clocks */
deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
/* Maintain prior (possibly buggy) behaviour where if no deadline
* was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more than
* INT32_MAX nanoseconds ahead, we still use INT32_MAX
* nanoseconds.
*/
if ((deadline < 0) || (deadline > INT32_MAX)) {
deadline = INT32_MAX;
}
if (deadline > 0) {
/*
* Ensure the vm_clock proceeds even when the virtual CPU goes to
* Ensure QEMU_CLOCK_VIRTUAL proceeds even when the virtual CPU goes to
* sleep. Otherwise, the CPU might be waiting for a future timer
* interrupt to wake it up, but the interrupt never comes because
* the vCPU isn't running any insns and thus doesn't advance the
* vm_clock.
* QEMU_CLOCK_VIRTUAL.
*
* An extreme solution for this problem would be to never let VCPUs
* sleep in icount mode if there is a pending vm_clock timer; rather
* time could just advance to the next vm_clock event. Instead, we
* do stop VCPUs and only advance vm_clock after some "real" time,
* (related to the time left until the next event) has passed. This
* rt_clock timer will do this. This avoids that the warps are too
* visible externally---for example, you will not be sending network
* packets continuously instead of every 100ms.
* sleep in icount mode if there is a pending QEMU_CLOCK_VIRTUAL
* timer; rather time could just advance to the next QEMU_CLOCK_VIRTUAL
* event. Instead, we do stop VCPUs and only advance QEMU_CLOCK_VIRTUAL
* after some e"real" time, (related to the time left until the next
* event) has passed. The QEMU_CLOCK_REALTIME timer will do this.
* This avoids that the warps are visible externally; for example,
* you will not be sending network packets continuously instead of
* every 100ms.
*/
qemu_mod_timer(icount_warp_timer, vm_clock_warp_start + deadline);
} else {
qemu_notify_event();
timer_mod(icount_warp_timer, vm_clock_warp_start + deadline);
} else if (deadline == 0) {
qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
}
}
@ -363,7 +376,8 @@ void configure_icount(const char *option)
return;
}
icount_warp_timer = qemu_new_timer_ns(rt_clock, icount_warp_rt, NULL);
icount_warp_timer = timer_new_ns(QEMU_CLOCK_REALTIME,
icount_warp_rt, NULL);
if (strcmp(option, "auto") != 0) {
icount_time_shift = strtol(option, NULL, 0);
use_icount = 1;
@ -381,12 +395,15 @@ void configure_icount(const char *option)
the virtual time trigger catches emulated time passing too fast.
Realtime triggers occur even when idle, so use them less frequently
than VM triggers. */
icount_rt_timer = qemu_new_timer_ms(rt_clock, icount_adjust_rt, NULL);
qemu_mod_timer(icount_rt_timer,
qemu_get_clock_ms(rt_clock) + 1000);
icount_vm_timer = qemu_new_timer_ns(vm_clock, icount_adjust_vm, NULL);
qemu_mod_timer(icount_vm_timer,
qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 10);
icount_rt_timer = timer_new_ms(QEMU_CLOCK_REALTIME,
icount_adjust_rt, NULL);
timer_mod(icount_rt_timer,
qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + 1000);
icount_vm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
icount_adjust_vm, NULL);
timer_mod(icount_vm_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec() / 10);
}
/***********************************************************/
@ -735,7 +752,7 @@ static void qemu_tcg_wait_io_event(void)
while (all_cpu_threads_idle()) {
/* Start accounting real time to the virtual clock if the CPUs
are idle. */
qemu_clock_warp(vm_clock);
qemu_clock_warp(QEMU_CLOCK_VIRTUAL);
qemu_cond_wait(tcg_halt_cond, &qemu_global_mutex);
}
@ -866,8 +883,13 @@ static void *qemu_tcg_cpu_thread_fn(void *arg)
while (1) {
tcg_exec_all();
if (use_icount && qemu_clock_deadline(vm_clock) <= 0) {
qemu_notify_event();
if (use_icount) {
int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
if (deadline == 0) {
qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
}
}
qemu_tcg_wait_io_event();
}
@ -985,7 +1007,7 @@ void pause_all_vcpus(void)
{
CPUState *cpu = first_cpu;
qemu_clock_enable(vm_clock, false);
qemu_clock_enable(QEMU_CLOCK_VIRTUAL, false);
while (cpu) {
cpu->stop = true;
qemu_cpu_kick(cpu);
@ -1026,7 +1048,7 @@ void resume_all_vcpus(void)
{
CPUState *cpu = first_cpu;
qemu_clock_enable(vm_clock, true);
qemu_clock_enable(QEMU_CLOCK_VIRTUAL, true);
while (cpu) {
cpu_resume(cpu);
cpu = cpu->next_cpu;
@ -1145,11 +1167,23 @@ static int tcg_cpu_exec(CPUArchState *env)
#endif
if (use_icount) {
int64_t count;
int64_t deadline;
int decr;
qemu_icount -= (env->icount_decr.u16.low + env->icount_extra);
env->icount_decr.u16.low = 0;
env->icount_extra = 0;
count = qemu_icount_round(qemu_clock_deadline(vm_clock));
deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
/* Maintain prior (possibly buggy) behaviour where if no deadline
* was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more than
* INT32_MAX nanoseconds ahead, we still use INT32_MAX
* nanoseconds.
*/
if ((deadline < 0) || (deadline > INT32_MAX)) {
deadline = INT32_MAX;
}
count = qemu_icount_round(deadline);
qemu_icount += count;
decr = (count > 0xffff) ? 0xffff : count;
count -= decr;
@ -1175,8 +1209,8 @@ static void tcg_exec_all(void)
{
int r;
/* Account partial waits to the vm_clock. */
qemu_clock_warp(vm_clock);
/* Account partial waits to QEMU_CLOCK_VIRTUAL. */
qemu_clock_warp(QEMU_CLOCK_VIRTUAL);
if (next_cpu == NULL) {
next_cpu = first_cpu;
@ -1185,7 +1219,7 @@ static void tcg_exec_all(void)
CPUState *cpu = next_cpu;
CPUArchState *env = cpu->env_ptr;
qemu_clock_enable(vm_clock,
qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
(cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
if (cpu_can_run(cpu)) {

1
dma-helpers.c
View File

@ -11,6 +11,7 @@
#include "trace.h"
#include "qemu/range.h"
#include "qemu/thread.h"
#include "qemu/main-loop.h"
/* #define DEBUG_IOMMU */

8
hmp.c
View File

@ -1195,13 +1195,13 @@ static void hmp_migrate_status_cb(void *opaque)
monitor_flush(status->mon);
}
qemu_mod_timer(status->timer, qemu_get_clock_ms(rt_clock) + 1000);
timer_mod(status->timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + 1000);
} else {
if (status->is_block_migration) {
monitor_printf(status->mon, "\n");
}
monitor_resume(status->mon);
qemu_del_timer(status->timer);
timer_del(status->timer);
g_free(status);
}
@ -1235,9 +1235,9 @@ void hmp_migrate(Monitor *mon, const QDict *qdict)
status = g_malloc0(sizeof(*status));
status->mon = mon;
status->is_block_migration = blk || inc;
status->timer = qemu_new_timer_ms(rt_clock, hmp_migrate_status_cb,
status->timer = timer_new_ms(QEMU_CLOCK_REALTIME, hmp_migrate_status_cb,
status);
qemu_mod_timer(status->timer, qemu_get_clock_ms(rt_clock));
timer_mod(status->timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME));
}
}

8
hw/acpi/core.c
View File

@ -433,9 +433,9 @@ void acpi_pm_tmr_update(ACPIREGS *ar, bool enable)
if (enable) {
expire_time = muldiv64(ar->tmr.overflow_time, get_ticks_per_sec(),
PM_TIMER_FREQUENCY);
qemu_mod_timer(ar->tmr.timer, expire_time);
timer_mod(ar->tmr.timer, expire_time);
} else {
qemu_del_timer(ar->tmr.timer);
timer_del(ar->tmr.timer);
}
}
@ -481,7 +481,7 @@ void acpi_pm_tmr_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
MemoryRegion *parent)
{
ar->tmr.update_sci = update_sci;
ar->tmr.timer = qemu_new_timer_ns(vm_clock, acpi_pm_tmr_timer, ar);
ar->tmr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, acpi_pm_tmr_timer, ar);
memory_region_init_io(&ar->tmr.io, memory_region_owner(parent),
&acpi_pm_tmr_ops, ar, "acpi-tmr", 4);
memory_region_add_subregion(parent, 8, &ar->tmr.io);
@ -490,7 +490,7 @@ void acpi_pm_tmr_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
void acpi_pm_tmr_reset(ACPIREGS *ar)
{
ar->tmr.overflow_time = 0;
qemu_del_timer(ar->tmr.timer);
timer_del(ar->tmr.timer);
}
/* ACPI PM1aCNT */

2
hw/acpi/piix4.c
View File

@ -263,7 +263,7 @@ static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
return ret;
}
qemu_get_timer(f, s->ar.tmr.timer);
timer_get(f, s->ar.tmr.timer);
qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);

2
hw/alpha/typhoon.c
View File

@ -833,7 +833,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
AlphaCPU *cpu = cpus[i];
s->cchip.cpu[i] = cpu;
if (cpu != NULL) {
cpu->alarm_timer = qemu_new_timer_ns(vm_clock,
cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
typhoon_alarm_timer,
(void *)((uintptr_t)s + i));
}

52
hw/arm/omap1.c
View File

@ -99,7 +99,7 @@ struct omap_mpu_timer_s {
static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
{
uint64_t distance = qemu_get_clock_ns(vm_clock) - timer->time;
uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time;
if (timer->st && timer->enable && timer->rate)
return timer->val - muldiv64(distance >> (timer->ptv + 1),
@ -111,7 +111,7 @@ static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
{
timer->val = omap_timer_read(timer);
timer->time = qemu_get_clock_ns(vm_clock);
timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
@ -130,11 +130,11 @@ static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
* in a busy loop when it wants to sleep just a couple of CPU
* ticks. */
if (expires > (get_ticks_per_sec() >> 10) || timer->ar)
qemu_mod_timer(timer->timer, timer->time + expires);
timer_mod(timer->timer, timer->time + expires);
else
qemu_bh_schedule(timer->tick);
} else
qemu_del_timer(timer->timer);
timer_del(timer->timer);
}
static void omap_timer_fire(void *opaque)
@ -240,7 +240,7 @@ static const MemoryRegionOps omap_mpu_timer_ops = {
static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
{
qemu_del_timer(s->timer);
timer_del(s->timer);
s->enable = 0;
s->reset_val = 31337;
s->val = 0;
@ -259,7 +259,7 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
s->irq = irq;
s->clk = clk;
s->timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, s);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s);
s->tick = qemu_bh_new(omap_timer_fire, s);
omap_mpu_timer_reset(s);
omap_timer_clk_setup(s);
@ -363,7 +363,7 @@ static const MemoryRegionOps omap_wd_timer_ops = {
static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
{
qemu_del_timer(s->timer.timer);
timer_del(s->timer.timer);
if (!s->mode)
omap_clk_get(s->timer.clk);
s->mode = 1;
@ -388,7 +388,7 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
s->timer.irq = irq;
s->timer.clk = clk;
s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
omap_wd_timer_reset(s);
omap_timer_clk_setup(&s->timer);
@ -475,7 +475,7 @@ static const MemoryRegionOps omap_os_timer_ops = {
static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
{
qemu_del_timer(s->timer.timer);
timer_del(s->timer.timer);
s->timer.enable = 0;
s->timer.it_ena = 0;
s->timer.reset_val = 0x00ffffff;
@ -494,7 +494,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
s->timer.irq = irq;
s->timer.clk = clk;
s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
omap_os_timer_reset(s);
omap_timer_clk_setup(&s->timer);
@ -600,7 +600,7 @@ static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
case 0x10: /* GAUGING_CTRL */
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (value & 1)
s->ulpd_gauge_start = now;
@ -2881,7 +2881,7 @@ static void omap_rtc_tick(void *opaque)
if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
s->tick += s->comp_reg * 1000 / 32768;
qemu_mod_timer(s->clk, s->tick);
timer_mod(s->clk, s->tick);
}
static void omap_rtc_reset(struct omap_rtc_s *s)
@ -2894,7 +2894,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s)
s->pm_am = 0;
s->auto_comp = 0;
s->round = 0;
s->tick = qemu_get_clock_ms(rtc_clock);
s->tick = qemu_clock_get_ms(rtc_clock);
memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
s->alarm_tm.tm_mday = 0x01;
s->status = 1 << 7;
@ -2915,7 +2915,7 @@ static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
s->irq = timerirq;
s->alarm = alarmirq;
s->clk = qemu_new_timer_ms(rtc_clock, omap_rtc_tick, s);
s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s);
omap_rtc_reset(s);
@ -3009,7 +3009,7 @@ static void omap_mcbsp_source_tick(void *opaque)
s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
omap_mcbsp_rx_newdata(s);
qemu_mod_timer(s->source_timer, qemu_get_clock_ns(vm_clock) +
timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec());
}
@ -3025,7 +3025,7 @@ static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
{
qemu_del_timer(s->source_timer);
timer_del(s->source_timer);
}
static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
@ -3055,7 +3055,7 @@ static void omap_mcbsp_sink_tick(void *opaque)
s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
omap_mcbsp_tx_newdata(s);
qemu_mod_timer(s->sink_timer, qemu_get_clock_ns(vm_clock) +
timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec());
}
@ -3082,7 +3082,7 @@ static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
{
s->tx_req = 0;
omap_mcbsp_tx_done(s);
qemu_del_timer(s->sink_timer);
timer_del(s->sink_timer);
}
static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
@ -3432,8 +3432,8 @@ static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
s->rx_req = 0;
s->tx_rate = 0;
s->rx_rate = 0;
qemu_del_timer(s->source_timer);
qemu_del_timer(s->sink_timer);
timer_del(s->source_timer);
timer_del(s->sink_timer);
}
static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
@ -3448,8 +3448,8 @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
s->rxirq = rxirq;
s->txdrq = dma[0];
s->rxdrq = dma[1];
s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s);
s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s);
s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s);
omap_mcbsp_reset(s);
memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
@ -3503,9 +3503,9 @@ static void omap_lpg_tick(void *opaque)
struct omap_lpg_s *s = opaque;
if (s->cycle)
qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->period - s->on);
timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on);
else
qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->on);
timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on);
s->cycle = !s->cycle;
printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
@ -3527,7 +3527,7 @@ static void omap_lpg_update(struct omap_lpg_s *s)
per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
}
qemu_del_timer(s->tm);
timer_del(s->tm);
if (on == period && s->on < s->period)
printf("%s: LED is on\n", __FUNCTION__);
else if (on == 0 && s->on)
@ -3623,7 +3623,7 @@ static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
struct omap_lpg_s *s = (struct omap_lpg_s *)
g_malloc0(sizeof(struct omap_lpg_s));
s->tm = qemu_new_timer_ms(vm_clock, omap_lpg_tick, s);
s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s);
omap_lpg_reset(s);

59
hw/arm/pxa2xx.c
View File

@ -335,7 +335,7 @@ static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
if (s->pmnc & 1) {
*value = qemu_get_clock_ns(vm_clock);
*value = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
} else {
*value = 0;
}
@ -842,7 +842,7 @@ static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
{
int64_t rt = qemu_get_clock_ms(rtc_clock);
int64_t rt = qemu_clock_get_ms(rtc_clock);
s->last_rcnr += ((rt - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
s->last_rdcr += ((rt - s->last_hz) << 15) /
@ -852,7 +852,7 @@ static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
{
int64_t rt = qemu_get_clock_ms(rtc_clock);
int64_t rt = qemu_clock_get_ms(rtc_clock);
if (s->rtsr & (1 << 12))
s->last_swcr += (rt - s->last_sw) / 10;
s->last_sw = rt;
@ -860,7 +860,7 @@ static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
{
int64_t rt = qemu_get_clock_ms(rtc_clock);
int64_t rt = qemu_clock_get_ms(rtc_clock);
if (s->rtsr & (1 << 15))
s->last_swcr += rt - s->last_pi;
s->last_pi = rt;
@ -870,43 +870,43 @@ static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
uint32_t rtsr)
{
if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
qemu_mod_timer(s->rtc_hz, s->last_hz +
timer_mod(s->rtc_hz, s->last_hz +
(((s->rtar - s->last_rcnr) * 1000 *
((s->rttr & 0xffff) + 1)) >> 15));
else
qemu_del_timer(s->rtc_hz);
timer_del(s->rtc_hz);
if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
qemu_mod_timer(s->rtc_rdal1, s->last_hz +
timer_mod(s->rtc_rdal1, s->last_hz +
(((s->rdar1 - s->last_rdcr) * 1000 *
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
else
qemu_del_timer(s->rtc_rdal1);
timer_del(s->rtc_rdal1);
if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
qemu_mod_timer(s->rtc_rdal2, s->last_hz +
timer_mod(s->rtc_rdal2, s->last_hz +
(((s->rdar2 - s->last_rdcr) * 1000 *
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
else
qemu_del_timer(s->rtc_rdal2);
timer_del(s->rtc_rdal2);
if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
qemu_mod_timer(s->rtc_swal1, s->last_sw +
timer_mod(s->rtc_swal1, s->last_sw +
(s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
else
qemu_del_timer(s->rtc_swal1);
timer_del(s->rtc_swal1);
if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
qemu_mod_timer(s->rtc_swal2, s->last_sw +
timer_mod(s->rtc_swal2, s->last_sw +
(s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
else
qemu_del_timer(s->rtc_swal2);
timer_del(s->rtc_swal2);
if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
qemu_mod_timer(s->rtc_pi, s->last_pi +
timer_mod(s->rtc_pi, s->last_pi +
(s->piar & 0xffff) - s->last_rtcpicr);
else
qemu_del_timer(s->rtc_pi);
timer_del(s->rtc_pi);
}
static inline void pxa2xx_rtc_hz_tick(void *opaque)
@ -986,16 +986,19 @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
case PIAR:
return s->piar;
case RCNR:
return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
return s->last_rcnr +
((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
case RDCR:
return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
return s->last_rdcr +
((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
case RYCR:
return s->last_rycr;
case SWCR:
if (s->rtsr & (1 << 12))
return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10;
return s->last_swcr +
(qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;
else
return s->last_swcr;
default:
@ -1135,14 +1138,14 @@ static int pxa2xx_rtc_init(SysBusDevice *dev)
s->last_swcr = (tm.tm_hour << 19) |
(tm.tm_min << 13) | (tm.tm_sec << 7);
s->last_rtcpicr = 0;
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock);
s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);
s->rtc_hz = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
s->rtc_pi = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
sysbus_init_irq(dev, &s->rtc_irq);

6
hw/arm/spitz.c
View File

@ -393,7 +393,7 @@ static void spitz_keyboard_tick(void *opaque)
s->fifopos = 0;
}
qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock) +
timer_mod(s->kbdtimer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec() / 32);
}
@ -485,7 +485,7 @@ static void spitz_keyboard_register(PXA2xxState *cpu)
qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i],
qdev_get_gpio_in(dev, i));
qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock));
timer_mod(s->kbdtimer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
}
@ -505,7 +505,7 @@ static int spitz_keyboard_init(SysBusDevice *sbd)
spitz_keyboard_pre_map(s);
s->kbdtimer = qemu_new_timer_ns(vm_clock, spitz_keyboard_tick, s);
s->kbdtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, spitz_keyboard_tick, s);
qdev_init_gpio_in(dev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
qdev_init_gpio_out(dev, s->sense, SPITZ_KEY_SENSE_NUM);

10
hw/arm/stellaris.c
View File

@ -78,14 +78,14 @@ static void gptm_update_irq(gptm_state *s)
static void gptm_stop(gptm_state *s, int n)
{
qemu_del_timer(s->timer[n]);
timer_del(s->timer[n]);
}
static void gptm_reload(gptm_state *s, int n, int reset)
{
int64_t tick;
if (reset)
tick = qemu_get_clock_ns(vm_clock);
tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
else
tick = s->tick[n];
@ -103,7 +103,7 @@ static void gptm_reload(gptm_state *s, int n, int reset)
hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
}
s->tick[n] = tick;
qemu_mod_timer(s->timer[n], tick);
timer_mod(s->timer[n], tick);
}
static void gptm_tick(void *opaque)
@ -318,8 +318,8 @@ static int stellaris_gptm_init(SysBusDevice *sbd)
sysbus_init_mmio(sbd, &s->iomem);
s->opaque[0] = s->opaque[1] = s;
s->timer[0] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[0]);
s->timer[1] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[1]);
s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
vmstate_register(dev, -1, &vmstate_stellaris_gptm, s);
return 0;
}

34
hw/arm/strongarm.c
View File

@ -269,7 +269,7 @@ static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
{
int64_t rt = qemu_get_clock_ms(rtc_clock);
int64_t rt = qemu_clock_get_ms(rtc_clock);
s->last_rcnr += ((rt - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
s->last_hz = rt;
@ -278,17 +278,17 @@ static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
{
if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
qemu_mod_timer(s->rtc_hz, s->last_hz + 1000);
timer_mod(s->rtc_hz, s->last_hz + 1000);
} else {
qemu_del_timer(s->rtc_hz);
timer_del(s->rtc_hz);
}
if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
qemu_mod_timer(s->rtc_alarm, s->last_hz +
timer_mod(s->rtc_alarm, s->last_hz +
(((s->rtar - s->last_rcnr) * 1000 *
((s->rttr & 0xffff) + 1)) >> 15));
} else {
qemu_del_timer(s->rtc_alarm);
timer_del(s->rtc_alarm);
}
}
@ -322,7 +322,7 @@ static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
return s->rtar;
case RCNR:
return s->last_rcnr +
((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
default:
printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
@ -388,10 +388,10 @@ static int strongarm_rtc_init(SysBusDevice *dev)
qemu_get_timedate(&tm, 0);
s->last_rcnr = (uint32_t) mktimegm(&tm);
s->last_hz = qemu_get_clock_ms(rtc_clock);
s->last_hz = qemu_clock_get_ms(rtc_clock);
s->rtc_alarm = qemu_new_timer_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
s->rtc_hz = qemu_new_timer_ms(rtc_clock, strongarm_rtc_hz_tick, s);
s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s);
sysbus_init_irq(dev, &s->rtc_irq);
sysbus_init_irq(dev, &s->rtc_hz_irq);
@ -1085,8 +1085,8 @@ static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
}
/* call the timeout receive callback in 3 char transmit time */
qemu_mod_timer(s->rx_timeout_timer,
qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
timer_mod(s->rx_timeout_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
strongarm_uart_update_status(s);
strongarm_uart_update_int_status(s);
@ -1107,7 +1107,7 @@ static void strongarm_uart_event(void *opaque, int event)
static void strongarm_uart_tx(void *opaque)
{
StrongARMUARTState *s = opaque;
uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (s->utcr3 & UTCR3_LBM) /* loopback */ {
strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
@ -1118,7 +1118,7 @@ static void strongarm_uart_tx(void *opaque)
s->tx_start = (s->tx_start + 1) % 8;
s->tx_len--;
if (s->tx_len) {
qemu_mod_timer(s->tx_timer, new_xmit_ts + s->char_transmit_time);
timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time);
}
strongarm_uart_update_status(s);
strongarm_uart_update_int_status(s);
@ -1237,8 +1237,8 @@ static int strongarm_uart_init(SysBusDevice *dev)
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s);
s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s);
s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);
s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
if (s->chr) {
qemu_chr_add_handlers(s->chr,
@ -1282,8 +1282,8 @@ static int strongarm_uart_post_load(void *opaque, int version_id)
/* restart rx timeout timer */
if (s->rx_len) {
qemu_mod_timer(s->rx_timeout_timer,
qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
timer_mod(s->rx_timeout_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
}
return 0;

2
hw/audio/adlib.c
View File

@ -173,7 +173,7 @@ static void timer_handler (int c, double interval_Sec)
s->ticking[n] = 1;
#ifdef DEBUG
interval = get_ticks_per_sec () * interval_Sec;
exp = qemu_get_clock_ns (vm_clock) + interval;
exp = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + interval;
s->exp[n] = exp;
#endif

4
hw/audio/intel-hda.c
View File

@ -526,7 +526,7 @@ static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
{
int64_t ns;
ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns;
ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
}
@ -1111,7 +1111,7 @@ static void intel_hda_reset(DeviceState *dev)
HDACodecDevice *cdev;
intel_hda_regs_reset(d);
d->wall_base_ns = qemu_get_clock_ns(vm_clock);
d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
/* reset codecs */
QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {

6
hw/audio/sb16.c
View File

@ -768,9 +768,9 @@ static void complete (SB16State *s)
}
else {
if (s->aux_ts) {
qemu_mod_timer (
timer_mod (
s->aux_ts,
qemu_get_clock_ns (vm_clock) + ticks
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ticks
);
}
}
@ -1378,7 +1378,7 @@ static void sb16_realizefn (DeviceState *dev, Error **errp)
s->csp_regs[9] = 0xf8;
reset_mixer (s);
s->aux_ts = qemu_new_timer_ns (vm_clock, aux_timer, s);
s->aux_ts = timer_new_ns(QEMU_CLOCK_VIRTUAL, aux_timer, s);
if (!s->aux_ts) {
dolog ("warning: Could not create auxiliary timer\n");
}

6
hw/block/fdc.c
View File

@ -1647,8 +1647,8 @@ static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
FDrive *cur_drv = get_cur_drv(fdctrl);
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
qemu_mod_timer(fdctrl->result_timer,
qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
timer_mod(fdctrl->result_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50));
}
static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
@ -2108,7 +2108,7 @@ static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
FLOPPY_DPRINTF("init controller\n");
fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
fdctrl->fifo_size = 512;
fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
fdctrl_result_timer, fdctrl);
fdctrl->version = 0x90; /* Intel 82078 controller */

20
hw/block/nvme.c
View File

@ -187,7 +187,7 @@ static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
assert(cq->cqid == req->sq->cqid);
QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
qemu_mod_timer(cq->timer, qemu_get_clock_ns(vm_clock) + 500);
timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
}
static void nvme_rw_cb(void *opaque, int ret)
@ -264,8 +264,8 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
{
n->sq[sq->sqid] = NULL;
qemu_del_timer(sq->timer);
qemu_free_timer(sq->timer);
timer_del(sq->timer);
timer_free(sq->timer);
g_free(sq->io_req);
if (sq->sqid) {
g_free(sq);
@ -327,7 +327,7 @@ static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
sq->io_req[i].sq = sq;
QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
}
sq->timer = qemu_new_timer_ns(vm_clock, nvme_process_sq, sq);
sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
assert(n->cq[cqid]);
cq = n->cq[cqid];
@ -369,8 +369,8 @@ static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *cmd)
static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
{
n->cq[cq->cqid] = NULL;
qemu_del_timer(cq->timer);
qemu_free_timer(cq->timer);
timer_del(cq->timer);
timer_free(cq->timer);
msix_vector_unuse(&n->parent_obj, cq->vector);
if (cq->cqid) {
g_free(cq);
@ -410,7 +410,7 @@ static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
QTAILQ_INIT(&cq->sq_list);
msix_vector_use(&n->parent_obj, cq->vector);
n->cq[cqid] = cq;
cq->timer = qemu_new_timer_ns(vm_clock, nvme_post_cqes, cq);
cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq);
}
static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd)
@ -691,9 +691,9 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
if (start_sqs) {
NvmeSQueue *sq;
QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
qemu_mod_timer(sq->timer, qemu_get_clock_ns(vm_clock) + 500);
timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
}
qemu_mod_timer(cq->timer, qemu_get_clock_ns(vm_clock) + 500);
timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
}
if (cq->tail != cq->head) {
@ -714,7 +714,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
}
sq->tail = new_tail;
qemu_mod_timer(sq->timer, qemu_get_clock_ns(vm_clock) + 500);
timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
}
}

2
hw/block/pflash_cfi01.c
View File

@ -613,7 +613,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
pfl->ro = 0;
}
pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);
pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
pfl->wcycle = 0;
pfl->cmd = 0;
pfl->status = 0;

10
hw/block/pflash_cfi02.c
View File

@ -430,8 +430,8 @@ static void pflash_write (pflash_t *pfl, hwaddr offset,
}
pfl->status = 0x00;
/* Let's wait 5 seconds before chip erase is done */
qemu_mod_timer(pfl->timer,
qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 5));
timer_mod(pfl->timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() * 5));
break;
case 0x30:
/* Sector erase */
@ -445,8 +445,8 @@ static void pflash_write (pflash_t *pfl, hwaddr offset,
}
pfl->status = 0x00;
/* Let's wait 1/2 second before sector erase is done */
qemu_mod_timer(pfl->timer,
qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 2));
timer_mod(pfl->timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 2));
break;
default:
DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
@ -633,7 +633,7 @@ static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
pfl->ro = 0;
}
pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);
pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
pfl->wcycle = 0;
pfl->cmd = 0;
pfl->status = 0;

4
hw/bt/hci-csr.c
View File

@ -87,7 +87,7 @@ static inline void csrhci_fifo_wake(struct csrhci_s *s)
}
if (s->out_len)
qemu_mod_timer(s->out_tm, qemu_get_clock_ns(vm_clock) + s->baud_delay);
timer_mod(s->out_tm, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->baud_delay);
}
#define csrhci_out_packetz(s, len) memset(csrhci_out_packet(s, len), 0, len)
@ -446,7 +446,7 @@ CharDriverState *uart_hci_init(qemu_irq wakeup)
s->hci->evt_recv = csrhci_out_hci_packet_event;
s->hci->acl_recv = csrhci_out_hci_packet_acl;
s->out_tm = qemu_new_timer_ns(vm_clock, csrhci_out_tick, s);
s->out_tm = timer_new_ns(QEMU_CLOCK_VIRTUAL, csrhci_out_tick, s);
s->pins = qemu_allocate_irqs(csrhci_pins, s, __csrhci_pins);
csrhci_reset(s);

38
hw/bt/hci.c
View File

@ -576,7 +576,7 @@ static void bt_hci_inquiry_result(struct bt_hci_s *hci,
static void bt_hci_mod_timer_1280ms(QEMUTimer *timer, int period)
{
qemu_mod_timer(timer, qemu_get_clock_ns(vm_clock) +
timer_mod(timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
muldiv64(period << 7, get_ticks_per_sec(), 100));
}
@ -657,7 +657,7 @@ static void bt_hci_lmp_link_establish(struct bt_hci_s *hci,
if (master) {
link->acl_mode = acl_active;
hci->lm.handle[hci->lm.last_handle].acl_mode_timer =
qemu_new_timer_ns(vm_clock, bt_hci_mode_tick, link);
timer_new_ns(QEMU_CLOCK_VIRTUAL, bt_hci_mode_tick, link);
}
}
@ -667,8 +667,8 @@ static void bt_hci_lmp_link_teardown(struct bt_hci_s *hci, uint16_t handle)
hci->lm.handle[handle].link = NULL;
if (bt_hci_role_master(hci, handle)) {
qemu_del_timer(hci->lm.handle[handle].acl_mode_timer);
qemu_free_timer(hci->lm.handle[handle].acl_mode_timer);
timer_del(hci->lm.handle[handle].acl_mode_timer);
timer_free(hci->lm.handle[handle].acl_mode_timer);
}
}
@ -1080,7 +1080,7 @@ static int bt_hci_mode_change(struct bt_hci_s *hci, uint16_t handle,
bt_hci_event_status(hci, HCI_SUCCESS);
qemu_mod_timer(link->acl_mode_timer, qemu_get_clock_ns(vm_clock) +
timer_mod(link->acl_mode_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
muldiv64(interval * 625, get_ticks_per_sec(), 1000000));
bt_hci_lmp_mode_change_master(hci, link->link, mode, interval);
@ -1103,7 +1103,7 @@ static int bt_hci_mode_cancel(struct bt_hci_s *hci, uint16_t handle, int mode)
bt_hci_event_status(hci, HCI_SUCCESS);
qemu_del_timer(link->acl_mode_timer);
timer_del(link->acl_mode_timer);
bt_hci_lmp_mode_change_master(hci, link->link, acl_active, 0);
return 0;
@ -1146,10 +1146,10 @@ static void bt_hci_reset(struct bt_hci_s *hci)
hci->psb_handle = 0x000;
hci->asb_handle = 0x000;
/* XXX: qemu_del_timer(sl->acl_mode_timer); for all links */
qemu_del_timer(hci->lm.inquiry_done);
qemu_del_timer(hci->lm.inquiry_next);
qemu_del_timer(hci->conn_accept_timer);
/* XXX: timer_del(sl->acl_mode_timer); for all links */
timer_del(hci->lm.inquiry_done);
timer_del(hci->lm.inquiry_next);
timer_del(hci->conn_accept_timer);
}
static void bt_hci_read_local_version_rp(struct bt_hci_s *hci)
@ -1514,7 +1514,7 @@ static void bt_submit_hci(struct HCIInfo *info,
}
hci->lm.inquire = 0;
qemu_del_timer(hci->lm.inquiry_done);
timer_del(hci->lm.inquiry_done);
bt_hci_event_complete_status(hci, HCI_SUCCESS);
break;
@ -1552,8 +1552,8 @@ static void bt_submit_hci(struct HCIInfo *info,
break;
}
hci->lm.inquire = 0;
qemu_del_timer(hci->lm.inquiry_done);
qemu_del_timer(hci->lm.inquiry_next);
timer_del(hci->lm.inquiry_done);
timer_del(hci->lm.inquiry_next);
bt_hci_event_complete_status(hci, HCI_SUCCESS);
break;
@ -2141,10 +2141,10 @@ struct HCIInfo *bt_new_hci(struct bt_scatternet_s *net)
{
struct bt_hci_s *s = g_malloc0(sizeof(struct bt_hci_s));
s->lm.inquiry_done = qemu_new_timer_ns(vm_clock, bt_hci_inquiry_done, s);
s->lm.inquiry_next = qemu_new_timer_ns(vm_clock, bt_hci_inquiry_next, s);
s->lm.inquiry_done = timer_new_ns(QEMU_CLOCK_VIRTUAL, bt_hci_inquiry_done, s);
s->lm.inquiry_next = timer_new_ns(QEMU_CLOCK_VIRTUAL, bt_hci_inquiry_next, s);
s->conn_accept_timer =
qemu_new_timer_ns(vm_clock, bt_hci_conn_accept_timeout, s);
timer_new_ns(QEMU_CLOCK_VIRTUAL, bt_hci_conn_accept_timeout, s);
s->evt_packet = bt_hci_evt_packet;
s->evt_submit = bt_hci_evt_submit;
@ -2209,9 +2209,9 @@ static void bt_hci_done(struct HCIInfo *info)
* s->device.lmp_connection_complete to free the remaining bits once
* hci->lm.awaiting_bdaddr[] is empty. */
qemu_free_timer(hci->lm.inquiry_done);
qemu_free_timer(hci->lm.inquiry_next);
qemu_free_timer(hci->conn_accept_timer);
timer_free(hci->lm.inquiry_done);
timer_free(hci->lm.inquiry_next);
timer_free(hci->conn_accept_timer);
g_free(hci);
}

8
hw/bt/l2cap.c
View File

@ -166,9 +166,9 @@ static void l2cap_retransmission_timer_update(struct l2cap_chan_s *ch)
{
#if 0
if (ch->mode != L2CAP_MODE_BASIC && ch->rexmit)
qemu_mod_timer(ch->retransmission_timer);
timer_mod(ch->retransmission_timer);
else
qemu_del_timer(ch->retransmission_timer);
timer_del(ch->retransmission_timer);
#endif
}
@ -176,9 +176,9 @@ static void l2cap_monitor_timer_update(struct l2cap_chan_s *ch)
{
#if 0
if (ch->mode != L2CAP_MODE_BASIC && !ch->rexmit)
qemu_mod_timer(ch->monitor_timer);
timer_mod(ch->monitor_timer);
else
qemu_del_timer(ch->monitor_timer);
timer_del(ch->monitor_timer);
#endif
}

12
hw/char/cadence_uart.c
View File

@ -141,9 +141,9 @@ static void fifo_trigger_update(void *opaque)
static void uart_tx_redo(UartState *s)
{
uint64_t new_tx_time = qemu_get_clock_ns(vm_clock);
uint64_t new_tx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
qemu_mod_timer(s->tx_time_handle, new_tx_time + s->char_tx_time);
timer_mod(s->tx_time_handle, new_tx_time + s->char_tx_time);
s->r[R_SR] |= UART_SR_INTR_TEMPTY;
@ -265,7 +265,7 @@ static void uart_ctrl_update(UartState *s)
static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
{
UartState *s = (UartState *)opaque;
uint64_t new_rx_time = qemu_get_clock_ns(vm_clock);
uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int i;
if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
@ -291,7 +291,7 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
s->r[R_SR] |= UART_SR_INTR_RTRIG;
}
}
qemu_mod_timer(s->fifo_trigger_handle, new_rx_time +
timer_mod(s->fifo_trigger_handle, new_rx_time +
(s->char_tx_time * 4));
}
uart_update_status(s);
@ -452,10 +452,10 @@ static int cadence_uart_init(SysBusDevice *dev)
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->fifo_trigger_handle = qemu_new_timer_ns(vm_clock,
s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
(QEMUTimerCB *)fifo_trigger_update, s);
s->tx_time_handle = qemu_new_timer_ns(vm_clock,
s->tx_time_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
(QEMUTimerCB *)uart_tx_write, s);
s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;

22
hw/char/serial.c
View File

@ -189,7 +189,7 @@ static void serial_update_msl(SerialState *s)
uint8_t omsr;
int flags;
qemu_del_timer(s->modem_status_poll);
timer_del(s->modem_status_poll);
if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
s->poll_msl = -1;
@ -216,7 +216,7 @@ static void serial_update_msl(SerialState *s)
We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
if (s->poll_msl)
qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 100);
}
static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
@ -253,7 +253,7 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
s->tsr_retry = 0;
}
s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (s->lsr & UART_LSR_THRE) {
s->lsr |= UART_LSR_TEMT;
@ -307,7 +307,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
s->poll_msl = 1;
serial_update_msl(s);
} else {
qemu_del_timer(s->modem_status_poll);
timer_del(s->modem_status_poll);
s->poll_msl = 0;
}
}
@ -330,7 +330,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
/* FIFO clear */
if (val & UART_FCR_RFR) {
qemu_del_timer(s->fifo_timeout_timer);
timer_del(s->fifo_timeout_timer);
s->timeout_ipending=0;
fifo8_reset(&s->recv_fifo);
}
@ -398,7 +398,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
/* Update the modem status after a one-character-send wait-time, since there may be a response
from the device/computer at the other end of the serial line */
qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
}
}
break;
@ -430,7 +430,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
if (s->recv_fifo.num == 0) {
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
} else {
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
}
s->timeout_ipending = 0;
} else {
@ -557,7 +557,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size)
}
s->lsr |= UART_LSR_DR;
/* call the timeout receive callback in 4 char transmit time */
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
} else {
if (s->lsr & UART_LSR_DR)
s->lsr |= UART_LSR_OE;
@ -636,7 +636,7 @@ static void serial_reset(void *opaque)
fifo8_reset(&s->recv_fifo);
fifo8_reset(&s->xmit_fifo);
s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->thr_ipending = 0;
s->last_break_enable = 0;
@ -650,9 +650,9 @@ void serial_realize_core(SerialState *s, Error **errp)
return;
}
s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
qemu_register_reset(serial_reset, s);
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,

10
hw/char/virtio-serial-bus.c
View File

@ -603,7 +603,7 @@ static void virtio_serial_post_load_timer_cb(void *opaque)
}
}
g_free(s->post_load->connected);
qemu_free_timer(s->post_load->timer);
timer_free(s->post_load->timer);
g_free(s->post_load);
s->post_load = NULL;
}
@ -618,7 +618,7 @@ static int fetch_active_ports_list(QEMUFile *f, int version_id,
s->post_load->connected =
g_malloc0(sizeof(*s->post_load->connected) * nr_active_ports);
s->post_load->timer = qemu_new_timer_ns(vm_clock,
s->post_load->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
virtio_serial_post_load_timer_cb,
s);
@ -660,7 +660,7 @@ static int fetch_active_ports_list(QEMUFile *f, int version_id,
}
}
}
qemu_mod_timer(s->post_load->timer, 1);
timer_mod(s->post_load->timer, 1);
return 0;
}
@ -999,8 +999,8 @@ static int virtio_serial_device_exit(DeviceState *dev)
g_free(vser->ports_map);
if (vser->post_load) {
g_free(vser->post_load->connected);
qemu_del_timer(vser->post_load->timer);
qemu_free_timer(vser->post_load->timer);
timer_del(vser->post_load->timer);
timer_free(vser->post_load->timer);
g_free(vser->post_load);
}
virtio_cleanup(vdev);

18
hw/core/ptimer.c
View File

@ -48,7 +48,7 @@ static void ptimer_reload(ptimer_state *s)
if (s->period_frac) {
s->next_event += ((int64_t)s->period_frac * s->delta) >> 32;
}
qemu_mod_timer(s->timer, s->next_event);
timer_mod(s->timer, s->next_event);
}
static void ptimer_tick(void *opaque)
@ -69,7 +69,7 @@ uint64_t ptimer_get_count(ptimer_state *s)
uint64_t counter;
if (s->enabled) {
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
/* Figure out the current counter value. */
if (now - s->next_event > 0
|| s->period == 0) {
@ -123,7 +123,7 @@ void ptimer_set_count(ptimer_state *s, uint64_t count)
{
s->delta = count;
if (s->enabled) {
s->next_event = qemu_get_clock_ns(vm_clock);
s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ptimer_reload(s);
}
}
@ -138,7 +138,7 @@ void ptimer_run(ptimer_state *s, int oneshot)
return;
}
s->enabled = oneshot ? 2 : 1;
s->next_event = qemu_get_clock_ns(vm_clock);
s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ptimer_reload(s);
}
@ -150,7 +150,7 @@ void ptimer_stop(ptimer_state *s)
return;
s->delta = ptimer_get_count(s);
qemu_del_timer(s->timer);
timer_del(s->timer);
s->enabled = 0;
}
@ -160,7 +160,7 @@ void ptimer_set_period(ptimer_state *s, int64_t period)
s->period = period;
s->period_frac = 0;
if (s->enabled) {
s->next_event = qemu_get_clock_ns(vm_clock);
s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ptimer_reload(s);
}
}
@ -171,7 +171,7 @@ void ptimer_set_freq(ptimer_state *s, uint32_t freq)
s->period = 1000000000ll / freq;
s->period_frac = (1000000000ll << 32) / freq;
if (s->enabled) {
s->next_event = qemu_get_clock_ns(vm_clock);
s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ptimer_reload(s);
}
}
@ -197,7 +197,7 @@ void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload)
if (reload)
s->delta = limit;
if (s->enabled && reload) {
s->next_event = qemu_get_clock_ns(vm_clock);
s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ptimer_reload(s);
}
}
@ -226,6 +226,6 @@ ptimer_state *ptimer_init(QEMUBH *bh)
s = (ptimer_state *)g_malloc0(sizeof(ptimer_state));
s->bh = bh;
s->timer = qemu_new_timer_ns(vm_clock, ptimer_tick, s);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
return s;
}

2
hw/display/qxl-logger.c
View File

@ -242,7 +242,7 @@ int qxl_log_command(PCIQXLDevice *qxl, const char *ring, QXLCommandExt *ext)
if (!qxl->cmdlog) {
return 0;
}
fprintf(stderr, "%" PRId64 " qxl-%d/%s:", qemu_get_clock_ns(vm_clock),
fprintf(stderr, "%" PRId64 " qxl-%d/%s:", qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
qxl->id, ring);
fprintf(stderr, " cmd @ 0x%" PRIx64 " %s%s", ext->cmd.data,
qxl_name(qxl_type, ext->cmd.type),

2
hw/display/qxl.c
View File

@ -1596,7 +1596,7 @@ async_common:
trace_qxl_io_log(d->id, d->ram->log_buf);
if (d->guestdebug) {
fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
qemu_get_clock_ns(vm_clock), d->ram->log_buf);
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf);
}
break;
case QXL_IO_RESET:

6
hw/display/vga.c
View File

@ -318,7 +318,7 @@ static uint8_t vga_precise_retrace(VGACommonState *s)
int cur_line, cur_line_char, cur_char;
int64_t cur_tick;
cur_tick = qemu_get_clock_ns(vm_clock);
cur_tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
cur_line = cur_char / r->htotal;
@ -1304,7 +1304,7 @@ static void vga_draw_text(VGACommonState *s, int full_update)
uint32_t *ch_attr_ptr;
vga_draw_glyph8_func *vga_draw_glyph8;
vga_draw_glyph9_func *vga_draw_glyph9;
int64_t now = qemu_get_clock_ms(vm_clock);
int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
/* compute font data address (in plane 2) */
v = s->sr[VGA_SEQ_CHARACTER_MAP];
@ -1907,7 +1907,7 @@ static void vga_update_display(void *opaque)
}
if (graphic_mode != s->graphic_mode) {
s->graphic_mode = graphic_mode;
s->cursor_blink_time = qemu_get_clock_ms(vm_clock);
s->cursor_blink_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
full_update = 1;
}
switch(graphic_mode) {

6
hw/dma/pl330.c
View File

@ -1256,7 +1256,7 @@ static void pl330_dma_stop_irq(void *opaque, int irq, int level)
if (s->periph_busy[irq] != level) {
s->periph_busy[irq] = level;
qemu_mod_timer(s->timer, qemu_get_clock_ns(vm_clock));
timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}
}
@ -1519,7 +1519,7 @@ static void pl330_reset(DeviceState *d)
s->periph_busy[i] = 0;
}
qemu_del_timer(s->timer);
timer_del(s->timer);
}
static void pl330_realize(DeviceState *dev, Error **errp)
@ -1532,7 +1532,7 @@ static void pl330_realize(DeviceState *dev, Error **errp)
"dma", PL330_IOMEM_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
s->timer = qemu_new_timer_ns(vm_clock, pl330_exec_cycle_timer, s);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s);
s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) |
(s->num_periph_req > 0 ? 1 : 0) |

4
hw/dma/rc4030.c
View File

@ -107,7 +107,7 @@ static void set_next_tick(rc4030State *s)
tm_hz = 1000 / (s->itr + 1);
qemu_mod_timer(s->periodic_timer, qemu_get_clock_ns(vm_clock) +
timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec() / tm_hz);
}
@ -806,7 +806,7 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
*irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
*dmas = rc4030_allocate_dmas(s, 4);
s->periodic_timer = qemu_new_timer_ns(vm_clock, rc4030_periodic_timer, s);
s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rc4030_periodic_timer, s);
s->timer_irq = timer;
s->jazz_bus_irq = jazz_bus;

8
hw/dma/soc_dma.c
View File

@ -84,10 +84,10 @@ struct dma_s {
static void soc_dma_ch_schedule(struct soc_dma_ch_s *ch, int delay_bytes)
{
int64_t now = qemu_get_clock_ns(vm_clock);
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
struct dma_s *dma = (struct dma_s *) ch->dma;
qemu_mod_timer(ch->timer, now + delay_bytes / dma->channel_freq);
timer_mod(ch->timer, now + delay_bytes / dma->channel_freq);
}
static void soc_dma_ch_run(void *opaque)
@ -217,7 +217,7 @@ void soc_dma_set_request(struct soc_dma_ch_s *ch, int level)
ch->enable = level;
if (!ch->enable)
qemu_del_timer(ch->timer);
timer_del(ch->timer);
else if (!ch->running)
soc_dma_ch_run(ch);
else
@ -246,7 +246,7 @@ struct soc_dma_s *soc_dma_init(int n)
for (i = 0; i < n; i ++) {
s->ch[i].dma = &s->soc;
s->ch[i].num = i;
s->ch[i].timer = qemu_new_timer_ns(vm_clock, soc_dma_ch_run, &s->ch[i]);
s->ch[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, soc_dma_ch_run, &s->ch[i]);
}
soc_dma_reset(&s->soc);

1
hw/dma/xilinx_axidma.c
View File

@ -27,6 +27,7 @@
#include "hw/ptimer.h"
#include "qemu/log.h"
#include "qapi/qmp/qerror.h"
#include "qemu/main-loop.h"
#include "hw/stream.h"

2
hw/i386/kvm/apic.c
View File

@ -79,7 +79,7 @@ void kvm_get_apic_state(DeviceState *d, struct kvm_lapic_state *kapic)
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
s->count_shift = (v + 1) & 7;
s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
apic_next_timer(s, s->initial_count_load_time);
}

6
hw/i386/kvm/i8254.c
View File

@ -65,12 +65,12 @@ static void kvm_pit_update_clock_offset(KVMPITState *s)
/*
* Measure the delta between CLOCK_MONOTONIC, the base used for
* kvm_pit_channel_state::count_load_time, and vm_clock. Take the
* kvm_pit_channel_state::count_load_time, and QEMU_CLOCK_VIRTUAL. Take the
* minimum of several samples to filter out scheduling noise.
*/
clock_offset = INT64_MAX;
for (i = 0; i < CALIBRATION_ROUNDS; i++) {
offset = qemu_get_clock_ns(vm_clock);
offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
clock_gettime(CLOCK_MONOTONIC, &ts);
offset -= ts.tv_nsec;
offset -= (int64_t)ts.tv_sec * 1000000000;
@ -194,7 +194,7 @@ static void kvm_pit_set_gate(PITCommonState *s, PITChannelState *sc, int val)
case 5:
if (sc->gate < val) {
/* restart counting on rising edge */
sc->count_load_time = qemu_get_clock_ns(vm_clock);
sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
break;
}

6
hw/i386/xen_domainbuild.c
View File

@ -148,7 +148,7 @@ static void xen_domain_poll(void *opaque)
goto quit;
}
qemu_mod_timer(xen_poll, qemu_get_clock_ms(rt_clock) + 1000);
timer_mod(xen_poll, qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + 1000);
return;
quit:
@ -290,8 +290,8 @@ int xen_domain_build_pv(const char *kernel, const char *ramdisk,
goto err;
}
xen_poll = qemu_new_timer_ms(rt_clock, xen_domain_poll, NULL);
qemu_mod_timer(xen_poll, qemu_get_clock_ms(rt_clock) + 1000);
xen_poll = timer_new_ms(QEMU_CLOCK_REALTIME, xen_domain_poll, NULL);
timer_mod(xen_poll, qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + 1000);
return 0;
err:

6
hw/ide/core.c
View File

@ -768,8 +768,8 @@ static void ide_sector_write_cb(void *opaque, int ret)
that at the expense of slower write performances. Use this
option _only_ to install Windows 2000. You must disable it
for normal use. */
qemu_mod_timer(s->sector_write_timer,
qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
timer_mod(s->sector_write_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
} else {
ide_set_irq(s->bus);
}
@ -2163,7 +2163,7 @@ static void ide_init1(IDEBus *bus, int unit)
s->smart_selftest_data = qemu_blockalign(s->bs, 512);
memset(s->smart_selftest_data, 0, 512);
s->sector_write_timer = qemu_new_timer_ns(vm_clock,
s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
ide_sector_write_timer_cb, s);
}

10
hw/input/hid.c
View File

@ -85,8 +85,8 @@ static void hid_idle_timer(void *opaque)
static void hid_del_idle_timer(HIDState *hs)
{
if (hs->idle_timer) {
qemu_del_timer(hs->idle_timer);
qemu_free_timer(hs->idle_timer);
timer_del(hs->idle_timer);
timer_free(hs->idle_timer);
hs->idle_timer = NULL;
}
}
@ -94,12 +94,12 @@ static void hid_del_idle_timer(HIDState *hs)
void hid_set_next_idle(HIDState *hs)
{
if (hs->idle) {
uint64_t expire_time = qemu_get_clock_ns(vm_clock) +
uint64_t expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec() * hs->idle * 4 / 1000;
if (!hs->idle_timer) {
hs->idle_timer = qemu_new_timer_ns(vm_clock, hid_idle_timer, hs);
hs->idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hid_idle_timer, hs);
}
qemu_mod_timer_ns(hs->idle_timer, expire_time);
timer_mod_ns(hs->idle_timer, expire_time);
} else {
hid_del_idle_timer(hs);
}

8
hw/input/lm832x.c
View File

@ -365,7 +365,7 @@ static void lm_kbd_write(LM823KbdState *s, int reg, int byte, uint8_t value)
break;
}
qemu_del_timer(s->pwm.tm[(value & 3) - 1]);
timer_del(s->pwm.tm[(value & 3) - 1]);
break;
case LM832x_GENERAL_ERROR:
@ -463,9 +463,9 @@ static int lm8323_init(I2CSlave *i2c)
LM823KbdState *s = FROM_I2C_SLAVE(LM823KbdState, i2c);
s->model = 0x8323;
s->pwm.tm[0] = qemu_new_timer_ns(vm_clock, lm_kbd_pwm0_tick, s);
s->pwm.tm[1] = qemu_new_timer_ns(vm_clock, lm_kbd_pwm1_tick, s);
s->pwm.tm[2] = qemu_new_timer_ns(vm_clock, lm_kbd_pwm2_tick, s);
s->pwm.tm[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm0_tick, s);
s->pwm.tm[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm1_tick, s);
s->pwm.tm[2] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm2_tick, s);
qdev_init_gpio_out(&i2c->qdev, &s->nirq, 1);
lm_kbd_reset(s);

16
hw/input/tsc2005.c
View File

@ -201,7 +201,7 @@ static void tsc2005_write(TSC2005State *s, int reg, uint16_t data)
fprintf(stderr, "%s: touchscreen sense %sabled\n",
__FUNCTION__, s->enabled ? "en" : "dis");
if (s->busy && !s->enabled)
qemu_del_timer(s->timer);
timer_del(s->timer);
s->busy &= s->enabled;
}
s->nextprecision = (data >> 13) & 1;
@ -290,8 +290,8 @@ static void tsc2005_pin_update(TSC2005State *s)
s->precision = s->nextprecision;
s->function = s->nextfunction;
s->pdst = !s->pnd0; /* Synchronised on internal clock */
expires = qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() >> 7);
qemu_mod_timer(s->timer, expires);
expires = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() >> 7);
timer_mod(s->timer, expires);
}
static void tsc2005_reset(TSC2005State *s)
@ -337,7 +337,7 @@ static uint8_t tsc2005_txrx_word(void *opaque, uint8_t value)
fprintf(stderr, "%s: touchscreen sense %sabled\n",
__FUNCTION__, s->enabled ? "en" : "dis");
if (s->busy && !s->enabled)
qemu_del_timer(s->timer);
timer_del(s->timer);
s->busy &= s->enabled;
}
tsc2005_pin_update(s);
@ -449,7 +449,7 @@ static void tsc2005_save(QEMUFile *f, void *opaque)
qemu_put_be16s(f, &s->dav);
qemu_put_be16s(f, &s->data);
qemu_put_timer(f, s->timer);
timer_put(f, s->timer);
qemu_put_byte(f, s->enabled);
qemu_put_byte(f, s->host_mode);
qemu_put_byte(f, s->function);
@ -490,7 +490,7 @@ static int tsc2005_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_be16s(f, &s->dav);
qemu_get_be16s(f, &s->data);
qemu_get_timer(f, s->timer);
timer_get(f, s->timer);
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
@ -513,7 +513,7 @@ static int tsc2005_load(QEMUFile *f, void *opaque, int version_id)
for (i = 0; i < 8; i ++)
s->tr[i] = qemu_get_be32(f);
s->busy = qemu_timer_pending(s->timer);
s->busy = timer_pending(s->timer);
tsc2005_pin_update(s);
return 0;
@ -529,7 +529,7 @@ void *tsc2005_init(qemu_irq pintdav)
s->y = 240;
s->pressure = 0;
s->precision = s->nextprecision = 0;
s->timer = qemu_new_timer_ns(vm_clock, tsc2005_timer_tick, s);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tsc2005_timer_tick, s);
s->pint = pintdav;
s->model = 0x2005;

32
hw/input/tsc210x.c
View File

@ -503,9 +503,9 @@ static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg)
l_ch = 1;
r_ch = 1;
if (s->softstep && !(s->dac_power & (1 << 10))) {
l_ch = (qemu_get_clock_ns(vm_clock) >
l_ch = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
s->volume_change + TSC_SOFTSTEP_DELAY);
r_ch = (qemu_get_clock_ns(vm_clock) >
r_ch = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
s->volume_change + TSC_SOFTSTEP_DELAY);
}
@ -514,7 +514,7 @@ static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg)
case 0x05: /* Stereo DAC Power Control */
return 0x2aa0 | s->dac_power |
(((s->dac_power & (1 << 10)) &&
(qemu_get_clock_ns(vm_clock) >
(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
s->powerdown + TSC_POWEROFF_DELAY)) << 6);
case 0x06: /* Audio Control 3 */
@ -594,7 +594,7 @@ static void tsc2102_control_register_write(
s->host_mode = value >> 15;
s->enabled = !(value & 0x4000);
if (s->busy && !s->enabled)
qemu_del_timer(s->timer);
timer_del(s->timer);
s->busy &= s->enabled;
s->nextfunction = (value >> 10) & 0xf;
s->nextprecision = (value >> 8) & 3;
@ -629,7 +629,7 @@ static void tsc2102_control_register_write(
case 0x04: /* Reset */
if (value == 0xbb00) {
if (s->busy)
qemu_del_timer(s->timer);
timer_del(s->timer);
tsc210x_reset(s);
#ifdef TSC_VERBOSE
} else {
@ -695,7 +695,7 @@ static void tsc2102_audio_register_write(
case 0x02: /* DAC Volume Control */
s->volume = value;
s->volume_change = qemu_get_clock_ns(vm_clock);
s->volume_change = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
return;
case 0x03:
@ -717,7 +717,7 @@ static void tsc2102_audio_register_write(
case 0x05: /* Stereo DAC Power Control */
if ((value & ~s->dac_power) & (1 << 10))
s->powerdown = qemu_get_clock_ns(vm_clock);
s->powerdown = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->dac_power = value & 0x9543;
#ifdef TSC_VERBOSE
@ -864,8 +864,8 @@ static void tsc210x_pin_update(TSC210xState *s)
s->busy = 1;
s->precision = s->nextprecision;
s->function = s->nextfunction;
expires = qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() >> 10);
qemu_mod_timer(s->timer, expires);
expires = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() >> 10);
timer_mod(s->timer, expires);
}
static uint16_t tsc210x_read(TSC210xState *s)
@ -1005,7 +1005,7 @@ static void tsc210x_i2s_set_rate(TSC210xState *s, int in, int out)
static void tsc210x_save(QEMUFile *f, void *opaque)
{
TSC210xState *s = (TSC210xState *) opaque;
int64_t now = qemu_get_clock_ns(vm_clock);
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int i;
qemu_put_be16(f, s->x);
@ -1020,7 +1020,7 @@ static void tsc210x_save(QEMUFile *f, void *opaque)
qemu_put_byte(f, s->irq);
qemu_put_be16s(f, &s->dav);
qemu_put_timer(f, s->timer);
timer_put(f, s->timer);
qemu_put_byte(f, s->enabled);
qemu_put_byte(f, s->host_mode);
qemu_put_byte(f, s->function);
@ -1051,7 +1051,7 @@ static void tsc210x_save(QEMUFile *f, void *opaque)
static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
{
TSC210xState *s = (TSC210xState *) opaque;
int64_t now = qemu_get_clock_ns(vm_clock);
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int i;
s->x = qemu_get_be16(f);
@ -1066,7 +1066,7 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->irq = qemu_get_byte(f);
qemu_get_be16s(f, &s->dav);
qemu_get_timer(f, s->timer);
timer_get(f, s->timer);
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
@ -1093,7 +1093,7 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
for (i = 0; i < 0x14; i ++)
qemu_get_be16s(f, &s->filter_data[i]);
s->busy = qemu_timer_pending(s->timer);
s->busy = timer_pending(s->timer);
qemu_set_irq(s->pint, !s->irq);
qemu_set_irq(s->davint, !s->dav);
@ -1111,7 +1111,7 @@ uWireSlave *tsc2102_init(qemu_irq pint)
s->y = 160;
s->pressure = 0;
s->precision = s->nextprecision = 0;
s->timer = qemu_new_timer_ns(vm_clock, tsc210x_timer_tick, s);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tsc210x_timer_tick, s);
s->pint = pint;
s->model = 0x2102;
s->name = "tsc2102";
@ -1160,7 +1160,7 @@ uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav)
s->y = 240;
s->pressure = 0;
s->precision = s->nextprecision = 0;
s->timer = qemu_new_timer_ns(vm_clock, tsc210x_timer_tick, s);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tsc210x_timer_tick, s);
s->pint = penirq;
s->kbint = kbirq;
s->davint = dav;

16
hw/intc/apic.c
View File

@ -606,7 +606,7 @@ static uint32_t apic_get_current_count(APICCommonState *s)
{
int64_t d;
uint32_t val;
d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >>
d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >>
s->count_shift;
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
/* periodic */
@ -623,9 +623,9 @@ static uint32_t apic_get_current_count(APICCommonState *s)
static void apic_timer_update(APICCommonState *s, int64_t current_time)
{
if (apic_next_timer(s, current_time)) {
qemu_mod_timer(s->timer, s->next_time);
timer_mod(s->timer, s->next_time);
} else {
qemu_del_timer(s->timer);
timer_del(s->timer);
}
}
@ -822,7 +822,7 @@ static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
int n = index - 0x32;
s->lvt[n] = val;
if (n == APIC_LVT_TIMER) {
apic_timer_update(s, qemu_get_clock_ns(vm_clock));
apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
} else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) {
apic_update_irq(s);
}
@ -830,7 +830,7 @@ static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
break;
case 0x38:
s->initial_count = val;
s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
apic_timer_update(s, s->initial_count_load_time);
break;
case 0x39:
@ -857,9 +857,9 @@ static void apic_pre_save(APICCommonState *s)
static void apic_post_load(APICCommonState *s)
{
if (s->timer_expiry != -1) {
qemu_mod_timer(s->timer, s->timer_expiry);
timer_mod(s->timer, s->timer_expiry);
} else {
qemu_del_timer(s->timer);
timer_del(s->timer);
}
}
@ -876,7 +876,7 @@ static void apic_init(APICCommonState *s)
memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi",
APIC_SPACE_SIZE);
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s);
local_apics[s->idx] = s;
msi_supported = true;

2
hw/intc/apic_common.c
View File

@ -198,7 +198,7 @@ void apic_init_reset(DeviceState *d)
s->wait_for_sipi = 1;
if (s->timer) {
qemu_del_timer(s->timer);
timer_del(s->timer);
}
s->timer_expiry = -1;
}

16
hw/intc/armv7m_nvic.c
View File

@ -78,9 +78,9 @@ static inline int64_t systick_scale(nvic_state *s)
static void systick_reload(nvic_state *s, int reset)
{
if (reset)
s->systick.tick = qemu_get_clock_ns(vm_clock);
s->systick.tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
qemu_mod_timer(s->systick.timer, s->systick.tick);
timer_mod(s->systick.timer, s->systick.tick);
}
static void systick_timer_tick(void * opaque)
@ -103,7 +103,7 @@ static void systick_reset(nvic_state *s)
s->systick.control = 0;
s->systick.reload = 0;
s->systick.tick = 0;
qemu_del_timer(s->systick.timer);
timer_del(s->systick.timer);
}
/* The external routines use the hardware vector numbering, ie. the first
@ -158,7 +158,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
int64_t t;
if ((s->systick.control & SYSTICK_ENABLE) == 0)
return 0;
t = qemu_get_clock_ns(vm_clock);
t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (t >= s->systick.tick)
return 0;
val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
@ -290,16 +290,16 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
s->systick.control &= 0xfffffff8;
s->systick.control |= value & 7;
if ((oldval ^ value) & SYSTICK_ENABLE) {
int64_t now = qemu_get_clock_ns(vm_clock);
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (value & SYSTICK_ENABLE) {
if (s->systick.tick) {
s->systick.tick += now;
qemu_mod_timer(s->systick.timer, s->systick.tick);
timer_mod(s->systick.timer, s->systick.tick);
} else {
systick_reload(s, 1);
}
} else {
qemu_del_timer(s->systick.timer);
timer_del(s->systick.timer);
s->systick.tick -= now;
if (s->systick.tick < 0)
s->systick.tick = 0;
@ -511,7 +511,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
* by the v7M architecture.
*/
memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
}
static void armv7m_nvic_instance_init(Object *obj)

4
hw/intc/i8259.c
View File

@ -150,7 +150,7 @@ static void pic_set_irq(void *opaque, int irq, int level)
#endif
#ifdef DEBUG_IRQ_LATENCY
if (level) {
irq_time[irq_index] = qemu_get_clock_ns(vm_clock);
irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
#endif
@ -228,7 +228,7 @@ int pic_read_irq(DeviceState *d)
#ifdef DEBUG_IRQ_LATENCY
printf("IRQ%d latency=%0.3fus\n",
irq,
(double)(qemu_get_clock_ns(vm_clock) -
(double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
#endif
DPRINTF("pic_interrupt: irq=%d\n", irq);

16
hw/mips/cputimer.c
View File

@ -47,11 +47,11 @@ static void cpu_mips_timer_update(CPUMIPSState *env)
uint64_t now, next;
uint32_t wait;
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
wait = env->CP0_Compare - env->CP0_Count -
(uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
qemu_mod_timer(env->timer, next);
timer_mod(env->timer, next);
}
/* Expire the timer. */
@ -71,9 +71,9 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env)
} else {
uint64_t now;
now = qemu_get_clock_ns(vm_clock);
if (qemu_timer_pending(env->timer)
&& qemu_timer_expired(env->timer, now)) {
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (timer_pending(env->timer)
&& timer_expired(env->timer, now)) {
/* The timer has already expired. */
cpu_mips_timer_expire(env);
}
@ -90,7 +90,7 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
else {
/* Store new count register */
env->CP0_Count =
count - (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
count - (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
TIMER_FREQ, get_ticks_per_sec());
/* Update timer timer */
cpu_mips_timer_update(env);
@ -115,7 +115,7 @@ void cpu_mips_start_count(CPUMIPSState *env)
void cpu_mips_stop_count(CPUMIPSState *env)
{
/* Store the current value */
env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
env->CP0_Count += (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
TIMER_FREQ, get_ticks_per_sec());
}
@ -141,7 +141,7 @@ static void mips_timer_cb (void *opaque)
void cpu_mips_clock_init (CPUMIPSState *env)
{
env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
env->CP0_Compare = 0;
cpu_mips_store_count(env, 1);
}

2
hw/misc/arm_sysctl.c
View File

@ -170,7 +170,7 @@ static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
case 0x58: /* BOOTCS */
return 0;
case 0x5c: /* 24MHz */
return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24000000, get_ticks_per_sec());
case 0x60: /* MISC */
return 0;
case 0x84: /* PROCID0 */

34
hw/misc/macio/cuda.c
View File

@ -128,7 +128,7 @@ static unsigned int get_counter(CUDATimer *s)
int64_t d;
unsigned int counter;
d = muldiv64(qemu_get_clock_ns(vm_clock) - s->load_time,
d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->load_time,
CUDA_TIMER_FREQ, get_ticks_per_sec());
if (s->index == 0) {
/* the timer goes down from latch to -1 (period of latch + 2) */
@ -147,7 +147,7 @@ static unsigned int get_counter(CUDATimer *s)
static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
{
CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val);
ti->load_time = qemu_get_clock_ns(vm_clock);
ti->load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ti->counter_value = val;
cuda_timer_update(s, ti, ti->load_time);
}
@ -191,10 +191,10 @@ static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
if (!ti->timer)
return;
if ((s->acr & T1MODE) != T1MODE_CONT) {
qemu_del_timer(ti->timer);
timer_del(ti->timer);
} else {
ti->next_irq_time = get_next_irq_time(ti, current_time);
qemu_mod_timer(ti->timer, ti->next_irq_time);
timer_mod(ti->timer, ti->next_irq_time);
}
}
@ -304,7 +304,7 @@ static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val)
break;
case 4:
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case 5:
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
@ -313,12 +313,12 @@ static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val)
break;
case 6:
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case 7:
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
s->ifr &= ~T1_INT;
cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case 8:
s->timers[1].latch = val;
@ -332,7 +332,7 @@ static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val)
break;
case 11:
s->acr = val;
cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
cuda_update(s);
break;
case 12:
@ -463,8 +463,8 @@ static void cuda_adb_poll(void *opaque)
obuf[1] = 0x40; /* polled data */
cuda_send_packet_to_host(s, obuf, olen + 2);
}
qemu_mod_timer(s->adb_poll_timer,
qemu_get_clock_ns(vm_clock) +
timer_mod(s->adb_poll_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
}
@ -481,11 +481,11 @@ static void cuda_receive_packet(CUDAState *s,
if (autopoll != s->autopoll) {
s->autopoll = autopoll;
if (autopoll) {
qemu_mod_timer(s->adb_poll_timer,
qemu_get_clock_ns(vm_clock) +
timer_mod(s->adb_poll_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
} else {
qemu_del_timer(s->adb_poll_timer);
timer_del(s->adb_poll_timer);
}
}
obuf[0] = CUDA_PACKET;
@ -494,14 +494,14 @@ static void cuda_receive_packet(CUDAState *s,
break;
case CUDA_SET_TIME:
ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4];
s->tick_offset = ti - (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec());
s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec());
obuf[0] = CUDA_PACKET;
obuf[1] = 0;
obuf[2] = 0;
cuda_send_packet_to_host(s, obuf, 3);
break;
case CUDA_GET_TIME:
ti = s->tick_offset + (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec());
ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec());
obuf[0] = CUDA_PACKET;
obuf[1] = 0;
obuf[2] = 0;
@ -689,12 +689,12 @@ static void cuda_realizefn(DeviceState *dev, Error **errp)
CUDAState *s = CUDA(dev);
struct tm tm;
s->timers[0].timer = qemu_new_timer_ns(vm_clock, cuda_timer1, s);
s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s);
qemu_get_timedate(&tm, 0);
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
s->adb_poll_timer = qemu_new_timer_ns(vm_clock, cuda_adb_poll, s);
s->adb_poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_adb_poll, s);
}
static void cuda_initfn(Object *obj)

4
hw/misc/macio/macio.c
View File

@ -245,10 +245,10 @@ static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
switch (addr) {
case 0x38:
value = qemu_get_clock_ns(vm_clock);
value = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
break;
case 0x3c:
value = qemu_get_clock_ns(vm_clock) >> 32;
value = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 32;
break;
}

14
hw/misc/vfio.c
View File

@ -276,8 +276,8 @@ static void vfio_intx_mmap_enable(void *opaque)
VFIODevice *vdev = opaque;
if (vdev->intx.pending) {
qemu_mod_timer(vdev->intx.mmap_timer,
qemu_get_clock_ms(vm_clock) + vdev->intx.mmap_timeout);
timer_mod(vdev->intx.mmap_timer,
qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout);
return;
}
@ -300,8 +300,8 @@ static void vfio_intx_interrupt(void *opaque)
qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 1);
vfio_mmap_set_enabled(vdev, false);
if (vdev->intx.mmap_timeout) {
qemu_mod_timer(vdev->intx.mmap_timer,
qemu_get_clock_ms(vm_clock) + vdev->intx.mmap_timeout);
timer_mod(vdev->intx.mmap_timer,
qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout);
}
}
@ -543,7 +543,7 @@ static void vfio_disable_intx(VFIODevice *vdev)
{
int fd;
qemu_del_timer(vdev->intx.mmap_timer);
timer_del(vdev->intx.mmap_timer);
vfio_disable_intx_kvm(vdev);
vfio_disable_irqindex(vdev, VFIO_PCI_INTX_IRQ_INDEX);
vdev->intx.pending = false;
@ -3176,7 +3176,7 @@ static int vfio_initfn(PCIDevice *pdev)
}
if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) {
vdev->intx.mmap_timer = qemu_new_timer_ms(vm_clock,
vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
vfio_intx_mmap_enable, vdev);
pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_update_irq);
ret = vfio_enable_intx(vdev);
@ -3210,7 +3210,7 @@ static void vfio_exitfn(PCIDevice *pdev)
pci_device_set_intx_routing_notifier(&vdev->pdev, NULL);
vfio_disable_interrupts(vdev);
if (vdev->intx.mmap_timer) {
qemu_free_timer(vdev->intx.mmap_timer);
timer_free(vdev->intx.mmap_timer);
}
vfio_teardown_msi(vdev);
vfio_unmap_bars(vdev);

20
hw/net/dp8393x.c
View File

@ -274,7 +274,7 @@ static void do_read_rra(dp8393xState *s)
static void do_software_reset(dp8393xState *s)
{
qemu_del_timer(s->watchdog);
timer_del(s->watchdog);
s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
@ -286,14 +286,14 @@ static void set_next_tick(dp8393xState *s)
int64_t delay;
if (s->regs[SONIC_CR] & SONIC_CR_STP) {
qemu_del_timer(s->watchdog);
timer_del(s->watchdog);
return;
}
ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
s->wt_last_update = qemu_get_clock_ns(vm_clock);
s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
delay = get_ticks_per_sec() * ticks / 5000000;
qemu_mod_timer(s->watchdog, s->wt_last_update + delay);
timer_mod(s->watchdog, s->wt_last_update + delay);
}
static void update_wt_regs(dp8393xState *s)
@ -302,11 +302,11 @@ static void update_wt_regs(dp8393xState *s)
uint32_t val;
if (s->regs[SONIC_CR] & SONIC_CR_STP) {
qemu_del_timer(s->watchdog);
timer_del(s->watchdog);
return;
}
elapsed = s->wt_last_update - qemu_get_clock_ns(vm_clock);
elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
val = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
val -= elapsed / 5000000;
s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
@ -838,7 +838,7 @@ static ssize_t nic_receive(NetClientState *nc, const uint8_t * buf, size_t size)
static void nic_reset(void *opaque)
{
dp8393xState *s = opaque;
qemu_del_timer(s->watchdog);
timer_del(s->watchdog);
s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
@ -866,8 +866,8 @@ static void nic_cleanup(NetClientState *nc)
memory_region_del_subregion(s->address_space, &s->mmio);
memory_region_destroy(&s->mmio);
qemu_del_timer(s->watchdog);
qemu_free_timer(s->watchdog);
timer_del(s->watchdog);
timer_free(s->watchdog);
g_free(s);
}
@ -896,7 +896,7 @@ void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
s->memory_rw = memory_rw;
s->it_shift = it_shift;
s->irq = irq;
s->watchdog = qemu_new_timer_ns(vm_clock, dp8393x_watchdog, s);
s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
s->conf.macaddr = nd->macaddr;

12
hw/net/e1000.c
View File

@ -190,7 +190,7 @@ set_phy_ctrl(E1000State *s, int index, uint16_t val)
e1000_link_down(s);
s->phy_reg[PHY_STATUS] &= ~MII_SR_AUTONEG_COMPLETE;
DBGOUT(PHY, "Start link auto negotiation\n");
qemu_mod_timer(s->autoneg_timer, qemu_get_clock_ms(vm_clock) + 500);
timer_mod(s->autoneg_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
}
}
@ -306,7 +306,7 @@ static void e1000_reset(void *opaque)
uint8_t *macaddr = d->conf.macaddr.a;
int i;
qemu_del_timer(d->autoneg_timer);
timer_del(d->autoneg_timer);
memset(d->phy_reg, 0, sizeof d->phy_reg);
memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
memset(d->mac_reg, 0, sizeof d->mac_reg);
@ -1184,7 +1184,7 @@ static int e1000_post_load(void *opaque, int version_id)
s->phy_reg[PHY_CTRL] & MII_CR_RESTART_AUTO_NEG &&
!(s->phy_reg[PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
nc->link_down = false;
qemu_mod_timer(s->autoneg_timer, qemu_get_clock_ms(vm_clock) + 500);
timer_mod(s->autoneg_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
}
return 0;
@ -1314,8 +1314,8 @@ pci_e1000_uninit(PCIDevice *dev)
{
E1000State *d = E1000(dev);
qemu_del_timer(d->autoneg_timer);
qemu_free_timer(d->autoneg_timer);
timer_del(d->autoneg_timer);
timer_free(d->autoneg_timer);
memory_region_destroy(&d->mmio);
memory_region_destroy(&d->io);
qemu_del_nic(d->nic);
@ -1370,7 +1370,7 @@ static int pci_e1000_init(PCIDevice *pci_dev)
add_boot_device_path(d->conf.bootindex, dev, "/ethernet-phy@0");
d->autoneg_timer = qemu_new_timer_ms(vm_clock, e1000_autoneg_timer, d);
d->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, e1000_autoneg_timer, d);
return 0;
}

4
hw/net/lan9118.c
View File

@ -439,7 +439,7 @@ static void lan9118_reset(DeviceState *d)
s->afc_cfg = 0;
s->e2p_cmd = 0;
s->e2p_data = 0;
s->free_timer_start = qemu_get_clock_ns(vm_clock) / 40;
s->free_timer_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40;
ptimer_stop(s->timer);
ptimer_set_count(s->timer, 0xffff);
@ -1236,7 +1236,7 @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
case CSR_WORD_SWAP:
return s->word_swap;
case CSR_FREE_RUN:
return (qemu_get_clock_ns(vm_clock) / 40) - s->free_timer_start;
return (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40) - s->free_timer_start;
case CSR_RX_DROP:
/* TODO: Implement dropped frames counter. */
return 0;

4
hw/net/pcnet-pci.c
View File

@ -284,8 +284,8 @@ static void pci_pcnet_uninit(PCIDevice *dev)
memory_region_destroy(&d->state.mmio);
memory_region_destroy(&d->io_bar);
qemu_del_timer(d->state.poll_timer);
qemu_free_timer(d->state.poll_timer);
timer_del(d->state.poll_timer);
timer_free(d->state.poll_timer);
qemu_del_nic(d->state.nic);
}

10
hw/net/pcnet.c
View File

@ -1331,7 +1331,7 @@ static void pcnet_poll_timer(void *opaque)
{
PCNetState *s = opaque;
qemu_del_timer(s->poll_timer);
timer_del(s->poll_timer);
if (CSR_TDMD(s)) {
pcnet_transmit(s);
@ -1340,7 +1340,7 @@ static void pcnet_poll_timer(void *opaque)
pcnet_update_irq(s);
if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
uint64_t now = qemu_get_clock_ns(vm_clock) * 33;
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) * 33;
if (!s->timer || !now)
s->timer = now;
else {
@ -1351,8 +1351,8 @@ static void pcnet_poll_timer(void *opaque)
} else
CSR_POLL(s) = t;
}
qemu_mod_timer(s->poll_timer,
pcnet_get_next_poll_time(s,qemu_get_clock_ns(vm_clock)));
timer_mod(s->poll_timer,
pcnet_get_next_poll_time(s,qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)));
}
}
@ -1731,7 +1731,7 @@ int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info)
int i;
uint16_t checksum;
s->poll_timer = qemu_new_timer_ns(vm_clock, pcnet_poll_timer, s);
s->poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pcnet_poll_timer, s);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(info, &s->conf, object_get_typename(OBJECT(dev)), dev->id, s);

28
hw/net/rtl8139.c
View File

@ -2648,7 +2648,7 @@ static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
s->IntrMask = val;
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
rtl8139_update_irq(s);
}
@ -2689,7 +2689,7 @@ static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
* and probably emulated is slower is better to assume this resetting was
* done before testing on previous rtl8139_update_irq lead to IRQ losing
*/
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
rtl8139_update_irq(s);
#endif
@ -2697,7 +2697,7 @@ static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
{
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
uint32_t ret = s->IntrStatus;
@ -2913,7 +2913,7 @@ static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
s->TimerExpire = next_time;
if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
qemu_mod_timer(s->timer, next_time);
timer_mod(s->timer, next_time);
}
}
@ -2960,7 +2960,7 @@ static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
case Timer:
DPRINTF("TCTR Timer reset on write\n");
s->TCTR_base = qemu_get_clock_ns(vm_clock);
s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
rtl8139_set_next_tctr_time(s, s->TCTR_base);
break;
@ -2968,7 +2968,7 @@ static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
if (s->TimerInt != val) {
s->TimerInt = val;
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}
break;
@ -3183,7 +3183,7 @@ static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
break;
case Timer:
ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base,
PCI_FREQUENCY, get_ticks_per_sec());
DPRINTF("TCTR Timer read val=0x%08x\n", ret);
break;
@ -3245,7 +3245,7 @@ static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr)
static int rtl8139_post_load(void *opaque, int version_id)
{
RTL8139State* s = opaque;
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
if (version_id < 4) {
s->cplus_enabled = s->CpCmd != 0;
}
@ -3275,7 +3275,7 @@ static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
static void rtl8139_pre_save(void *opaque)
{
RTL8139State* s = opaque;
int64_t current_time = qemu_get_clock_ns(vm_clock);
int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
/* set IntrStatus correctly */
rtl8139_set_next_tctr_time(s, current_time);
@ -3446,7 +3446,7 @@ static void rtl8139_timer(void *opaque)
s->IntrStatus |= PCSTimeout;
rtl8139_update_irq(s);
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}
static void rtl8139_cleanup(NetClientState *nc)
@ -3466,8 +3466,8 @@ static void pci_rtl8139_uninit(PCIDevice *dev)
g_free(s->cplus_txbuffer);
s->cplus_txbuffer = NULL;
}
qemu_del_timer(s->timer);
qemu_free_timer(s->timer);
timer_del(s->timer);
timer_free(s->timer);
qemu_del_nic(s->nic);
}
@ -3535,8 +3535,8 @@ static int pci_rtl8139_init(PCIDevice *dev)
s->cplus_txbuffer_offset = 0;
s->TimerExpire = 0;
s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s);
rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
add_boot_device_path(s->conf.bootindex, d, "/ethernet-phy@0");

20
hw/net/virtio-net.c
View File

@ -162,14 +162,14 @@ static void virtio_net_set_status(struct VirtIODevice *vdev, uint8_t status)
if (virtio_net_started(n, queue_status) && !n->vhost_started) {
if (q->tx_timer) {
qemu_mod_timer(q->tx_timer,
qemu_get_clock_ns(vm_clock) + n->tx_timeout);
timer_mod(q->tx_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + n->tx_timeout);
} else {
qemu_bh_schedule(q->tx_bh);
}
} else {
if (q->tx_timer) {
qemu_del_timer(q->tx_timer);
timer_del(q->tx_timer);
} else {
qemu_bh_cancel(q->tx_bh);
}
@ -1131,12 +1131,12 @@ static void virtio_net_handle_tx_timer(VirtIODevice *vdev, VirtQueue *vq)
if (q->tx_waiting) {
virtio_queue_set_notification(vq, 1);
qemu_del_timer(q->tx_timer);
timer_del(q->tx_timer);
q->tx_waiting = 0;
virtio_net_flush_tx(q);
} else {
qemu_mod_timer(q->tx_timer,
qemu_get_clock_ns(vm_clock) + n->tx_timeout);
timer_mod(q->tx_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + n->tx_timeout);
q->tx_waiting = 1;
virtio_queue_set_notification(vq, 0);
}
@ -1233,7 +1233,7 @@ static void virtio_net_set_multiqueue(VirtIONet *n, int multiqueue)
if (n->vqs[i].tx_timer) {
n->vqs[i].tx_vq =
virtio_add_queue(vdev, 256, virtio_net_handle_tx_timer);
n->vqs[i].tx_timer = qemu_new_timer_ns(vm_clock,
n->vqs[i].tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
virtio_net_tx_timer,
&n->vqs[i]);
} else {
@ -1513,7 +1513,7 @@ static int virtio_net_device_init(VirtIODevice *vdev)
if (n->net_conf.tx && !strcmp(n->net_conf.tx, "timer")) {
n->vqs[0].tx_vq = virtio_add_queue(vdev, 256,
virtio_net_handle_tx_timer);
n->vqs[0].tx_timer = qemu_new_timer_ns(vm_clock, virtio_net_tx_timer,
n->vqs[0].tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, virtio_net_tx_timer,
&n->vqs[0]);
} else {
n->vqs[0].tx_vq = virtio_add_queue(vdev, 256,
@ -1598,8 +1598,8 @@ static int virtio_net_device_exit(DeviceState *qdev)
qemu_purge_queued_packets(nc);
if (q->tx_timer) {
qemu_del_timer(q->tx_timer);
qemu_free_timer(q->tx_timer);
timer_del(q->tx_timer);
timer_free(q->tx_timer);
} else {
qemu_bh_delete(q->tx_bh);
}

10
hw/openrisc/cputimer.c
View File

@ -33,9 +33,9 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu)
uint64_t now, next;
uint32_t wait;
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (!is_counting) {
qemu_del_timer(cpu->env.timer);
timer_del(cpu->env.timer);
last_clk = now;
return;
}
@ -52,7 +52,7 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu)
}
next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
qemu_mod_timer(cpu->env.timer, next);
timer_mod(cpu->env.timer, next);
}
void cpu_openrisc_count_start(OpenRISCCPU *cpu)
@ -72,7 +72,7 @@ static void openrisc_timer_cb(void *opaque)
OpenRISCCPU *cpu = opaque;
if ((cpu->env.ttmr & TTMR_IE) &&
qemu_timer_expired(cpu->env.timer, qemu_get_clock_ns(vm_clock))) {
timer_expired(cpu->env.timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL))) {
CPUState *cs = CPU(cpu);
cpu->env.ttmr |= TTMR_IP;
@ -97,7 +97,7 @@ static void openrisc_timer_cb(void *opaque)
void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
{
cpu->env.timer = qemu_new_timer_ns(vm_clock, &openrisc_timer_cb, cpu);
cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu);
cpu->env.ttmr = 0x00000000;
cpu->env.ttcr = 0x00000000;
}

64
hw/ppc/ppc.c
View File

@ -471,7 +471,7 @@ uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
return env->spr[SPR_TBL];
}
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb;
@ -482,7 +482,7 @@ static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb >> 32;
@ -510,9 +510,9 @@ void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
tb &= 0xFFFFFFFF00000000ULL;
cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
&tb_env->tb_offset, tb | (uint64_t)value);
}
@ -521,9 +521,9 @@ static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
tb &= 0x00000000FFFFFFFFULL;
cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
&tb_env->tb_offset, ((uint64_t)value << 32) | tb);
}
@ -537,7 +537,7 @@ uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb;
@ -548,7 +548,7 @@ uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb >> 32;
@ -559,9 +559,9 @@ void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
tb &= 0xFFFFFFFF00000000ULL;
cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
&tb_env->atb_offset, tb | (uint64_t)value);
}
@ -570,9 +570,9 @@ void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
tb &= 0x00000000FFFFFFFFULL;
cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
&tb_env->atb_offset, ((uint64_t)value << 32) | tb);
}
@ -583,7 +583,7 @@ static void cpu_ppc_tb_stop (CPUPPCState *env)
/* If the time base is already frozen, do nothing */
if (tb_env->tb_freq != 0) {
vmclk = qemu_get_clock_ns(vm_clock);
vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
/* Get the time base */
tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
/* Get the alternate time base */
@ -605,7 +605,7 @@ static void cpu_ppc_tb_start (CPUPPCState *env)
/* If the time base is not frozen, do nothing */
if (tb_env->tb_freq == 0) {
vmclk = qemu_get_clock_ns(vm_clock);
vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
/* Get the time base from tb_offset */
tb = tb_env->tb_offset;
/* Get the alternate time base from atb_offset */
@ -625,7 +625,7 @@ static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
uint32_t decr;
int64_t diff;
diff = next - qemu_get_clock_ns(vm_clock);
diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (diff >= 0) {
decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec());
} else if (tb_env->flags & PPC_TIMER_BOOKE) {
@ -661,7 +661,7 @@ uint64_t cpu_ppc_load_purr (CPUPPCState *env)
ppc_tb_t *tb_env = env->tb_env;
uint64_t diff;
diff = qemu_get_clock_ns(vm_clock) - tb_env->purr_start;
diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start;
return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec());
}
@ -701,7 +701,7 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
return;
}
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq);
if (is_excp) {
next += *nextp - now;
@ -711,7 +711,7 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
}
*nextp = next;
/* Adjust timer */
qemu_mod_timer(timer, next);
timer_mod(timer, next);
/* If we set a negative value and the decrementer was positive, raise an
* exception.
@ -776,7 +776,7 @@ static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
ppc_tb_t *tb_env = cpu->env.tb_env;
tb_env->purr_load = value;
tb_env->purr_start = qemu_get_clock_ns(vm_clock);
tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
@ -806,11 +806,11 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
env->tb_env = tb_env;
tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
/* Create new timer */
tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_decr_cb, cpu);
tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu);
if (0) {
/* XXX: find a suitable condition to enable the hypervisor decrementer
*/
tb_env->hdecr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_hdecr_cb,
tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb,
cpu);
} else {
tb_env->hdecr_timer = NULL;
@ -877,7 +877,7 @@ static void cpu_4xx_fit_cb (void *opaque)
cpu = ppc_env_get_cpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
case 0:
next = 1 << 9;
@ -898,7 +898,7 @@ static void cpu_4xx_fit_cb (void *opaque)
next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq);
if (next == now)
next++;
qemu_mod_timer(ppc40x_timer->fit_timer, next);
timer_mod(ppc40x_timer->fit_timer, next);
env->spr[SPR_40x_TSR] |= 1 << 26;
if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
@ -920,18 +920,18 @@ static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
(is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
/* Stop PIT */
LOG_TB("%s: stop PIT\n", __func__);
qemu_del_timer(tb_env->decr_timer);
timer_del(tb_env->decr_timer);
} else {
LOG_TB("%s: start PIT %016" PRIx64 "\n",
__func__, ppc40x_timer->pit_reload);
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
next = now + muldiv64(ppc40x_timer->pit_reload,
get_ticks_per_sec(), tb_env->decr_freq);
if (is_excp)
next += tb_env->decr_next - now;
if (next == now)
next++;
qemu_mod_timer(tb_env->decr_timer, next);
timer_mod(tb_env->decr_timer, next);
tb_env->decr_next = next;
}
}
@ -973,7 +973,7 @@ static void cpu_4xx_wdt_cb (void *opaque)
cpu = ppc_env_get_cpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
case 0:
next = 1 << 17;
@ -999,12 +999,12 @@ static void cpu_4xx_wdt_cb (void *opaque)
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
case 0x0:
case 0x1:
qemu_mod_timer(ppc40x_timer->wdt_timer, next);
timer_mod(ppc40x_timer->wdt_timer, next);
ppc40x_timer->wdt_next = next;
env->spr[SPR_40x_TSR] |= 1 << 31;
break;
case 0x2:
qemu_mod_timer(ppc40x_timer->wdt_timer, next);
timer_mod(ppc40x_timer->wdt_timer, next);
ppc40x_timer->wdt_next = next;
env->spr[SPR_40x_TSR] |= 1 << 30;
if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
@ -1076,11 +1076,11 @@ clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
if (ppc40x_timer != NULL) {
/* We use decr timer for PIT */
tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_4xx_pit_cb, env);
tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env);
ppc40x_timer->fit_timer =
qemu_new_timer_ns(vm_clock, &cpu_4xx_fit_cb, env);
timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env);
ppc40x_timer->wdt_timer =
qemu_new_timer_ns(vm_clock, &cpu_4xx_wdt_cb, env);
timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env);
ppc40x_timer->decr_excp = decr_excp;
}

8
hw/ppc/ppc405_uc.c
View File

@ -1348,7 +1348,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
switch (addr) {
case 0x00:
/* Time base counter */
ret = muldiv64(qemu_get_clock_ns(vm_clock) + gpt->tb_offset,
ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
gpt->tb_freq, get_ticks_per_sec());
break;
case 0x10:
@ -1405,7 +1405,7 @@ static void ppc4xx_gpt_writel (void *opaque,
case 0x00:
/* Time base counter */
gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
- qemu_get_clock_ns(vm_clock);
- qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ppc4xx_gpt_compute_timer(gpt);
break;
case 0x10:
@ -1476,7 +1476,7 @@ static void ppc4xx_gpt_reset (void *opaque)
int i;
gpt = opaque;
qemu_del_timer(gpt->timer);
timer_del(gpt->timer);
gpt->oe = 0x00000000;
gpt->ol = 0x00000000;
gpt->im = 0x00000000;
@ -1497,7 +1497,7 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
for (i = 0; i < 5; i++) {
gpt->irqs[i] = irqs[i];
}
gpt->timer = qemu_new_timer_ns(vm_clock, &ppc4xx_gpt_cb, gpt);
gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
#ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif

10
hw/ppc/ppc_booke.c
View File

@ -136,7 +136,7 @@ static void booke_update_fixed_timer(CPUPPCState *env,
uint64_t period;
uint64_t now;
now = qemu_get_clock_ns(vm_clock);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
period = 1ULL << target_bit;
delta_tick = period - (tb & (period - 1));
@ -167,7 +167,7 @@ static void booke_update_fixed_timer(CPUPPCState *env,
(*next)++;
}
qemu_mod_timer(timer, *next);
timer_mod(timer, *next);
}
static void booke_decr_cb(void *opaque)
@ -303,12 +303,12 @@ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
tb_env->tb_freq = freq;
tb_env->decr_freq = freq;
tb_env->opaque = booke_timer;
tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &booke_decr_cb, cpu);
tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu);
booke_timer->fit_timer =
qemu_new_timer_ns(vm_clock, &booke_fit_cb, cpu);
timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu);
booke_timer->wdt_timer =
qemu_new_timer_ns(vm_clock, &booke_wdt_cb, cpu);
timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu);
ret = kvmppc_booke_watchdog_enable(cpu);

8
hw/ppc/spapr.c
View File

@ -789,7 +789,7 @@ static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr,
{
int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
int index = spapr->htab_save_index;
int64_t starttime = qemu_get_clock_ns(rt_clock);
int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
assert(spapr->htab_first_pass);
@ -820,7 +820,7 @@ static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr,
qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
HASH_PTE_SIZE_64 * n_valid);
if ((qemu_get_clock_ns(rt_clock) - starttime) > max_ns) {
if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
break;
}
}
@ -841,7 +841,7 @@ static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr,
int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
int examined = 0, sent = 0;
int index = spapr->htab_save_index;
int64_t starttime = qemu_get_clock_ns(rt_clock);
int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
assert(!spapr->htab_first_pass);
@ -886,7 +886,7 @@ static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr,
HASH_PTE_SIZE_64 * n_valid);
sent += index - chunkstart;
if (!final && (qemu_get_clock_ns(rt_clock) - starttime) > max_ns) {
if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
break;
}
}

28
hw/sd/sdhci.c
View File

@ -134,8 +134,8 @@ static void sdhci_raise_insertion_irq(void *opaque)
SDHCIState *s = (SDHCIState *)opaque;
if (s->norintsts & SDHC_NIS_REMOVE) {
qemu_mod_timer(s->insert_timer,
qemu_get_clock_ns(vm_clock) + SDHC_INSERTION_DELAY);
timer_mod(s->insert_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
} else {
s->prnsts = 0x1ff0000;
if (s->norintstsen & SDHC_NISEN_INSERT) {
@ -152,8 +152,8 @@ static void sdhci_insert_eject_cb(void *opaque, int irq, int level)
if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
/* Give target some time to notice card ejection */
qemu_mod_timer(s->insert_timer,
qemu_get_clock_ns(vm_clock) + SDHC_INSERTION_DELAY);
timer_mod(s->insert_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
} else {
if (level) {
s->prnsts = 0x1ff0000;
@ -186,8 +186,8 @@ static void sdhci_card_readonly_cb(void *opaque, int irq, int level)
static void sdhci_reset(SDHCIState *s)
{
qemu_del_timer(s->insert_timer);
qemu_del_timer(s->transfer_timer);
timer_del(s->insert_timer);
timer_del(s->transfer_timer);
/* Set all registers to 0. Capabilities registers are not cleared
* and assumed to always preserve their value, given to them during
* initialization */
@ -764,8 +764,8 @@ static void sdhci_do_adma(SDHCIState *s)
}
/* we have unfinished business - reschedule to continue ADMA */
qemu_mod_timer(s->transfer_timer,
qemu_get_clock_ns(vm_clock) + SDHC_TRANSFER_DELAY);
timer_mod(s->transfer_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY);
}
/* Perform data transfer according to controller configuration */
@ -1170,18 +1170,18 @@ static void sdhci_initfn(Object *obj)
s->ro_cb = qemu_allocate_irqs(sdhci_card_readonly_cb, s, 1)[0];
sd_set_cb(s->card, s->ro_cb, s->eject_cb);
s->insert_timer = qemu_new_timer_ns(vm_clock, sdhci_raise_insertion_irq, s);
s->transfer_timer = qemu_new_timer_ns(vm_clock, sdhci_do_data_transfer, s);
s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_do_data_transfer, s);
}
static void sdhci_uninitfn(Object *obj)
{
SDHCIState *s = SDHCI(obj);
qemu_del_timer(s->insert_timer);
qemu_free_timer(s->insert_timer);
qemu_del_timer(s->transfer_timer);
qemu_free_timer(s->transfer_timer);
timer_del(s->insert_timer);
timer_free(s->insert_timer);
timer_del(s->transfer_timer);
timer_free(s->transfer_timer);
qemu_free_irqs(&s->eject_cb);
qemu_free_irqs(&s->ro_cb);

24
hw/sparc64/sun4u.c
View File

@ -363,7 +363,7 @@ void cpu_put_timer(QEMUFile *f, CPUTimer *s)
qemu_put_be64s(f, &s->disabled_mask);
qemu_put_sbe64s(f, &s->clock_offset);
qemu_put_timer(f, s->qtimer);
timer_put(f, s->qtimer);
}
void cpu_get_timer(QEMUFile *f, CPUTimer *s)
@ -373,7 +373,7 @@ void cpu_get_timer(QEMUFile *f, CPUTimer *s)
qemu_get_be64s(f, &s->disabled_mask);
qemu_get_sbe64s(f, &s->clock_offset);
qemu_get_timer(f, s->qtimer);
timer_get(f, s->qtimer);
}
static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
@ -387,9 +387,9 @@ static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
timer->disabled_mask = disabled_mask;
timer->disabled = 1;
timer->clock_offset = qemu_get_clock_ns(vm_clock);
timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
timer->qtimer = qemu_new_timer_ns(vm_clock, cb, cpu);
timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
return timer;
}
@ -397,9 +397,9 @@ static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
static void cpu_timer_reset(CPUTimer *timer)
{
timer->disabled = 1;
timer->clock_offset = qemu_get_clock_ns(vm_clock);
timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
qemu_del_timer(timer->qtimer);
timer_del(timer->qtimer);
}
static void main_cpu_reset(void *opaque)
@ -495,7 +495,7 @@ void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
uint64_t real_count = count & ~timer->disabled_mask;
uint64_t disabled_bit = count & timer->disabled_mask;
int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) -
int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
cpu_to_timer_ticks(real_count, timer->frequency);
TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
@ -509,7 +509,7 @@ void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
uint64_t cpu_tick_get_count(CPUTimer *timer)
{
uint64_t real_count = timer_to_cpu_ticks(
qemu_get_clock_ns(vm_clock) - timer->clock_offset,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
timer->frequency);
TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
@ -524,7 +524,7 @@ uint64_t cpu_tick_get_count(CPUTimer *timer)
void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
{
int64_t now = qemu_get_clock_ns(vm_clock);
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
uint64_t real_limit = limit & ~timer->disabled_mask;
timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
@ -548,11 +548,11 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
if (!real_limit) {
TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
timer->name);
qemu_del_timer(timer->qtimer);
timer_del(timer->qtimer);
} else if (timer->disabled) {
qemu_del_timer(timer->qtimer);
timer_del(timer->qtimer);
} else {
qemu_mod_timer(timer->qtimer, expires);
timer_mod(timer->qtimer, expires);
}
}

12
hw/timer/arm_mptimer.c
View File

@ -81,10 +81,10 @@ static void timerblock_reload(TimerBlock *tb, int restart)
return;
}
if (restart) {
tb->tick = qemu_get_clock_ns(vm_clock);
tb->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
tb->tick += (int64_t)tb->count * timerblock_scale(tb);
qemu_mod_timer(tb->timer, tb->tick);
timer_mod(tb->timer, tb->tick);
}
static void timerblock_tick(void *opaque)
@ -113,7 +113,7 @@ static uint64_t timerblock_read(void *opaque, hwaddr addr,
return 0;
}
/* Slow and ugly, but hopefully won't happen too often. */
val = tb->tick - qemu_get_clock_ns(vm_clock);
val = tb->tick - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
val /= timerblock_scale(tb);
if (val < 0) {
val = 0;
@ -140,7 +140,7 @@ static void timerblock_write(void *opaque, hwaddr addr,
case 4: /* Counter. */
if ((tb->control & 1) && tb->count) {
/* Cancel the previous timer. */
qemu_del_timer(tb->timer);
timer_del(tb->timer);
}
tb->count = value;
if (tb->control & 1) {
@ -211,7 +211,7 @@ static void timerblock_reset(TimerBlock *tb)
tb->status = 0;
tb->tick = 0;
if (tb->timer) {
qemu_del_timer(tb->timer);
timer_del(tb->timer);
}
}
@ -248,7 +248,7 @@ static int arm_mptimer_init(SysBusDevice *dev)
sysbus_init_mmio(dev, &s->iomem);
for (i = 0; i < s->num_cpu; i++) {
TimerBlock *tb = &s->timerblock[i];
tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);
tb->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, timerblock_tick, tb);
sysbus_init_irq(dev, &tb->irq);
memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb,
"arm_mptimer_timerblock", 0x20);

1
hw/timer/arm_timer.c
View File

@ -12,6 +12,7 @@
#include "qemu-common.h"
#include "hw/qdev.h"
#include "hw/ptimer.h"
#include "qemu/main-loop.h"
/* Common timer implementation. */

6
hw/timer/cadence_ttc.c
View File

@ -172,7 +172,7 @@ static void cadence_timer_run(CadenceTimerState *s)
event_interval = next_value - (int64_t)s->reg_value;
event_interval = (event_interval < 0) ? -event_interval : event_interval;
qemu_mod_timer(s->timer, s->cpu_time +
timer_mod(s->timer, s->cpu_time +
cadence_timer_get_ns(s, event_interval));
}
@ -184,7 +184,7 @@ static void cadence_timer_sync(CadenceTimerState *s)
(int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;
uint64_t old_time = s->cpu_time;
s->cpu_time = qemu_get_clock_ns(vm_clock);
s->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
DB_PRINT("cpu time: %lld ns\n", (long long)old_time);
if (!s->cpu_time_valid || old_time == s->cpu_time) {
@ -401,7 +401,7 @@ static void cadence_timer_init(uint32_t freq, CadenceTimerState *s)
cadence_timer_reset(s);
s->timer = qemu_new_timer_ns(vm_clock, cadence_timer_tick, s);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cadence_timer_tick, s);
}
static int cadence_ttc_init(SysBusDevice *dev)

2
hw/timer/etraxfs_timer.c
View File

@ -93,7 +93,7 @@ timer_read(void *opaque, hwaddr addr, unsigned int size)
r = ptimer_get_count(t->ptimer_t1);
break;
case R_TIME:
r = qemu_get_clock_ns(vm_clock) / 10;
r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
break;
case RW_INTR_MASK:
r = t->rw_intr_mask;

3
hw/timer/exynos4210_mct.c
View File

@ -54,6 +54,7 @@
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h"
#include "qemu-common.h"
#include "hw/ptimer.h"
@ -905,7 +906,7 @@ static void exynos4210_ltick_event(void *opaque)
/* raise interrupt if enabled */
if (s->reg.int_enb & L_INT_INTENB_ICNTEIE) {
#ifdef DEBUG_MCT
time2[s->id] = qemu_get_clock_ns(vm_clock);
time2[s->id] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
DPRINTF("local timer[%d] IRQ: %llx\n", s->id,
time2[s->id] - time1[s->id]);
time1[s->id] = time2[s->id];

1
hw/timer/exynos4210_pwm.c
View File

@ -23,6 +23,7 @@
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "qemu-common.h"
#include "qemu/main-loop.h"
#include "hw/ptimer.h"
#include "hw/arm/exynos4210.h"

2
hw/timer/grlib_gptimer.c
View File

@ -25,6 +25,8 @@
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h"
#include "trace.h"

20
hw/timer/hpet.c
View File

@ -152,7 +152,7 @@ static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
static uint64_t hpet_get_ticks(HPETState *s)
{
return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset);
return ns_to_ticks(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hpet_offset);
}
/*
@ -233,7 +233,7 @@ static int hpet_post_load(void *opaque, int version_id)
HPETState *s = opaque;
/* Recalculate the offset between the main counter and guest time */
s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
/* Push number of timers into capability returned via HPET_ID */
s->capability &= ~HPET_ID_NUM_TIM_MASK;
@ -332,12 +332,12 @@ static void hpet_timer(void *opaque)
}
}
diff = hpet_calculate_diff(t, cur_tick);
qemu_mod_timer(t->qemu_timer,
qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
timer_mod(t->qemu_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff));
} else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
if (t->wrap_flag) {
diff = hpet_calculate_diff(t, cur_tick);
qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) +
timer_mod(t->qemu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(int64_t)ticks_to_ns(diff));
t->wrap_flag = 0;
}
@ -365,13 +365,13 @@ static void hpet_set_timer(HPETTimer *t)
t->wrap_flag = 1;
}
}
qemu_mod_timer(t->qemu_timer,
qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
timer_mod(t->qemu_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff));
}
static void hpet_del_timer(HPETTimer *t)
{
qemu_del_timer(t->qemu_timer);
timer_del(t->qemu_timer);
update_irq(t, 0);
}
@ -567,7 +567,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
/* Enable main counter and interrupt generation. */
s->hpet_offset =
ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
for (i = 0; i < s->num_timers; i++) {
if ((&s->timer[i])->cmp != ~0ULL) {
hpet_set_timer(&s->timer[i]);
@ -726,7 +726,7 @@ static void hpet_realize(DeviceState *dev, Error **errp)
}
for (i = 0; i < HPET_MAX_TIMERS; i++) {
timer = &s->timer[i];
timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer);
timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer);
timer->tn = i;
timer->state = s;
}

26
hw/timer/i8254.c
View File

@ -51,7 +51,7 @@ static int pit_get_count(PITChannelState *s)
uint64_t d;
int counter;
d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ,
get_ticks_per_sec());
switch(s->mode) {
case 0:
@ -85,7 +85,7 @@ static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
case 5:
if (sc->gate < val) {
/* restart counting on rising edge */
sc->count_load_time = qemu_get_clock_ns(vm_clock);
sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
pit_irq_timer_update(sc, sc->count_load_time);
}
break;
@ -93,7 +93,7 @@ static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
case 3:
if (sc->gate < val) {
/* restart counting on rising edge */
sc->count_load_time = qemu_get_clock_ns(vm_clock);
sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
pit_irq_timer_update(sc, sc->count_load_time);
}
/* XXX: disable/enable counting */
@ -106,7 +106,7 @@ static inline void pit_load_count(PITChannelState *s, int val)
{
if (val == 0)
val = 0x10000;
s->count_load_time = qemu_get_clock_ns(vm_clock);
s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->count = val;
pit_irq_timer_update(s, s->count_load_time);
}
@ -143,7 +143,7 @@ static void pit_ioport_write(void *opaque, hwaddr addr,
/* XXX: add BCD and null count */
s->status =
(pit_get_out(s,
qemu_get_clock_ns(vm_clock)) << 7) |
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) << 7) |
(s->rw_mode << 4) |
(s->mode << 1) |
s->bcd;
@ -260,9 +260,9 @@ static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
#endif
s->next_transition_time = expire_time;
if (expire_time != -1)
qemu_mod_timer(s->irq_timer, expire_time);
timer_mod(s->irq_timer, expire_time);
else
qemu_del_timer(s->irq_timer);
timer_del(s->irq_timer);
}
static void pit_irq_timer(void *opaque)
@ -281,7 +281,7 @@ static void pit_reset(DeviceState *dev)
s = &pit->channels[0];
if (!s->irq_disabled) {
qemu_mod_timer(s->irq_timer, s->next_transition_time);
timer_mod(s->irq_timer, s->next_transition_time);
}
}
@ -294,10 +294,10 @@ static void pit_irq_control(void *opaque, int n, int enable)
if (enable) {
s->irq_disabled = 0;
pit_irq_timer_update(s, qemu_get_clock_ns(vm_clock));
pit_irq_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
} else {
s->irq_disabled = 1;
qemu_del_timer(s->irq_timer);
timer_del(s->irq_timer);
}
}
@ -316,9 +316,9 @@ static void pit_post_load(PITCommonState *s)
PITChannelState *sc = &s->channels[0];
if (sc->next_transition_time != -1) {
qemu_mod_timer(sc->irq_timer, sc->next_transition_time);
timer_mod(sc->irq_timer, sc->next_transition_time);
} else {
qemu_del_timer(sc->irq_timer);
timer_del(sc->irq_timer);
}
}
@ -330,7 +330,7 @@ static void pit_realizefn(DeviceState *dev, Error **err)
s = &pit->channels[0];
/* the timer 0 is connected to an IRQ */
s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s);
qdev_init_gpio_out(dev, &s->irq, 1);
memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops,

4
hw/timer/i8254_common.c
View File

@ -136,7 +136,7 @@ void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
info->gate = sc->gate;
info->mode = sc->mode;
info->initial_count = sc->count;
info->out = pit_get_out(sc, qemu_get_clock_ns(vm_clock));
info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}
void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info)
@ -157,7 +157,7 @@ void pit_reset_common(PITCommonState *pit)
s = &pit->channels[i];
s->mode = 3;
s->gate = (i != 2);
s->count_load_time = qemu_get_clock_ns(vm_clock);
s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->count = 0x10000;
if (i == 0 && !s->irq_disabled) {
s->next_transition_time =

1
hw/timer/imx_epit.c
View File

@ -18,6 +18,7 @@
#include "hw/ptimer.h"
#include "hw/sysbus.h"
#include "hw/arm/imx.h"
#include "qemu/main-loop.h"
#define TYPE_IMX_EPIT "imx.epit"

1
hw/timer/imx_gpt.c
View File

@ -18,6 +18,7 @@
#include "hw/ptimer.h"
#include "hw/sysbus.h"
#include "hw/arm/imx.h"
#include "qemu/main-loop.h"
#define TYPE_IMX_GPT "imx.gpt"

1
hw/timer/lm32_timer.c
View File

@ -27,6 +27,7 @@
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#define DEFAULT_FREQUENCY (50*1000000)

18
hw/timer/m48t59.c
View File

@ -137,7 +137,7 @@ static void alarm_cb (void *opaque)
/* Repeat once a second */
next_time = 1;
}
qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) +
timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
next_time * 1000);
qemu_set_irq(NVRAM->IRQ, 0);
}
@ -146,10 +146,10 @@ static void set_alarm(M48t59State *NVRAM)
{
int diff;
if (NVRAM->alrm_timer != NULL) {
qemu_del_timer(NVRAM->alrm_timer);
timer_del(NVRAM->alrm_timer);
diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
if (diff > 0)
qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
timer_mod(NVRAM->alrm_timer, diff * 1000);
}
}
@ -188,10 +188,10 @@ static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
NVRAM->buffer[0x1FF0] &= ~0x80;
if (NVRAM->wd_timer != NULL) {
qemu_del_timer(NVRAM->wd_timer);
timer_del(NVRAM->wd_timer);
if (value != 0) {
interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
((interval * 1000) >> 4));
}
}
@ -609,10 +609,10 @@ static void m48t59_reset_common(M48t59State *NVRAM)
NVRAM->addr = 0;
NVRAM->lock = 0;
if (NVRAM->alrm_timer != NULL)
qemu_del_timer(NVRAM->alrm_timer);
timer_del(NVRAM->alrm_timer);
if (NVRAM->wd_timer != NULL)
qemu_del_timer(NVRAM->wd_timer);
timer_del(NVRAM->wd_timer);
}
static void m48t59_reset_isa(DeviceState *d)
@ -700,8 +700,8 @@ static void m48t59_realize_common(M48t59State *s, Error **errp)
{
s->buffer = g_malloc0(s->size);
if (s->model == 59) {
s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s);
s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
}
qemu_get_timedate(&s->alarm, 0);

50
hw/timer/mc146818rtc.c
View File

@ -102,7 +102,7 @@ static inline bool rtc_running(RTCState *s)
static uint64_t get_guest_rtc_ns(RTCState *s)
{
uint64_t guest_rtc;
uint64_t guest_clock = qemu_get_clock_ns(rtc_clock);
uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);
guest_rtc = s->base_rtc * NSEC_PER_SEC
+ guest_clock - s->last_update + s->offset;
@ -113,13 +113,13 @@ static uint64_t get_guest_rtc_ns(RTCState *s)
static void rtc_coalesced_timer_update(RTCState *s)
{
if (s->irq_coalesced == 0) {
qemu_del_timer(s->coalesced_timer);
timer_del(s->coalesced_timer);
} else {
/* divide each RTC interval to 2 - 8 smaller intervals */
int c = MIN(s->irq_coalesced, 7) + 1;
int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
int64_t next_clock = qemu_clock_get_ns(rtc_clock) +
muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
qemu_mod_timer(s->coalesced_timer, next_clock);
timer_mod(s->coalesced_timer, next_clock);
}
}
@ -169,12 +169,12 @@ static void periodic_timer_update(RTCState *s, int64_t current_time)
next_irq_clock = (cur_clock & ~(period - 1)) + period;
s->next_periodic_time =
muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
timer_mod(s->periodic_timer, s->next_periodic_time);
} else {
#ifdef TARGET_I386
s->irq_coalesced = 0;
#endif
qemu_del_timer(s->periodic_timer);
timer_del(s->periodic_timer);
}
}
@ -222,23 +222,23 @@ static void check_update_timer(RTCState *s)
* from occurring, because the time of day is not updated.
*/
if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
qemu_del_timer(s->update_timer);
timer_del(s->update_timer);
return;
}
if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
qemu_del_timer(s->update_timer);
timer_del(s->update_timer);
return;
}
if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
(s->cmos_data[RTC_REG_C] & REG_C_AF)) {
qemu_del_timer(s->update_timer);
timer_del(s->update_timer);
return;
}
guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC;
/* if UF is clear, reprogram to next second */
next_update_time = qemu_get_clock_ns(rtc_clock)
next_update_time = qemu_clock_get_ns(rtc_clock)
+ NSEC_PER_SEC - guest_nsec;
/* Compute time of next alarm. One second is already accounted
@ -252,8 +252,8 @@ static void check_update_timer(RTCState *s)
* the alarm time. */
next_update_time = s->next_alarm_time;
}
if (next_update_time != qemu_timer_expire_time_ns(s->update_timer)) {
qemu_mod_timer(s->update_timer, next_update_time);
if (next_update_time != timer_expire_time_ns(s->update_timer)) {
timer_mod(s->update_timer, next_update_time);
}
}
@ -371,7 +371,7 @@ static void rtc_update_timer(void *opaque)
rtc_update_time(s);
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) {
if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) {
irqs |= REG_C_AF;
if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
@ -445,7 +445,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr,
/* UIP bit is read only */
s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
(s->cmos_data[RTC_REG_A] & REG_A_UIP);
periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
check_update_timer(s);
break;
case RTC_REG_B:
@ -475,7 +475,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr,
qemu_irq_lower(s->irq);
}
s->cmos_data[RTC_REG_B] = data;
periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
check_update_timer(s);
break;
case RTC_REG_C:
@ -535,7 +535,7 @@ static void rtc_set_time(RTCState *s)
rtc_get_time(s, &tm);
s->base_rtc = mktimegm(&tm);
s->last_update = qemu_get_clock_ns(rtc_clock);
s->last_update = qemu_clock_get_ns(rtc_clock);
rtc_change_mon_event(&tm);
}
@ -587,10 +587,11 @@ static int update_in_progress(RTCState *s)
if (!rtc_running(s)) {
return 0;
}
if (qemu_timer_pending(s->update_timer)) {
int64_t next_update_time = qemu_timer_expire_time_ns(s->update_timer);
if (timer_pending(s->update_timer)) {
int64_t next_update_time = timer_expire_time_ns(s->update_timer);
/* Latch UIP until the timer expires. */
if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) {
if (qemu_clock_get_ns(rtc_clock) >=
(next_update_time - UIP_HOLD_LENGTH)) {
s->cmos_data[RTC_REG_A] |= REG_A_UIP;
return 1;
}
@ -695,7 +696,7 @@ static void rtc_set_date_from_host(ISADevice *dev)
qemu_get_timedate(&tm, 0);
s->base_rtc = mktimegm(&tm);
s->last_update = qemu_get_clock_ns(rtc_clock);
s->last_update = qemu_clock_get_ns(rtc_clock);
s->offset = 0;
/* set the CMOS date */
@ -843,7 +844,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
switch (s->lost_tick_policy) {
case LOST_TICK_SLEW:
s->coalesced_timer =
qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
break;
case LOST_TICK_DISCARD:
break;
@ -853,12 +854,13 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
}
#endif
s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s);
s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
check_update_timer(s);
s->clock_reset_notifier.notify = rtc_notify_clock_reset;
qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
qemu_clock_register_reset_notifier(QEMU_CLOCK_REALTIME,
&s->clock_reset_notifier);
s->suspend_notifier.notify = rtc_notify_suspend;
qemu_register_suspend_notifier(&s->suspend_notifier);

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