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64bit MIPS FPUs have 32 registers.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2610 c046a42c-6fe2-441c-8c8c-71466251a162
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ths 2007-04-05 23:14:23 +00:00
parent fb82fea064
commit f7cfb2a176
1 changed files with 1 additions and 2 deletions
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3
target-mips/cpu.h
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@ -62,9 +62,8 @@ struct CPUMIPSState {
target_ulong t2;
#endif
target_ulong HI, LO;
uint32_t DCR; /* ? */
/* Floating point registers */
fpr_t fpr[16];
fpr_t fpr[32];
#define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
#define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
#define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])