Add an ISA bus version of m48t59
Many thanks to Gerd Hoffmann for finding and fixing a bug in the initial version. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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042eb37a04
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95
hw/m48t59.c
95
hw/m48t59.c
@ -26,6 +26,7 @@
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "sysbus.h"
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#include "isa.h"
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//#define DEBUG_NVRAM
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@ -41,7 +42,6 @@
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* PPC platform there is also a nvram lock function.
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*/
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struct m48t59_t {
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SysBusDevice busdev;
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/* Model parameters */
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uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
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/* Hardware parameters */
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@ -61,6 +61,16 @@ struct m48t59_t {
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uint8_t *buffer;
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};
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typedef struct M48t59ISAState {
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ISADevice busdev;
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m48t59_t state;
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} M48t59ISAState;
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typedef struct M48t59SysBusState {
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SysBusDevice busdev;
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m48t59_t state;
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} M48t59SysBusState;
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/* Fake timer functions */
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/* Generic helpers for BCD */
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static inline uint8_t toBCD (uint8_t value)
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@ -620,7 +630,7 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
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{
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DeviceState *dev;
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SysBusDevice *s;
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m48t59_t *d;
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M48t59SysBusState *d;
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dev = qdev_create(NULL, "m48t59");
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qdev_prop_set_uint32(dev, "type", type);
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@ -637,22 +647,36 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
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sysbus_mmio_map(s, 0, mem_base);
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}
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d = FROM_SYSBUS(m48t59_t, s);
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d = FROM_SYSBUS(M48t59SysBusState, s);
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return d;
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return &d->state;
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}
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static int m48t59_init1(SysBusDevice *dev)
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m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
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{
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m48t59_t *s = FROM_SYSBUS(m48t59_t, dev);
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int mem_index;
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M48t59ISAState *d;
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ISADevice *dev;
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m48t59_t *s;
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dev = isa_create("m48t59_isa");
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qdev_prop_set_uint32(&dev->qdev, "type", type);
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qdev_prop_set_uint32(&dev->qdev, "size", size);
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qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
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qdev_init(&dev->qdev);
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d = DO_UPCAST(M48t59ISAState, busdev, dev);
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s = &d->state;
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if (io_base != 0) {
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register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
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register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
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}
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return s;
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}
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static void m48t59_init_common(m48t59_t *s)
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{
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s->buffer = qemu_mallocz(s->size);
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sysbus_init_irq(dev, &s->IRQ);
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mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
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sysbus_init_mmio(dev, s->size, mem_index);
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if (s->type == 59) {
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s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
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s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
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@ -661,17 +685,55 @@ static int m48t59_init1(SysBusDevice *dev)
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qemu_register_reset(m48t59_reset, s);
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register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s);
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}
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static int m48t59_init_isa1(ISADevice *dev)
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{
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M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
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m48t59_t *s = &d->state;
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isa_init_irq(dev, &s->IRQ, 8);
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m48t59_init_common(s);
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return 0;
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}
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static int m48t59_init1(SysBusDevice *dev)
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{
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M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
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m48t59_t *s = &d->state;
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int mem_index;
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sysbus_init_irq(dev, &s->IRQ);
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mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
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sysbus_init_mmio(dev, s->size, mem_index);
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m48t59_init_common(s);
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return 0;
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}
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static ISADeviceInfo m48t59_isa_info = {
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.init = m48t59_init_isa1,
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.qdev.name = "m48t59_isa",
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.qdev.size = sizeof(M48t59ISAState),
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.qdev.no_user = 1,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
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DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1),
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DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static SysBusDeviceInfo m48t59_info = {
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.init = m48t59_init1,
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.qdev.name = "m48t59",
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.qdev.size = sizeof(m48t59_t),
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.qdev.size = sizeof(M48t59SysBusState),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("size", m48t59_t, size, -1),
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DEFINE_PROP_UINT32("type", m48t59_t, type, -1),
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DEFINE_PROP_HEX32( "io_base", m48t59_t, io_base, 0),
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DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
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DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1),
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DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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@ -679,6 +741,7 @@ static SysBusDeviceInfo m48t59_info = {
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static void m48t59_register_devices(void)
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{
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sysbus_register_withprop(&m48t59_info);
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isa_qdev_register(&m48t59_isa_info);
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}
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device_init(m48t59_register_devices)
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@ -34,6 +34,7 @@ typedef struct m48t59_t m48t59_t;
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void m48t59_write (void *private, uint32_t addr, uint32_t val);
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uint32_t m48t59_read (void *private, uint32_t addr);
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void m48t59_toggle_lock (void *private, int lock);
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m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type);
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m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
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uint32_t io_base, uint16_t size,
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int type);
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@ -623,8 +623,7 @@ static void sun4uv_init(ram_addr_t RAM_size,
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fd[i] = dinfo ? dinfo->bdrv : NULL;
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}
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fdctrl_init_isa(fd);
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/* FIXME: wire up interrupts. */
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nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
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nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
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initrd_size = 0;
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kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
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