tcg/aarch64: Support raising sigbus for user-only
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
b1ee3c6725
commit
f85ab3d2e5
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@ -10,6 +10,7 @@
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* See the COPYING file in the top-level directory for details.
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*/
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#include "../tcg-ldst.c.inc"
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#include "../tcg-pool.c.inc"
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#include "qemu/bitops.h"
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@ -443,6 +444,7 @@ typedef enum {
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I3404_ANDI = 0x12000000,
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I3404_ORRI = 0x32000000,
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I3404_EORI = 0x52000000,
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I3404_ANDSI = 0x72000000,
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/* Move wide immediate instructions. */
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I3405_MOVN = 0x12800000,
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@ -1328,8 +1330,9 @@ static void tcg_out_goto_long(TCGContext *s, const tcg_insn_unit *target)
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if (offset == sextract64(offset, 0, 26)) {
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tcg_out_insn(s, 3206, B, offset);
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} else {
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target);
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tcg_out_insn(s, 3207, BR, TCG_REG_TMP);
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/* Choose X9 as a call-clobbered non-LR temporary. */
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X9, (intptr_t)target);
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tcg_out_insn(s, 3207, BR, TCG_REG_X9);
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}
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}
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@ -1541,9 +1544,14 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
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}
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}
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#ifdef CONFIG_SOFTMMU
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#include "../tcg-ldst.c.inc"
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static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target)
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{
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ptrdiff_t offset = tcg_pcrel_diff(s, target);
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tcg_debug_assert(offset == sextract64(offset, 0, 21));
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tcg_out_insn(s, 3406, ADR, rd, offset);
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}
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#ifdef CONFIG_SOFTMMU
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/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
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* MemOpIdx oi, uintptr_t ra)
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*/
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@ -1577,13 +1585,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = {
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#endif
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};
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static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target)
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{
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ptrdiff_t offset = tcg_pcrel_diff(s, target);
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tcg_debug_assert(offset == sextract64(offset, 0, 21));
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tcg_out_insn(s, 3406, ADR, rd, offset);
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}
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static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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MemOpIdx oi = lb->oi;
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@ -1714,15 +1715,58 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
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tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
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}
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#else
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static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg,
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unsigned a_bits)
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{
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unsigned a_mask = (1 << a_bits) - 1;
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TCGLabelQemuLdst *label = new_ldst_label(s);
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label->is_ld = is_ld;
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label->addrlo_reg = addr_reg;
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/* tst addr, #mask */
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tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask);
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label->label_ptr[0] = s->code_ptr;
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/* b.ne slow_path */
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tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
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label->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
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{
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if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
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return false;
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}
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tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_X1, l->addrlo_reg);
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
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/* "Tail call" to the helper, with the return address back inline. */
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tcg_out_adr(s, TCG_REG_LR, l->raddr);
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tcg_out_goto_long(s, (const void *)(l->is_ld ? helper_unaligned_ld
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: helper_unaligned_st));
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return true;
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}
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static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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{
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return tcg_out_fail_alignment(s, l);
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}
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static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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{
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return tcg_out_fail_alignment(s, l);
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}
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#endif /* CONFIG_SOFTMMU */
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static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
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TCGReg data_r, TCGReg addr_r,
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TCGType otype, TCGReg off_r)
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{
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/* Byte swapping is left to middle-end expansion. */
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tcg_debug_assert((memop & MO_BSWAP) == 0);
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switch (memop & MO_SSIZE) {
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case MO_UB:
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tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r);
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@ -1756,9 +1800,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
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TCGReg data_r, TCGReg addr_r,
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TCGType otype, TCGReg off_r)
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{
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/* Byte swapping is left to middle-end expansion. */
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tcg_debug_assert((memop & MO_BSWAP) == 0);
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switch (memop & MO_SIZE) {
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case MO_8:
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tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);
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@ -1782,6 +1823,10 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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{
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MemOp memop = get_memop(oi);
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const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
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/* Byte swapping is left to middle-end expansion. */
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tcg_debug_assert((memop & MO_BSWAP) == 0);
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#ifdef CONFIG_SOFTMMU
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unsigned mem_index = get_mmuidx(oi);
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tcg_insn_unit *label_ptr;
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@ -1792,6 +1837,10 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
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s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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unsigned a_bits = get_alignment_bits(memop);
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if (a_bits) {
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tcg_out_test_alignment(s, true, addr_reg, a_bits);
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}
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if (USE_GUEST_BASE) {
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tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
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TCG_REG_GUEST_BASE, otype, addr_reg);
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@ -1807,6 +1856,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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{
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MemOp memop = get_memop(oi);
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const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
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/* Byte swapping is left to middle-end expansion. */
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tcg_debug_assert((memop & MO_BSWAP) == 0);
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#ifdef CONFIG_SOFTMMU
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unsigned mem_index = get_mmuidx(oi);
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tcg_insn_unit *label_ptr;
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@ -1817,6 +1870,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
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data_reg, addr_reg, s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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unsigned a_bits = get_alignment_bits(memop);
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if (a_bits) {
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tcg_out_test_alignment(s, false, addr_reg, a_bits);
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}
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if (USE_GUEST_BASE) {
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tcg_out_qemu_st_direct(s, memop, data_reg,
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TCG_REG_GUEST_BASE, otype, addr_reg);
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@ -151,9 +151,7 @@ typedef enum {
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#ifdef CONFIG_SOFTMMU
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#define TCG_TARGET_NEED_LDST_LABELS
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#endif
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#define TCG_TARGET_NEED_POOL_LABELS
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#endif /* AARCH64_TCG_TARGET_H */
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