More detabification
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3338 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
81732d1926
commit
f930d07eda
16
hw/apb_pci.c
16
hw/apb_pci.c
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@ -70,7 +70,7 @@ static CPUReadMemoryFunc *pci_apb_config_read[] = {
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};
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};
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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uint32_t val)
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{
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{
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//PCIBus *s = opaque;
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//PCIBus *s = opaque;
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@ -80,14 +80,14 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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case 0x18: // AFAR
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case 0x18: // AFAR
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case 0x20: // Diagnostic
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case 0x20: // Diagnostic
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case 0x28: // Target address space
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case 0x28: // Target address space
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// XXX
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// XXX
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default:
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default:
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break;
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break;
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}
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}
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}
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}
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static uint32_t apb_config_readl (void *opaque,
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static uint32_t apb_config_readl (void *opaque,
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target_phys_addr_t addr)
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target_phys_addr_t addr)
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{
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{
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//PCIBus *s = opaque;
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//PCIBus *s = opaque;
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uint32_t val;
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uint32_t val;
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@ -98,10 +98,10 @@ static uint32_t apb_config_readl (void *opaque,
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case 0x18: // AFAR
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case 0x18: // AFAR
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case 0x20: // Diagnostic
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case 0x20: // Diagnostic
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case 0x28: // Target address space
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case 0x28: // Target address space
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// XXX
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// XXX
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default:
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default:
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val = 0;
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val = 0;
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break;
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break;
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}
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}
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return val;
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return val;
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}
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}
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@ -222,7 +222,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
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pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
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pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
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pci_apb_config_write, s);
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pci_apb_config_write, s);
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apb_config = cpu_register_io_memory(0, apb_config_read,
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apb_config = cpu_register_io_memory(0, apb_config_read,
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apb_config_write, s);
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apb_config_write, s);
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pci_mem_data = cpu_register_io_memory(0, pci_apb_read,
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pci_mem_data = cpu_register_io_memory(0, pci_apb_read,
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pci_apb_write, s);
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pci_apb_write, s);
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pci_ioport = cpu_register_io_memory(0, pci_apb_ioread,
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pci_ioport = cpu_register_io_memory(0, pci_apb_ioread,
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@ -79,11 +79,11 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
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break;
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break;
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}
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}
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DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
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DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
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break;
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break;
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default:
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default:
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ret = s->regs[saddr];
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ret = s->regs[saddr];
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DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
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DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
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break;
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break;
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}
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}
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return ret;
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return ret;
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}
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}
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@ -122,7 +122,7 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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break;
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break;
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default:
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default:
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s->regs[saddr] = val;
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s->regs[saddr] = val;
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break;
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break;
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}
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}
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}
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}
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158
hw/esp.c
158
hw/esp.c
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@ -107,9 +107,9 @@ static int get_cmd(ESPState *s, uint8_t *buf)
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if (s->dma) {
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if (s->dma) {
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espdma_memory_read(s->dma_opaque, buf, dmalen);
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espdma_memory_read(s->dma_opaque, buf, dmalen);
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} else {
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} else {
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buf[0] = 0;
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buf[0] = 0;
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memcpy(&buf[1], s->ti_buf, dmalen);
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memcpy(&buf[1], s->ti_buf, dmalen);
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dmalen++;
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dmalen++;
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}
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}
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s->ti_size = 0;
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s->ti_size = 0;
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@ -124,11 +124,11 @@ static int get_cmd(ESPState *s, uint8_t *buf)
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if (target >= MAX_DISKS || !s->scsi_dev[target]) {
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if (target >= MAX_DISKS || !s->scsi_dev[target]) {
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// No such drive
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// No such drive
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s->rregs[4] = STAT_IN;
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s->rregs[4] = STAT_IN;
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s->rregs[5] = INTR_DC;
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s->rregs[5] = INTR_DC;
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s->rregs[6] = SEQ_0;
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s->rregs[6] = SEQ_0;
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qemu_irq_raise(s->irq);
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qemu_irq_raise(s->irq);
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return 0;
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return 0;
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}
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}
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s->current_dev = s->scsi_dev[target];
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s->current_dev = s->scsi_dev[target];
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return dmalen;
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return dmalen;
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@ -190,14 +190,14 @@ static void write_response(ESPState *s)
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s->ti_buf[1] = 0;
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s->ti_buf[1] = 0;
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if (s->dma) {
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if (s->dma) {
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espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
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espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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s->rregs[6] = SEQ_CD;
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} else {
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} else {
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s->ti_size = 2;
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s->ti_size = 2;
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s->ti_rptr = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->ti_wptr = 0;
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s->rregs[7] = 2;
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s->rregs[7] = 2;
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}
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}
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qemu_irq_raise(s->irq);
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qemu_irq_raise(s->irq);
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}
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}
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@ -359,9 +359,9 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
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DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
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DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
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switch (saddr) {
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switch (saddr) {
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case 2:
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case 2:
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// FIFO
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// FIFO
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if (s->ti_size > 0) {
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if (s->ti_size > 0) {
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s->ti_size--;
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s->ti_size--;
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if ((s->rregs[4] & 6) == 0) {
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if ((s->rregs[4] & 6) == 0) {
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/* Data in/out. */
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/* Data in/out. */
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fprintf(stderr, "esp: PIO data read not implemented\n");
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fprintf(stderr, "esp: PIO data read not implemented\n");
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@ -370,20 +370,20 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
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s->rregs[2] = s->ti_buf[s->ti_rptr++];
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s->rregs[2] = s->ti_buf[s->ti_rptr++];
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}
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}
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qemu_irq_raise(s->irq);
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qemu_irq_raise(s->irq);
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}
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}
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if (s->ti_size == 0) {
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if (s->ti_size == 0) {
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s->ti_rptr = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->ti_wptr = 0;
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}
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}
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break;
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break;
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case 5:
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case 5:
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// interrupt
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// interrupt
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// Clear interrupt/error status bits
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// Clear interrupt/error status bits
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s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
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s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
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qemu_irq_lower(s->irq);
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qemu_irq_lower(s->irq);
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break;
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break;
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default:
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default:
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break;
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break;
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}
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}
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return s->rregs[saddr];
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return s->rregs[saddr];
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}
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}
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@ -401,7 +401,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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s->rregs[4] &= ~STAT_TC;
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s->rregs[4] &= ~STAT_TC;
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break;
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break;
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case 2:
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case 2:
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// FIFO
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// FIFO
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if (s->do_cmd) {
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if (s->do_cmd) {
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s->cmdbuf[s->cmdlen++] = val & 0xff;
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s->cmdbuf[s->cmdlen++] = val & 0xff;
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} else if ((s->rregs[4] & 6) == 0) {
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} else if ((s->rregs[4] & 6) == 0) {
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@ -413,73 +413,73 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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s->ti_size++;
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s->ti_size++;
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s->ti_buf[s->ti_wptr++] = val & 0xff;
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s->ti_buf[s->ti_wptr++] = val & 0xff;
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}
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}
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break;
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break;
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case 3:
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case 3:
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s->rregs[saddr] = val;
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s->rregs[saddr] = val;
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// Command
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// Command
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if (val & 0x80) {
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if (val & 0x80) {
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s->dma = 1;
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s->dma = 1;
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/* Reload DMA counter. */
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/* Reload DMA counter. */
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s->rregs[0] = s->wregs[0];
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s->rregs[0] = s->wregs[0];
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s->rregs[1] = s->wregs[1];
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s->rregs[1] = s->wregs[1];
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} else {
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} else {
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s->dma = 0;
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s->dma = 0;
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}
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}
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switch(val & 0x7f) {
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switch(val & 0x7f) {
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case 0:
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case 0:
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DPRINTF("NOP (%2.2x)\n", val);
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DPRINTF("NOP (%2.2x)\n", val);
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break;
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break;
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case 1:
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case 1:
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DPRINTF("Flush FIFO (%2.2x)\n", val);
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DPRINTF("Flush FIFO (%2.2x)\n", val);
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//s->ti_size = 0;
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//s->ti_size = 0;
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s->rregs[5] = INTR_FC;
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s->rregs[5] = INTR_FC;
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s->rregs[6] = 0;
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s->rregs[6] = 0;
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break;
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break;
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case 2:
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case 2:
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DPRINTF("Chip reset (%2.2x)\n", val);
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DPRINTF("Chip reset (%2.2x)\n", val);
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esp_reset(s);
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esp_reset(s);
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break;
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break;
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case 3:
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case 3:
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DPRINTF("Bus reset (%2.2x)\n", val);
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DPRINTF("Bus reset (%2.2x)\n", val);
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s->rregs[5] = INTR_RST;
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s->rregs[5] = INTR_RST;
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if (!(s->wregs[8] & 0x40)) {
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if (!(s->wregs[8] & 0x40)) {
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qemu_irq_raise(s->irq);
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qemu_irq_raise(s->irq);
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}
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}
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break;
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break;
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case 0x10:
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case 0x10:
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handle_ti(s);
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handle_ti(s);
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break;
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break;
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case 0x11:
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case 0x11:
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DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
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DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
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write_response(s);
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write_response(s);
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break;
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break;
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case 0x12:
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case 0x12:
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DPRINTF("Message Accepted (%2.2x)\n", val);
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DPRINTF("Message Accepted (%2.2x)\n", val);
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write_response(s);
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write_response(s);
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s->rregs[5] = INTR_DC;
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s->rregs[5] = INTR_DC;
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s->rregs[6] = 0;
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s->rregs[6] = 0;
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break;
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break;
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case 0x1a:
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case 0x1a:
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DPRINTF("Set ATN (%2.2x)\n", val);
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DPRINTF("Set ATN (%2.2x)\n", val);
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break;
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break;
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case 0x42:
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case 0x42:
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DPRINTF("Set ATN (%2.2x)\n", val);
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DPRINTF("Set ATN (%2.2x)\n", val);
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handle_satn(s);
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handle_satn(s);
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break;
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break;
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case 0x43:
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case 0x43:
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DPRINTF("Set ATN & stop (%2.2x)\n", val);
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DPRINTF("Set ATN & stop (%2.2x)\n", val);
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handle_satn_stop(s);
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handle_satn_stop(s);
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break;
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break;
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case 0x44:
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case 0x44:
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DPRINTF("Enable selection (%2.2x)\n", val);
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DPRINTF("Enable selection (%2.2x)\n", val);
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break;
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break;
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default:
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default:
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DPRINTF("Unhandled ESP command (%2.2x)\n", val);
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DPRINTF("Unhandled ESP command (%2.2x)\n", val);
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break;
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break;
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}
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}
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break;
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break;
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case 4 ... 7:
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case 4 ... 7:
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break;
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break;
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case 8:
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case 8:
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s->rregs[saddr] = val;
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s->rregs[saddr] = val;
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break;
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break;
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@ -492,7 +492,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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s->rregs[saddr] = val;
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s->rregs[saddr] = val;
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break;
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break;
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default:
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default:
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break;
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break;
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}
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}
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s->wregs[saddr] = val;
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s->wregs[saddr] = val;
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}
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}
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100
hw/iommu.c
100
hw/iommu.c
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@ -81,7 +81,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
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#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
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#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
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#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
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#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
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#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
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#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
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produced by this device as pure
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produced by this device as pure
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physical. */
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physical. */
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#define IOMMU_SBCFG_MASK 0x00010003
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#define IOMMU_SBCFG_MASK 0x00010003
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@ -98,7 +98,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
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#define PAGE_SHIFT 12
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#define PAGE_MASK (PAGE_SIZE - 1)
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#define PAGE_MASK (PAGE_SIZE - 1)
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typedef struct IOMMUState {
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typedef struct IOMMUState {
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target_phys_addr_t addr;
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target_phys_addr_t addr;
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@ -114,9 +114,9 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
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saddr = (addr - s->addr) >> 2;
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saddr = (addr - s->addr) >> 2;
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switch (saddr) {
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switch (saddr) {
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default:
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default:
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DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
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DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
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return s->regs[saddr];
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return s->regs[saddr];
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break;
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break;
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}
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}
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return 0;
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return 0;
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}
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}
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@ -130,61 +130,61 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
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DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
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DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
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switch (saddr) {
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switch (saddr) {
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case IOMMU_CTRL:
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case IOMMU_CTRL:
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switch (val & IOMMU_CTRL_RNGE) {
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switch (val & IOMMU_CTRL_RNGE) {
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case IOMMU_RNGE_16MB:
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case IOMMU_RNGE_16MB:
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s->iostart = 0xffffffffff000000ULL;
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s->iostart = 0xffffffffff000000ULL;
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break;
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break;
|
||||||
case IOMMU_RNGE_32MB:
|
case IOMMU_RNGE_32MB:
|
||||||
s->iostart = 0xfffffffffe000000ULL;
|
s->iostart = 0xfffffffffe000000ULL;
|
||||||
break;
|
break;
|
||||||
case IOMMU_RNGE_64MB:
|
case IOMMU_RNGE_64MB:
|
||||||
s->iostart = 0xfffffffffc000000ULL;
|
s->iostart = 0xfffffffffc000000ULL;
|
||||||
break;
|
break;
|
||||||
case IOMMU_RNGE_128MB:
|
case IOMMU_RNGE_128MB:
|
||||||
s->iostart = 0xfffffffff8000000ULL;
|
s->iostart = 0xfffffffff8000000ULL;
|
||||||
break;
|
break;
|
||||||
case IOMMU_RNGE_256MB:
|
case IOMMU_RNGE_256MB:
|
||||||
s->iostart = 0xfffffffff0000000ULL;
|
s->iostart = 0xfffffffff0000000ULL;
|
||||||
break;
|
break;
|
||||||
case IOMMU_RNGE_512MB:
|
case IOMMU_RNGE_512MB:
|
||||||
s->iostart = 0xffffffffe0000000ULL;
|
s->iostart = 0xffffffffe0000000ULL;
|
||||||
break;
|
break;
|
||||||
case IOMMU_RNGE_1GB:
|
case IOMMU_RNGE_1GB:
|
||||||
s->iostart = 0xffffffffc0000000ULL;
|
s->iostart = 0xffffffffc0000000ULL;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
case IOMMU_RNGE_2GB:
|
case IOMMU_RNGE_2GB:
|
||||||
s->iostart = 0xffffffff80000000ULL;
|
s->iostart = 0xffffffff80000000ULL;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
|
DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
|
||||||
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
|
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
|
||||||
break;
|
break;
|
||||||
case IOMMU_BASE:
|
case IOMMU_BASE:
|
||||||
s->regs[saddr] = val & IOMMU_BASE_MASK;
|
s->regs[saddr] = val & IOMMU_BASE_MASK;
|
||||||
break;
|
break;
|
||||||
case IOMMU_TLBFLUSH:
|
case IOMMU_TLBFLUSH:
|
||||||
DPRINTF("tlb flush %x\n", val);
|
DPRINTF("tlb flush %x\n", val);
|
||||||
s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
|
s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
|
||||||
break;
|
break;
|
||||||
case IOMMU_PGFLUSH:
|
case IOMMU_PGFLUSH:
|
||||||
DPRINTF("page flush %x\n", val);
|
DPRINTF("page flush %x\n", val);
|
||||||
s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
|
s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
|
||||||
break;
|
break;
|
||||||
case IOMMU_SBCFG0:
|
case IOMMU_SBCFG0:
|
||||||
case IOMMU_SBCFG1:
|
case IOMMU_SBCFG1:
|
||||||
case IOMMU_SBCFG2:
|
case IOMMU_SBCFG2:
|
||||||
case IOMMU_SBCFG3:
|
case IOMMU_SBCFG3:
|
||||||
s->regs[saddr] = val & IOMMU_SBCFG_MASK;
|
s->regs[saddr] = val & IOMMU_SBCFG_MASK;
|
||||||
break;
|
break;
|
||||||
case IOMMU_ARBEN:
|
case IOMMU_ARBEN:
|
||||||
// XXX implement SBus probing: fault when reading unmapped
|
// XXX implement SBus probing: fault when reading unmapped
|
||||||
// addresses, fault cause and address stored to MMU/IOMMU
|
// addresses, fault cause and address stored to MMU/IOMMU
|
||||||
s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
|
s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
s->regs[saddr] = val;
|
s->regs[saddr] = val;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -283,7 +283,7 @@ static void iommu_save(QEMUFile *f, void *opaque)
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; i < IOMMU_NREGS; i++)
|
for (i = 0; i < IOMMU_NREGS; i++)
|
||||||
qemu_put_be32s(f, &s->regs[i]);
|
qemu_put_be32s(f, &s->regs[i]);
|
||||||
qemu_put_be64s(f, &s->iostart);
|
qemu_put_be64s(f, &s->iostart);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -100,21 +100,21 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint
|
||||||
DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
|
DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
|
||||||
switch (saddr) {
|
switch (saddr) {
|
||||||
case 1: // clear pending softints
|
case 1: // clear pending softints
|
||||||
if (val & 0x4000)
|
if (val & 0x4000)
|
||||||
val |= 80000000;
|
val |= 80000000;
|
||||||
val &= 0xfffe0000;
|
val &= 0xfffe0000;
|
||||||
s->intreg_pending[cpu] &= ~val;
|
s->intreg_pending[cpu] &= ~val;
|
||||||
slavio_check_interrupts(s);
|
slavio_check_interrupts(s);
|
||||||
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
||||||
break;
|
break;
|
||||||
case 2: // set softint
|
case 2: // set softint
|
||||||
val &= 0xfffe0000;
|
val &= 0xfffe0000;
|
||||||
s->intreg_pending[cpu] |= val;
|
s->intreg_pending[cpu] |= val;
|
||||||
slavio_check_interrupts(s);
|
slavio_check_interrupts(s);
|
||||||
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -165,27 +165,27 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin
|
||||||
DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
|
DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
|
||||||
switch (saddr) {
|
switch (saddr) {
|
||||||
case 2: // clear (enable)
|
case 2: // clear (enable)
|
||||||
// Force clear unused bits
|
// Force clear unused bits
|
||||||
val &= ~0x4fb2007f;
|
val &= ~0x4fb2007f;
|
||||||
s->intregm_disabled &= ~val;
|
s->intregm_disabled &= ~val;
|
||||||
DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
|
DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
|
||||||
slavio_check_interrupts(s);
|
slavio_check_interrupts(s);
|
||||||
break;
|
break;
|
||||||
case 3: // set (disable, clear pending)
|
case 3: // set (disable, clear pending)
|
||||||
// Force clear unused bits
|
// Force clear unused bits
|
||||||
val &= ~0x4fb2007f;
|
val &= ~0x4fb2007f;
|
||||||
s->intregm_disabled |= val;
|
s->intregm_disabled |= val;
|
||||||
s->intregm_pending &= ~val;
|
s->intregm_pending &= ~val;
|
||||||
slavio_check_interrupts(s);
|
slavio_check_interrupts(s);
|
||||||
DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
|
DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
|
||||||
break;
|
break;
|
||||||
case 4:
|
case 4:
|
||||||
s->target_cpu = val & (MAX_CPUS - 1);
|
s->target_cpu = val & (MAX_CPUS - 1);
|
||||||
slavio_check_interrupts(s);
|
slavio_check_interrupts(s);
|
||||||
DPRINTF("Set master irq cpu %d\n", s->target_cpu);
|
DPRINTF("Set master irq cpu %d\n", s->target_cpu);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -207,7 +207,7 @@ void slavio_pic_info(void *opaque)
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; i < MAX_CPUS; i++) {
|
for (i = 0; i < MAX_CPUS; i++) {
|
||||||
term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
|
term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
|
||||||
}
|
}
|
||||||
term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
|
term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
|
||||||
}
|
}
|
||||||
|
@ -310,7 +310,7 @@ static void slavio_intctl_save(QEMUFile *f, void *opaque)
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; i < MAX_CPUS; i++) {
|
for (i = 0; i < MAX_CPUS; i++) {
|
||||||
qemu_put_be32s(f, &s->intreg_pending[i]);
|
qemu_put_be32s(f, &s->intreg_pending[i]);
|
||||||
}
|
}
|
||||||
qemu_put_be32s(f, &s->intregm_pending);
|
qemu_put_be32s(f, &s->intregm_pending);
|
||||||
qemu_put_be32s(f, &s->intregm_disabled);
|
qemu_put_be32s(f, &s->intregm_disabled);
|
||||||
|
@ -326,7 +326,7 @@ static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
for (i = 0; i < MAX_CPUS; i++) {
|
for (i = 0; i < MAX_CPUS; i++) {
|
||||||
qemu_get_be32s(f, &s->intreg_pending[i]);
|
qemu_get_be32s(f, &s->intreg_pending[i]);
|
||||||
}
|
}
|
||||||
qemu_get_be32s(f, &s->intregm_pending);
|
qemu_get_be32s(f, &s->intregm_pending);
|
||||||
qemu_get_be32s(f, &s->intregm_disabled);
|
qemu_get_be32s(f, &s->intregm_disabled);
|
||||||
|
@ -341,7 +341,7 @@ static void slavio_intctl_reset(void *opaque)
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; i < MAX_CPUS; i++) {
|
for (i = 0; i < MAX_CPUS; i++) {
|
||||||
s->intreg_pending[i] = 0;
|
s->intreg_pending[i] = 0;
|
||||||
}
|
}
|
||||||
s->intregm_disabled = ~0xffb2007f;
|
s->intregm_disabled = ~0xffb2007f;
|
||||||
s->intregm_pending = 0;
|
s->intregm_pending = 0;
|
||||||
|
@ -363,8 +363,8 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
|
||||||
|
|
||||||
s->intbit_to_level = intbit_to_level;
|
s->intbit_to_level = intbit_to_level;
|
||||||
for (i = 0; i < MAX_CPUS; i++) {
|
for (i = 0; i < MAX_CPUS; i++) {
|
||||||
slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
|
slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
|
||||||
cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
|
cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
|
||||||
slavio_intctl_io_memory);
|
slavio_intctl_io_memory);
|
||||||
s->cpu_irqs[i] = parent_irq[i];
|
s->cpu_irqs[i] = parent_irq[i];
|
||||||
}
|
}
|
||||||
|
|
106
hw/slavio_misc.c
106
hw/slavio_misc.c
|
@ -76,9 +76,9 @@ void slavio_set_power_fail(void *opaque, int power_failing)
|
||||||
|
|
||||||
MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
|
MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
|
||||||
if (power_failing && (s->config & 0x8)) {
|
if (power_failing && (s->config & 0x8)) {
|
||||||
s->aux2 |= 0x4;
|
s->aux2 |= 0x4;
|
||||||
} else {
|
} else {
|
||||||
s->aux2 &= ~0x4;
|
s->aux2 &= ~0x4;
|
||||||
}
|
}
|
||||||
slavio_misc_update_irq(s);
|
slavio_misc_update_irq(s);
|
||||||
}
|
}
|
||||||
|
@ -89,44 +89,44 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32
|
||||||
|
|
||||||
switch (addr & 0xfff0000) {
|
switch (addr & 0xfff0000) {
|
||||||
case 0x1800000:
|
case 0x1800000:
|
||||||
MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
|
MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
|
||||||
s->config = val & 0xff;
|
s->config = val & 0xff;
|
||||||
slavio_misc_update_irq(s);
|
slavio_misc_update_irq(s);
|
||||||
break;
|
break;
|
||||||
case 0x1900000:
|
case 0x1900000:
|
||||||
MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
|
MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
|
||||||
s->aux1 = val & 0xff;
|
s->aux1 = val & 0xff;
|
||||||
break;
|
break;
|
||||||
case 0x1910000:
|
case 0x1910000:
|
||||||
val &= 0x3;
|
val &= 0x3;
|
||||||
MISC_DPRINTF("Write aux2 %2.2x\n", val);
|
MISC_DPRINTF("Write aux2 %2.2x\n", val);
|
||||||
val |= s->aux2 & 0x4;
|
val |= s->aux2 & 0x4;
|
||||||
if (val & 0x2) // Clear Power Fail int
|
if (val & 0x2) // Clear Power Fail int
|
||||||
val &= 0x1;
|
val &= 0x1;
|
||||||
s->aux2 = val;
|
s->aux2 = val;
|
||||||
if (val & 1)
|
if (val & 1)
|
||||||
qemu_system_shutdown_request();
|
qemu_system_shutdown_request();
|
||||||
slavio_misc_update_irq(s);
|
slavio_misc_update_irq(s);
|
||||||
break;
|
break;
|
||||||
case 0x1a00000:
|
case 0x1a00000:
|
||||||
MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
|
MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
|
||||||
s->diag = val & 0xff;
|
s->diag = val & 0xff;
|
||||||
break;
|
break;
|
||||||
case 0x1b00000:
|
case 0x1b00000:
|
||||||
MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
|
MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
|
||||||
s->mctrl = val & 0xff;
|
s->mctrl = val & 0xff;
|
||||||
break;
|
break;
|
||||||
case 0x1f00000:
|
case 0x1f00000:
|
||||||
MISC_DPRINTF("Write system control %2.2x\n", val & 0xff);
|
MISC_DPRINTF("Write system control %2.2x\n", val & 0xff);
|
||||||
if (val & 1) {
|
if (val & 1) {
|
||||||
s->sysctrl = 0x2;
|
s->sysctrl = 0x2;
|
||||||
qemu_system_reset_request();
|
qemu_system_reset_request();
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case 0xa000000:
|
case 0xa000000:
|
||||||
MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
|
MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
|
||||||
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
|
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -137,32 +137,32 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
|
||||||
|
|
||||||
switch (addr & 0xfff0000) {
|
switch (addr & 0xfff0000) {
|
||||||
case 0x1800000:
|
case 0x1800000:
|
||||||
ret = s->config;
|
ret = s->config;
|
||||||
MISC_DPRINTF("Read config %2.2x\n", ret);
|
MISC_DPRINTF("Read config %2.2x\n", ret);
|
||||||
break;
|
break;
|
||||||
case 0x1900000:
|
case 0x1900000:
|
||||||
ret = s->aux1;
|
ret = s->aux1;
|
||||||
MISC_DPRINTF("Read aux1 %2.2x\n", ret);
|
MISC_DPRINTF("Read aux1 %2.2x\n", ret);
|
||||||
break;
|
break;
|
||||||
case 0x1910000:
|
case 0x1910000:
|
||||||
ret = s->aux2;
|
ret = s->aux2;
|
||||||
MISC_DPRINTF("Read aux2 %2.2x\n", ret);
|
MISC_DPRINTF("Read aux2 %2.2x\n", ret);
|
||||||
break;
|
break;
|
||||||
case 0x1a00000:
|
case 0x1a00000:
|
||||||
ret = s->diag;
|
ret = s->diag;
|
||||||
MISC_DPRINTF("Read diag %2.2x\n", ret);
|
MISC_DPRINTF("Read diag %2.2x\n", ret);
|
||||||
break;
|
break;
|
||||||
case 0x1b00000:
|
case 0x1b00000:
|
||||||
ret = s->mctrl;
|
ret = s->mctrl;
|
||||||
MISC_DPRINTF("Read modem control %2.2x\n", ret);
|
MISC_DPRINTF("Read modem control %2.2x\n", ret);
|
||||||
break;
|
break;
|
||||||
case 0x1f00000:
|
case 0x1f00000:
|
||||||
MISC_DPRINTF("Read system control %2.2x\n", ret);
|
MISC_DPRINTF("Read system control %2.2x\n", ret);
|
||||||
ret = s->sysctrl;
|
ret = s->sysctrl;
|
||||||
break;
|
break;
|
||||||
case 0xa000000:
|
case 0xa000000:
|
||||||
MISC_DPRINTF("Read power management %2.2x\n", ret);
|
MISC_DPRINTF("Read power management %2.2x\n", ret);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
|
@ -139,7 +139,7 @@ static uint32_t get_queue(void *opaque)
|
||||||
int val;
|
int val;
|
||||||
|
|
||||||
if (q->count == 0) {
|
if (q->count == 0) {
|
||||||
return 0;
|
return 0;
|
||||||
} else {
|
} else {
|
||||||
val = q->data[q->rptr];
|
val = q->data[q->rptr];
|
||||||
if (++q->rptr == SERIO_QUEUE_SIZE)
|
if (++q->rptr == SERIO_QUEUE_SIZE)
|
||||||
|
@ -148,17 +148,17 @@ static uint32_t get_queue(void *opaque)
|
||||||
}
|
}
|
||||||
SER_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val);
|
SER_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val);
|
||||||
if (q->count > 0)
|
if (q->count > 0)
|
||||||
serial_receive_byte(s, 0);
|
serial_receive_byte(s, 0);
|
||||||
return val;
|
return val;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int slavio_serial_update_irq_chn(ChannelState *s)
|
static int slavio_serial_update_irq_chn(ChannelState *s)
|
||||||
{
|
{
|
||||||
if ((s->wregs[1] & 1) && // interrupts enabled
|
if ((s->wregs[1] & 1) && // interrupts enabled
|
||||||
(((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending
|
(((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending
|
||||||
((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) &&
|
((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) &&
|
||||||
s->rxint == 1) || // rx ints enabled, pending
|
s->rxint == 1) || // rx ints enabled, pending
|
||||||
((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p
|
((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -181,8 +181,8 @@ static void slavio_serial_reset_chn(ChannelState *s)
|
||||||
|
|
||||||
s->reg = 0;
|
s->reg = 0;
|
||||||
for (i = 0; i < SERIAL_SIZE; i++) {
|
for (i = 0; i < SERIAL_SIZE; i++) {
|
||||||
s->rregs[i] = 0;
|
s->rregs[i] = 0;
|
||||||
s->wregs[i] = 0;
|
s->wregs[i] = 0;
|
||||||
}
|
}
|
||||||
s->wregs[4] = 4;
|
s->wregs[4] = 4;
|
||||||
s->wregs[9] = 0xc0;
|
s->wregs[9] = 0xc0;
|
||||||
|
@ -367,82 +367,82 @@ static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint
|
||||||
s = &serial->chn[channel];
|
s = &serial->chn[channel];
|
||||||
switch (saddr) {
|
switch (saddr) {
|
||||||
case 0:
|
case 0:
|
||||||
SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff);
|
SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff);
|
||||||
newreg = 0;
|
newreg = 0;
|
||||||
switch (s->reg) {
|
switch (s->reg) {
|
||||||
case 0:
|
case 0:
|
||||||
newreg = val & 7;
|
newreg = val & 7;
|
||||||
val &= 0x38;
|
val &= 0x38;
|
||||||
switch (val) {
|
switch (val) {
|
||||||
case 8:
|
case 8:
|
||||||
newreg |= 0x8;
|
newreg |= 0x8;
|
||||||
break;
|
break;
|
||||||
case 0x28:
|
case 0x28:
|
||||||
clr_txint(s);
|
clr_txint(s);
|
||||||
break;
|
break;
|
||||||
case 0x38:
|
case 0x38:
|
||||||
if (s->rxint_under_svc)
|
if (s->rxint_under_svc)
|
||||||
clr_rxint(s);
|
clr_rxint(s);
|
||||||
else if (s->txint_under_svc)
|
else if (s->txint_under_svc)
|
||||||
clr_txint(s);
|
clr_txint(s);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case 1 ... 3:
|
case 1 ... 3:
|
||||||
case 6 ... 8:
|
case 6 ... 8:
|
||||||
case 10 ... 11:
|
case 10 ... 11:
|
||||||
case 14 ... 15:
|
case 14 ... 15:
|
||||||
s->wregs[s->reg] = val;
|
s->wregs[s->reg] = val;
|
||||||
break;
|
break;
|
||||||
case 4:
|
case 4:
|
||||||
case 5:
|
case 5:
|
||||||
case 12:
|
case 12:
|
||||||
case 13:
|
case 13:
|
||||||
s->wregs[s->reg] = val;
|
s->wregs[s->reg] = val;
|
||||||
slavio_serial_update_parameters(s);
|
slavio_serial_update_parameters(s);
|
||||||
break;
|
break;
|
||||||
case 9:
|
case 9:
|
||||||
switch (val & 0xc0) {
|
switch (val & 0xc0) {
|
||||||
case 0:
|
case 0:
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
case 0x40:
|
case 0x40:
|
||||||
slavio_serial_reset_chn(&serial->chn[1]);
|
slavio_serial_reset_chn(&serial->chn[1]);
|
||||||
return;
|
return;
|
||||||
case 0x80:
|
case 0x80:
|
||||||
slavio_serial_reset_chn(&serial->chn[0]);
|
slavio_serial_reset_chn(&serial->chn[0]);
|
||||||
return;
|
return;
|
||||||
case 0xc0:
|
case 0xc0:
|
||||||
slavio_serial_reset(serial);
|
slavio_serial_reset(serial);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (s->reg == 0)
|
if (s->reg == 0)
|
||||||
s->reg = newreg;
|
s->reg = newreg;
|
||||||
else
|
else
|
||||||
s->reg = 0;
|
s->reg = 0;
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val);
|
SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val);
|
||||||
s->tx = val;
|
s->tx = val;
|
||||||
if (s->wregs[5] & 8) { // tx enabled
|
if (s->wregs[5] & 8) { // tx enabled
|
||||||
if (s->chr)
|
if (s->chr)
|
||||||
qemu_chr_write(s->chr, &s->tx, 1);
|
qemu_chr_write(s->chr, &s->tx, 1);
|
||||||
else if (s->type == kbd) {
|
else if (s->type == kbd) {
|
||||||
handle_kbd_command(s, val);
|
handle_kbd_command(s, val);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
s->rregs[0] |= 4; // Tx buffer empty
|
s->rregs[0] |= 4; // Tx buffer empty
|
||||||
s->rregs[1] |= 1; // All sent
|
s->rregs[1] |= 1; // All sent
|
||||||
set_txint(s);
|
set_txint(s);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -459,21 +459,21 @@ static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr)
|
||||||
s = &serial->chn[channel];
|
s = &serial->chn[channel];
|
||||||
switch (saddr) {
|
switch (saddr) {
|
||||||
case 0:
|
case 0:
|
||||||
SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]);
|
SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]);
|
||||||
ret = s->rregs[s->reg];
|
ret = s->rregs[s->reg];
|
||||||
s->reg = 0;
|
s->reg = 0;
|
||||||
return ret;
|
return ret;
|
||||||
case 1:
|
case 1:
|
||||||
s->rregs[0] &= ~1;
|
s->rregs[0] &= ~1;
|
||||||
clr_rxint(s);
|
clr_rxint(s);
|
||||||
if (s->type == kbd || s->type == mouse)
|
if (s->type == kbd || s->type == mouse)
|
||||||
ret = get_queue(s);
|
ret = get_queue(s);
|
||||||
else
|
else
|
||||||
ret = s->rx;
|
ret = s->rx;
|
||||||
SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);
|
SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);
|
||||||
return ret;
|
return ret;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -484,10 +484,10 @@ static int serial_can_receive(void *opaque)
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
if (((s->wregs[3] & 1) == 0) // Rx not enabled
|
if (((s->wregs[3] & 1) == 0) // Rx not enabled
|
||||||
|| ((s->rregs[0] & 1) == 1)) // char already available
|
|| ((s->rregs[0] & 1) == 1)) // char already available
|
||||||
ret = 0;
|
ret = 0;
|
||||||
else
|
else
|
||||||
ret = 1;
|
ret = 1;
|
||||||
//SER_DPRINTF("channel %c can receive %d\n", CHN_C(s), ret);
|
//SER_DPRINTF("channel %c can receive %d\n", CHN_C(s), ret);
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
@ -584,7 +584,7 @@ static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id)
|
||||||
|
|
||||||
ret = slavio_serial_load_chn(f, &s->chn[0], version_id);
|
ret = slavio_serial_load_chn(f, &s->chn[0], version_id);
|
||||||
if (ret != 0)
|
if (ret != 0)
|
||||||
return ret;
|
return ret;
|
||||||
ret = slavio_serial_load_chn(f, &s->chn[1], version_id);
|
ret = slavio_serial_load_chn(f, &s->chn[1], version_id);
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
|
@ -607,13 +607,13 @@ SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
|
||||||
s->chn[1].chr = chr2;
|
s->chn[1].chr = chr2;
|
||||||
|
|
||||||
for (i = 0; i < 2; i++) {
|
for (i = 0; i < 2; i++) {
|
||||||
s->chn[i].irq = irq;
|
s->chn[i].irq = irq;
|
||||||
s->chn[i].chn = 1 - i;
|
s->chn[i].chn = 1 - i;
|
||||||
s->chn[i].type = ser;
|
s->chn[i].type = ser;
|
||||||
if (s->chn[i].chr) {
|
if (s->chn[i].chr) {
|
||||||
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
|
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
|
||||||
serial_receive1, serial_event, &s->chn[i]);
|
serial_receive1, serial_event, &s->chn[i]);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
s->chn[0].otherchn = &s->chn[1];
|
s->chn[0].otherchn = &s->chn[1];
|
||||||
s->chn[1].otherchn = &s->chn[0];
|
s->chn[1].otherchn = &s->chn[0];
|
||||||
|
@ -698,21 +698,21 @@ static void handle_kbd_command(ChannelState *s, int val)
|
||||||
switch (val) {
|
switch (val) {
|
||||||
case 1: // Reset, return type code
|
case 1: // Reset, return type code
|
||||||
clear_queue(s);
|
clear_queue(s);
|
||||||
put_queue(s, 0xff);
|
put_queue(s, 0xff);
|
||||||
put_queue(s, 4); // Type 4
|
put_queue(s, 4); // Type 4
|
||||||
put_queue(s, 0x7f);
|
put_queue(s, 0x7f);
|
||||||
break;
|
break;
|
||||||
case 0xe: // Set leds
|
case 0xe: // Set leds
|
||||||
s->led_mode = 1;
|
s->led_mode = 1;
|
||||||
break;
|
break;
|
||||||
case 7: // Query layout
|
case 7: // Query layout
|
||||||
case 0xf:
|
case 0xf:
|
||||||
clear_queue(s);
|
clear_queue(s);
|
||||||
put_queue(s, 0xfe);
|
put_queue(s, 0xfe);
|
||||||
put_queue(s, 0); // XXX, layout?
|
put_queue(s, 0); // XXX, layout?
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -768,9 +768,9 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq)
|
||||||
if (!s)
|
if (!s)
|
||||||
return;
|
return;
|
||||||
for (i = 0; i < 2; i++) {
|
for (i = 0; i < 2; i++) {
|
||||||
s->chn[i].irq = irq;
|
s->chn[i].irq = irq;
|
||||||
s->chn[i].chn = 1 - i;
|
s->chn[i].chn = 1 - i;
|
||||||
s->chn[i].chr = NULL;
|
s->chn[i].chr = NULL;
|
||||||
}
|
}
|
||||||
s->chn[0].otherchn = &s->chn[1];
|
s->chn[0].otherchn = &s->chn[1];
|
||||||
s->chn[1].otherchn = &s->chn[0];
|
s->chn[1].otherchn = &s->chn[0];
|
||||||
|
|
|
@ -86,7 +86,7 @@ static void slavio_timer_irq(void *opaque)
|
||||||
DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
|
DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
|
||||||
s->reached = 0x80000000;
|
s->reached = 0x80000000;
|
||||||
if (s->mode != 1)
|
if (s->mode != 1)
|
||||||
qemu_irq_raise(s->irq);
|
qemu_irq_raise(s->irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
|
static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
|
||||||
|
@ -97,34 +97,34 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
|
||||||
saddr = (addr & TIMER_MAXADDR) >> 2;
|
saddr = (addr & TIMER_MAXADDR) >> 2;
|
||||||
switch (saddr) {
|
switch (saddr) {
|
||||||
case 0:
|
case 0:
|
||||||
// read limit (system counter mode) or read most signifying
|
// read limit (system counter mode) or read most signifying
|
||||||
// part of counter (user mode)
|
// part of counter (user mode)
|
||||||
if (s->mode != 1) {
|
if (s->mode != 1) {
|
||||||
// clear irq
|
// clear irq
|
||||||
qemu_irq_lower(s->irq);
|
qemu_irq_lower(s->irq);
|
||||||
s->reached = 0;
|
s->reached = 0;
|
||||||
ret = s->limit & 0x7fffffff;
|
ret = s->limit & 0x7fffffff;
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
slavio_timer_get_out(s);
|
slavio_timer_get_out(s);
|
||||||
ret = s->counthigh & 0x7fffffff;
|
ret = s->counthigh & 0x7fffffff;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
// read counter and reached bit (system mode) or read lsbits
|
// read counter and reached bit (system mode) or read lsbits
|
||||||
// of counter (user mode)
|
// of counter (user mode)
|
||||||
slavio_timer_get_out(s);
|
slavio_timer_get_out(s);
|
||||||
if (s->mode != 1)
|
if (s->mode != 1)
|
||||||
ret = (s->count & 0x7fffffff) | s->reached;
|
ret = (s->count & 0x7fffffff) | s->reached;
|
||||||
else
|
else
|
||||||
ret = s->count;
|
ret = s->count;
|
||||||
break;
|
break;
|
||||||
case 3:
|
case 3:
|
||||||
// read start/stop status
|
// read start/stop status
|
||||||
ret = s->stopped;
|
ret = s->stopped;
|
||||||
break;
|
break;
|
||||||
case 4:
|
case 4:
|
||||||
// read user/system mode
|
// read user/system mode
|
||||||
ret = s->slave_mode;
|
ret = s->slave_mode;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
@ -161,14 +161,14 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3
|
||||||
qemu_irq_lower(s->irq);
|
qemu_irq_lower(s->irq);
|
||||||
// fall through
|
// fall through
|
||||||
case 2:
|
case 2:
|
||||||
// set limit without resetting counter
|
// set limit without resetting counter
|
||||||
s->limit = val & 0x7ffffe00ULL;
|
s->limit = val & 0x7ffffe00ULL;
|
||||||
if (!s->limit)
|
if (!s->limit)
|
||||||
s->limit = 0x7ffffe00ULL;
|
s->limit = 0x7ffffe00ULL;
|
||||||
ptimer_set_limit(s->timer, s->limit >> 9, reload);
|
ptimer_set_limit(s->timer, s->limit >> 9, reload);
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
// set user counter limit LSW, reset counter
|
// set user counter limit LSW, reset counter
|
||||||
if (s->mode == 1) {
|
if (s->mode == 1) {
|
||||||
qemu_irq_lower(s->irq);
|
qemu_irq_lower(s->irq);
|
||||||
s->limit &= 0x7fffffff00000000ULL;
|
s->limit &= 0x7fffffff00000000ULL;
|
||||||
|
@ -179,20 +179,20 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case 3:
|
case 3:
|
||||||
// start/stop user counter
|
// start/stop user counter
|
||||||
if (s->mode == 1) {
|
if (s->mode == 1) {
|
||||||
if (val & 1) {
|
if (val & 1) {
|
||||||
ptimer_stop(s->timer);
|
ptimer_stop(s->timer);
|
||||||
s->stopped = 1;
|
s->stopped = 1;
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
ptimer_run(s->timer, 0);
|
ptimer_run(s->timer, 0);
|
||||||
s->stopped = 0;
|
s->stopped = 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case 4:
|
case 4:
|
||||||
// bit 0: user (1) or system (0) counter mode
|
// bit 0: user (1) or system (0) counter mode
|
||||||
{
|
{
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
|
|
||||||
|
@ -211,9 +211,9 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3
|
||||||
}
|
}
|
||||||
s->slave_mode = val & ((1 << MAX_CPUS) - 1);
|
s->slave_mode = val & ((1 << MAX_CPUS) - 1);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -294,7 +294,7 @@ static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
|
||||||
ptimer_set_period(s->timer, 500ULL);
|
ptimer_set_period(s->timer, 500ULL);
|
||||||
|
|
||||||
slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
|
slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
|
||||||
slavio_timer_mem_write, s);
|
slavio_timer_mem_write, s);
|
||||||
if (mode < 2)
|
if (mode < 2)
|
||||||
cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory);
|
cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory);
|
||||||
else
|
else
|
||||||
|
|
44
hw/sun4m.c
44
hw/sun4m.c
|
@ -52,7 +52,7 @@
|
||||||
#define PROM_SIZE_MAX (512 * 1024)
|
#define PROM_SIZE_MAX (512 * 1024)
|
||||||
#define PROM_PADDR 0xff0000000ULL
|
#define PROM_PADDR 0xff0000000ULL
|
||||||
#define PROM_VADDR 0xffd00000
|
#define PROM_VADDR 0xffd00000
|
||||||
#define PROM_FILENAME "openbios-sparc32"
|
#define PROM_FILENAME "openbios-sparc32"
|
||||||
|
|
||||||
#define MAX_CPUS 16
|
#define MAX_CPUS 16
|
||||||
#define MAX_PILS 16
|
#define MAX_PILS 16
|
||||||
|
@ -158,9 +158,9 @@ static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
|
||||||
extern int nographic;
|
extern int nographic;
|
||||||
|
|
||||||
static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
|
static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
|
||||||
int boot_device, uint32_t RAM_size,
|
int boot_device, uint32_t RAM_size,
|
||||||
uint32_t kernel_size,
|
uint32_t kernel_size,
|
||||||
int width, int height, int depth,
|
int width, int height, int depth,
|
||||||
int machine_id)
|
int machine_id)
|
||||||
{
|
{
|
||||||
unsigned char tmp = 0;
|
unsigned char tmp = 0;
|
||||||
|
@ -179,8 +179,8 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
|
||||||
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
|
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
|
||||||
nvram_set_lword(nvram, 0x3C, kernel_size);
|
nvram_set_lword(nvram, 0x3C, kernel_size);
|
||||||
if (cmdline) {
|
if (cmdline) {
|
||||||
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
|
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
|
||||||
nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
||||||
nvram_set_lword(nvram, 0x44, strlen(cmdline));
|
nvram_set_lword(nvram, 0x44, strlen(cmdline));
|
||||||
}
|
}
|
||||||
// initrd_image, initrd_size passed differently
|
// initrd_image, initrd_size passed differently
|
||||||
|
@ -444,13 +444,13 @@ static void sun4m_load_kernel(long vram_size, int RAM_size, int boot_device,
|
||||||
kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
|
kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
|
||||||
NULL);
|
NULL);
|
||||||
if (kernel_size < 0)
|
if (kernel_size < 0)
|
||||||
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
||||||
if (kernel_size < 0)
|
if (kernel_size < 0)
|
||||||
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
||||||
if (kernel_size < 0) {
|
if (kernel_size < 0) {
|
||||||
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
||||||
kernel_filename);
|
kernel_filename);
|
||||||
exit(1);
|
exit(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* load initrd */
|
/* load initrd */
|
||||||
|
@ -464,14 +464,14 @@ static void sun4m_load_kernel(long vram_size, int RAM_size, int boot_device,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (initrd_size > 0) {
|
if (initrd_size > 0) {
|
||||||
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
|
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
|
||||||
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
||||||
== 0x48647253) { // HdrS
|
== 0x48647253) { // HdrS
|
||||||
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
||||||
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
||||||
|
@ -509,8 +509,8 @@ static const struct hwdef hwdefs[] = {
|
||||||
.cs_irq = 5,
|
.cs_irq = 5,
|
||||||
.machine_id = 0x80,
|
.machine_id = 0x80,
|
||||||
.intbit_to_level = {
|
.intbit_to_level = {
|
||||||
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
|
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
|
||||||
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
|
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
/* SS-10 */
|
/* SS-10 */
|
||||||
|
@ -542,8 +542,8 @@ static const struct hwdef hwdefs[] = {
|
||||||
.cs_irq = -1,
|
.cs_irq = -1,
|
||||||
.machine_id = 0x72,
|
.machine_id = 0x72,
|
||||||
.intbit_to_level = {
|
.intbit_to_level = {
|
||||||
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
|
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
|
||||||
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
|
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
46
hw/sun4u.c
46
hw/sun4u.c
|
@ -28,12 +28,12 @@
|
||||||
#define CMDLINE_ADDR 0x003ff000
|
#define CMDLINE_ADDR 0x003ff000
|
||||||
#define INITRD_LOAD_ADDR 0x00300000
|
#define INITRD_LOAD_ADDR 0x00300000
|
||||||
#define PROM_SIZE_MAX (512 * 1024)
|
#define PROM_SIZE_MAX (512 * 1024)
|
||||||
#define PROM_ADDR 0x1fff0000000ULL
|
#define PROM_ADDR 0x1fff0000000ULL
|
||||||
#define PROM_VADDR 0x000ffd00000ULL
|
#define PROM_VADDR 0x000ffd00000ULL
|
||||||
#define APB_SPECIAL_BASE 0x1fe00000000ULL
|
#define APB_SPECIAL_BASE 0x1fe00000000ULL
|
||||||
#define APB_MEM_BASE 0x1ff00000000ULL
|
#define APB_MEM_BASE 0x1ff00000000ULL
|
||||||
#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
|
#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
|
||||||
#define PROM_FILENAME "openbios-sparc64"
|
#define PROM_FILENAME "openbios-sparc64"
|
||||||
#define NVRAM_SIZE 0x2000
|
#define NVRAM_SIZE 0x2000
|
||||||
|
|
||||||
/* TSC handling */
|
/* TSC handling */
|
||||||
|
@ -162,10 +162,10 @@ uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
|
||||||
odd = count & 1;
|
odd = count & 1;
|
||||||
count &= ~1;
|
count &= ~1;
|
||||||
for (i = 0; i != count; i++) {
|
for (i = 0; i != count; i++) {
|
||||||
crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
|
crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
|
||||||
}
|
}
|
||||||
if (odd) {
|
if (odd) {
|
||||||
crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
||||||
}
|
}
|
||||||
|
|
||||||
return crc;
|
return crc;
|
||||||
|
@ -387,9 +387,9 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
|
||||||
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
|
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
|
||||||
ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
|
ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
||||||
buf);
|
buf);
|
||||||
exit(1);
|
exit(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
kernel_size = 0;
|
kernel_size = 0;
|
||||||
|
@ -398,13 +398,13 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
|
||||||
/* XXX: put correct offset */
|
/* XXX: put correct offset */
|
||||||
kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
|
kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
|
||||||
if (kernel_size < 0)
|
if (kernel_size < 0)
|
||||||
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
||||||
if (kernel_size < 0)
|
if (kernel_size < 0)
|
||||||
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
||||||
if (kernel_size < 0) {
|
if (kernel_size < 0) {
|
||||||
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
||||||
kernel_filename);
|
kernel_filename);
|
||||||
exit(1);
|
exit(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* load initrd */
|
/* load initrd */
|
||||||
|
@ -417,14 +417,14 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (initrd_size > 0) {
|
if (initrd_size > 0) {
|
||||||
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
|
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
|
||||||
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
||||||
== 0x48647253) { // HdrS
|
== 0x48647253) { // HdrS
|
||||||
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
||||||
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
|
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
|
||||||
|
@ -446,7 +446,7 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
|
||||||
for(i = 0; i < nb_nics; i++) {
|
for(i = 0; i < nb_nics; i++) {
|
||||||
if (!nd_table[i].model)
|
if (!nd_table[i].model)
|
||||||
nd_table[i].model = "ne2k_pci";
|
nd_table[i].model = "ne2k_pci";
|
||||||
pci_nic_init(pci_bus, &nd_table[i], -1);
|
pci_nic_init(pci_bus, &nd_table[i], -1);
|
||||||
}
|
}
|
||||||
|
|
||||||
irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
|
irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
|
||||||
|
|
112
hw/tcx.c
112
hw/tcx.c
|
@ -84,39 +84,39 @@ static void update_palette_entries(TCXState *s, int start, int end)
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tcx_draw_line32(TCXState *s1, uint8_t *d,
|
static void tcx_draw_line32(TCXState *s1, uint8_t *d,
|
||||||
const uint8_t *s, int width)
|
const uint8_t *s, int width)
|
||||||
{
|
{
|
||||||
int x;
|
int x;
|
||||||
uint8_t val;
|
uint8_t val;
|
||||||
uint32_t *p = (uint32_t *)d;
|
uint32_t *p = (uint32_t *)d;
|
||||||
|
|
||||||
for(x = 0; x < width; x++) {
|
for(x = 0; x < width; x++) {
|
||||||
val = *s++;
|
val = *s++;
|
||||||
*p++ = s1->palette[val];
|
*p++ = s1->palette[val];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tcx_draw_line16(TCXState *s1, uint8_t *d,
|
static void tcx_draw_line16(TCXState *s1, uint8_t *d,
|
||||||
const uint8_t *s, int width)
|
const uint8_t *s, int width)
|
||||||
{
|
{
|
||||||
int x;
|
int x;
|
||||||
uint8_t val;
|
uint8_t val;
|
||||||
uint16_t *p = (uint16_t *)d;
|
uint16_t *p = (uint16_t *)d;
|
||||||
|
|
||||||
for(x = 0; x < width; x++) {
|
for(x = 0; x < width; x++) {
|
||||||
val = *s++;
|
val = *s++;
|
||||||
*p++ = s1->palette[val];
|
*p++ = s1->palette[val];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tcx_draw_line8(TCXState *s1, uint8_t *d,
|
static void tcx_draw_line8(TCXState *s1, uint8_t *d,
|
||||||
const uint8_t *s, int width)
|
const uint8_t *s, int width)
|
||||||
{
|
{
|
||||||
int x;
|
int x;
|
||||||
uint8_t val;
|
uint8_t val;
|
||||||
|
|
||||||
for(x = 0; x < width; x++) {
|
for(x = 0; x < width; x++) {
|
||||||
val = *s++;
|
val = *s++;
|
||||||
*d++ = s1->palette[val];
|
*d++ = s1->palette[val];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -183,7 +183,7 @@ static void tcx_update_display(void *opaque)
|
||||||
void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
|
void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
|
||||||
|
|
||||||
if (ts->ds->depth == 0)
|
if (ts->ds->depth == 0)
|
||||||
return;
|
return;
|
||||||
page = ts->vram_offset;
|
page = ts->vram_offset;
|
||||||
y_start = -1;
|
y_start = -1;
|
||||||
page_min = 0xffffffff;
|
page_min = 0xffffffff;
|
||||||
|
@ -195,55 +195,55 @@ static void tcx_update_display(void *opaque)
|
||||||
|
|
||||||
switch (ts->ds->depth) {
|
switch (ts->ds->depth) {
|
||||||
case 32:
|
case 32:
|
||||||
f = tcx_draw_line32;
|
f = tcx_draw_line32;
|
||||||
break;
|
break;
|
||||||
case 15:
|
case 15:
|
||||||
case 16:
|
case 16:
|
||||||
f = tcx_draw_line16;
|
f = tcx_draw_line16;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
case 8:
|
case 8:
|
||||||
f = tcx_draw_line8;
|
f = tcx_draw_line8;
|
||||||
break;
|
break;
|
||||||
case 0:
|
case 0:
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
|
for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
|
||||||
if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
|
if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
|
||||||
if (y_start < 0)
|
if (y_start < 0)
|
||||||
y_start = y;
|
y_start = y;
|
||||||
if (page < page_min)
|
if (page < page_min)
|
||||||
page_min = page;
|
page_min = page;
|
||||||
if (page > page_max)
|
if (page > page_max)
|
||||||
page_max = page;
|
page_max = page;
|
||||||
f(ts, d, s, ts->width);
|
f(ts, d, s, ts->width);
|
||||||
d += dd;
|
d += dd;
|
||||||
s += ds;
|
s += ds;
|
||||||
f(ts, d, s, ts->width);
|
f(ts, d, s, ts->width);
|
||||||
d += dd;
|
d += dd;
|
||||||
s += ds;
|
s += ds;
|
||||||
f(ts, d, s, ts->width);
|
f(ts, d, s, ts->width);
|
||||||
d += dd;
|
d += dd;
|
||||||
s += ds;
|
s += ds;
|
||||||
f(ts, d, s, ts->width);
|
f(ts, d, s, ts->width);
|
||||||
d += dd;
|
d += dd;
|
||||||
s += ds;
|
s += ds;
|
||||||
} else {
|
} else {
|
||||||
if (y_start >= 0) {
|
if (y_start >= 0) {
|
||||||
/* flush to display */
|
/* flush to display */
|
||||||
dpy_update(ts->ds, 0, y_start,
|
dpy_update(ts->ds, 0, y_start,
|
||||||
ts->width, y - y_start);
|
ts->width, y - y_start);
|
||||||
y_start = -1;
|
y_start = -1;
|
||||||
}
|
}
|
||||||
d += dd * 4;
|
d += dd * 4;
|
||||||
s += ds * 4;
|
s += ds * 4;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (y_start >= 0) {
|
if (y_start >= 0) {
|
||||||
/* flush to display */
|
/* flush to display */
|
||||||
dpy_update(ts->ds, 0, y_start,
|
dpy_update(ts->ds, 0, y_start,
|
||||||
ts->width, y - y_start);
|
ts->width, y - y_start);
|
||||||
}
|
}
|
||||||
/* reset modified pages */
|
/* reset modified pages */
|
||||||
if (page_min <= page_max) {
|
if (page_min <= page_max) {
|
||||||
|
@ -334,7 +334,7 @@ static void tcx_invalidate_display(void *opaque)
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
|
for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
|
||||||
cpu_physical_memory_set_dirty(s->vram_offset + i);
|
cpu_physical_memory_set_dirty(s->vram_offset + i);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -424,32 +424,32 @@ static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||||
saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
|
saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
|
||||||
switch (saddr) {
|
switch (saddr) {
|
||||||
case 0:
|
case 0:
|
||||||
s->dac_index = val >> 24;
|
s->dac_index = val >> 24;
|
||||||
s->dac_state = 0;
|
s->dac_state = 0;
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
switch (s->dac_state) {
|
switch (s->dac_state) {
|
||||||
case 0:
|
case 0:
|
||||||
s->r[s->dac_index] = val >> 24;
|
s->r[s->dac_index] = val >> 24;
|
||||||
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
||||||
s->dac_state++;
|
s->dac_state++;
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
s->g[s->dac_index] = val >> 24;
|
s->g[s->dac_index] = val >> 24;
|
||||||
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
||||||
s->dac_state++;
|
s->dac_state++;
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
s->b[s->dac_index] = val >> 24;
|
s->b[s->dac_index] = val >> 24;
|
||||||
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
||||||
s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
|
s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
|
||||||
default:
|
default:
|
||||||
s->dac_state = 0;
|
s->dac_state = 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
3672
sparc-dis.c
3672
sparc-dis.c
File diff suppressed because it is too large
Load Diff
48
sparc.ld
48
sparc.ld
|
@ -1,5 +1,5 @@
|
||||||
OUTPUT_FORMAT("elf32-sparc", "elf32-sparc",
|
OUTPUT_FORMAT("elf32-sparc", "elf32-sparc",
|
||||||
"elf32-sparc")
|
"elf32-sparc")
|
||||||
OUTPUT_ARCH(sparc)
|
OUTPUT_ARCH(sparc)
|
||||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/alpha-unknown-linux-gnu/lib);
|
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/alpha-unknown-linux-gnu/lib);
|
||||||
ENTRY(_start)
|
ENTRY(_start)
|
||||||
|
@ -7,13 +7,13 @@ SECTIONS
|
||||||
{
|
{
|
||||||
/* Read-only sections, merged into text segment: */
|
/* Read-only sections, merged into text segment: */
|
||||||
. = 0x60000000 + SIZEOF_HEADERS;
|
. = 0x60000000 + SIZEOF_HEADERS;
|
||||||
.interp : { *(.interp) }
|
.interp : { *(.interp) }
|
||||||
.hash : { *(.hash) }
|
.hash : { *(.hash) }
|
||||||
.dynsym : { *(.dynsym) }
|
.dynsym : { *(.dynsym) }
|
||||||
.dynstr : { *(.dynstr) }
|
.dynstr : { *(.dynstr) }
|
||||||
.gnu.version : { *(.gnu.version) }
|
.gnu.version : { *(.gnu.version) }
|
||||||
.gnu.version_d : { *(.gnu.version_d) }
|
.gnu.version_d : { *(.gnu.version_d) }
|
||||||
.gnu.version_r : { *(.gnu.version_r) }
|
.gnu.version_r : { *(.gnu.version_r) }
|
||||||
.rel.text :
|
.rel.text :
|
||||||
{ *(.rel.text) *(.rel.gnu.linkonce.t*) }
|
{ *(.rel.text) *(.rel.gnu.linkonce.t*) }
|
||||||
.rela.text :
|
.rela.text :
|
||||||
|
@ -26,21 +26,21 @@ SECTIONS
|
||||||
{ *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
|
{ *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
|
||||||
.rela.rodata :
|
.rela.rodata :
|
||||||
{ *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
|
{ *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
|
||||||
.rel.got : { *(.rel.got) }
|
.rel.got : { *(.rel.got) }
|
||||||
.rela.got : { *(.rela.got) }
|
.rela.got : { *(.rela.got) }
|
||||||
.rel.ctors : { *(.rel.ctors) }
|
.rel.ctors : { *(.rel.ctors) }
|
||||||
.rela.ctors : { *(.rela.ctors) }
|
.rela.ctors : { *(.rela.ctors) }
|
||||||
.rel.dtors : { *(.rel.dtors) }
|
.rel.dtors : { *(.rel.dtors) }
|
||||||
.rela.dtors : { *(.rela.dtors) }
|
.rela.dtors : { *(.rela.dtors) }
|
||||||
.rel.init : { *(.rel.init) }
|
.rel.init : { *(.rel.init) }
|
||||||
.rela.init : { *(.rela.init) }
|
.rela.init : { *(.rela.init) }
|
||||||
.rel.fini : { *(.rel.fini) }
|
.rel.fini : { *(.rel.fini) }
|
||||||
.rela.fini : { *(.rela.fini) }
|
.rela.fini : { *(.rela.fini) }
|
||||||
.rel.bss : { *(.rel.bss) }
|
.rel.bss : { *(.rel.bss) }
|
||||||
.rela.bss : { *(.rela.bss) }
|
.rela.bss : { *(.rela.bss) }
|
||||||
.rel.plt : { *(.rel.plt) }
|
.rel.plt : { *(.rel.plt) }
|
||||||
.rela.plt : { *(.rela.plt) }
|
.rela.plt : { *(.rela.plt) }
|
||||||
.init : { *(.init) } =0x47ff041f
|
.init : { *(.init) } =0x47ff041f
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
*(.text)
|
*(.text)
|
||||||
|
@ -74,7 +74,7 @@ SECTIONS
|
||||||
{
|
{
|
||||||
*(.dtors)
|
*(.dtors)
|
||||||
}
|
}
|
||||||
.plt : { *(.plt) }
|
.plt : { *(.plt) }
|
||||||
.got : { *(.got.plt) *(.got) }
|
.got : { *(.got.plt) *(.got) }
|
||||||
.dynamic : { *(.dynamic) }
|
.dynamic : { *(.dynamic) }
|
||||||
/* We want the small data sections together, so single-instruction offsets
|
/* We want the small data sections together, so single-instruction offsets
|
||||||
|
|
48
sparc64.ld
48
sparc64.ld
|
@ -1,5 +1,5 @@
|
||||||
OUTPUT_FORMAT("elf64-sparc", "elf64-sparc",
|
OUTPUT_FORMAT("elf64-sparc", "elf64-sparc",
|
||||||
"elf64-sparc")
|
"elf64-sparc")
|
||||||
OUTPUT_ARCH(sparc:v9)
|
OUTPUT_ARCH(sparc:v9)
|
||||||
SEARCH_DIR(/lib64); SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib64); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib64); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/alpha-unknown-linux-gnu/lib);
|
SEARCH_DIR(/lib64); SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib64); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib64); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/alpha-unknown-linux-gnu/lib);
|
||||||
ENTRY(_start)
|
ENTRY(_start)
|
||||||
|
@ -7,13 +7,13 @@ SECTIONS
|
||||||
{
|
{
|
||||||
/* Read-only sections, merged into text segment: */
|
/* Read-only sections, merged into text segment: */
|
||||||
. = 0x60000000 + SIZEOF_HEADERS;
|
. = 0x60000000 + SIZEOF_HEADERS;
|
||||||
.interp : { *(.interp) }
|
.interp : { *(.interp) }
|
||||||
.hash : { *(.hash) }
|
.hash : { *(.hash) }
|
||||||
.dynsym : { *(.dynsym) }
|
.dynsym : { *(.dynsym) }
|
||||||
.dynstr : { *(.dynstr) }
|
.dynstr : { *(.dynstr) }
|
||||||
.gnu.version : { *(.gnu.version) }
|
.gnu.version : { *(.gnu.version) }
|
||||||
.gnu.version_d : { *(.gnu.version_d) }
|
.gnu.version_d : { *(.gnu.version_d) }
|
||||||
.gnu.version_r : { *(.gnu.version_r) }
|
.gnu.version_r : { *(.gnu.version_r) }
|
||||||
.rel.text :
|
.rel.text :
|
||||||
{ *(.rel.text) *(.rel.gnu.linkonce.t*) }
|
{ *(.rel.text) *(.rel.gnu.linkonce.t*) }
|
||||||
.rela.text :
|
.rela.text :
|
||||||
|
@ -26,21 +26,21 @@ SECTIONS
|
||||||
{ *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
|
{ *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
|
||||||
.rela.rodata :
|
.rela.rodata :
|
||||||
{ *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
|
{ *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
|
||||||
.rel.got : { *(.rel.got) }
|
.rel.got : { *(.rel.got) }
|
||||||
.rela.got : { *(.rela.got) }
|
.rela.got : { *(.rela.got) }
|
||||||
.rel.ctors : { *(.rel.ctors) }
|
.rel.ctors : { *(.rel.ctors) }
|
||||||
.rela.ctors : { *(.rela.ctors) }
|
.rela.ctors : { *(.rela.ctors) }
|
||||||
.rel.dtors : { *(.rel.dtors) }
|
.rel.dtors : { *(.rel.dtors) }
|
||||||
.rela.dtors : { *(.rela.dtors) }
|
.rela.dtors : { *(.rela.dtors) }
|
||||||
.rel.init : { *(.rel.init) }
|
.rel.init : { *(.rel.init) }
|
||||||
.rela.init : { *(.rela.init) }
|
.rela.init : { *(.rela.init) }
|
||||||
.rel.fini : { *(.rel.fini) }
|
.rel.fini : { *(.rel.fini) }
|
||||||
.rela.fini : { *(.rela.fini) }
|
.rela.fini : { *(.rela.fini) }
|
||||||
.rel.bss : { *(.rel.bss) }
|
.rel.bss : { *(.rel.bss) }
|
||||||
.rela.bss : { *(.rela.bss) }
|
.rela.bss : { *(.rela.bss) }
|
||||||
.rel.plt : { *(.rel.plt) }
|
.rel.plt : { *(.rel.plt) }
|
||||||
.rela.plt : { *(.rela.plt) }
|
.rela.plt : { *(.rela.plt) }
|
||||||
.init : { *(.init) } =0x47ff041f
|
.init : { *(.init) } =0x47ff041f
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
*(.text)
|
*(.text)
|
||||||
|
@ -82,7 +82,7 @@ SECTIONS
|
||||||
{
|
{
|
||||||
*(.dtors)
|
*(.dtors)
|
||||||
}
|
}
|
||||||
.plt : { *(.plt) }
|
.plt : { *(.plt) }
|
||||||
.got : { *(.got.plt) *(.got) }
|
.got : { *(.got.plt) *(.got) }
|
||||||
.dynamic : { *(.dynamic) }
|
.dynamic : { *(.dynamic) }
|
||||||
/* We want the small data sections together, so single-instruction offsets
|
/* We want the small data sections together, so single-instruction offsets
|
||||||
|
|
Loading…
Reference in New Issue