target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
028e2a7b87
commit
f97cfd596e
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@ -23,6 +23,151 @@ DEF_HELPER_FLAGS_3(sve_predtest, TCG_CALL_NO_WG, i32, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_pfirst, TCG_CALL_NO_WG, i32, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_pnext, TCG_CALL_NO_WG, i32, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_orr_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_orr_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_orr_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_orr_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_add_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_add_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_add_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_add_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_sub_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_sub_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_sub_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_sub_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smax_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smax_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smax_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smax_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umax_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umax_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umax_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umax_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smin_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smin_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smin_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smin_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umin_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umin_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umin_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umin_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_sabd_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_sabd_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_sabd_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_sabd_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_uabd_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_uabd_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_uabd_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_uabd_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_mul_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_mul_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_mul_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_mul_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smulh_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smulh_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smulh_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_smulh_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umulh_zpzz_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umulh_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umulh_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_umulh_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_sdiv_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_sdiv_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_udiv_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_udiv_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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@ -24,6 +24,10 @@
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%imm9_16_10 16:s6 10:3
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# Either a copy of rd (at bit 0), or a different source
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# as propagated via the MOVPRFX instruction.
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%reg_movprfx 0:5
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###########################################################################
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# Named attribute sets. These are used to make nice(er) names
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# when creating helpers common to those for the individual
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@ -33,6 +37,7 @@
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&rri rd rn imm
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&rrr_esz rd rn rm esz
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&rprr_s rd pg rn rm s
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&rprr_esz rd pg rn rm esz
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###########################################################################
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# Named instruction formats. These are generally used to
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@ -50,6 +55,12 @@
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# Three predicate operand, with governing predicate, flag setting
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@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
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# Two register operand, with governing predicate, vector element size
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@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
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&rprr_esz rn=%reg_movprfx
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@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
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&rprr_esz rm=%reg_movprfx
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# Basic Load/Store with 9-bit immediate offset
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@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
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&rri imm=%imm9_16_10
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@ -59,6 +70,37 @@
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###########################################################################
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# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
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### SVE Integer Arithmetic - Binary Predicated Group
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# SVE bitwise logical vector operations (predicated)
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ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
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EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
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AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
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BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
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# SVE integer add/subtract vectors (predicated)
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ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
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SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
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SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
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# SVE integer min/max/difference (predicated)
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SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
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UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
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SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
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UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
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SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
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UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
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# SVE integer multiply/divide (predicated)
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MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
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SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
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UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
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# Note that divide requires size >= 2; below 2 is unallocated.
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SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
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UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
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SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
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UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
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### SVE Logical - Unpredicated Group
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# SVE bitwise logical operations (unpredicated)
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@ -25,6 +25,22 @@
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#include "tcg/tcg-gvec-desc.h"
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/* Note that vector data is stored in host-endian 64-bit chunks,
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so addressing units smaller than that needs a host-endian fixup. */
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#ifdef HOST_WORDS_BIGENDIAN
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#define H1(x) ((x) ^ 7)
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#define H1_2(x) ((x) ^ 6)
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#define H1_4(x) ((x) ^ 4)
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#define H2(x) ((x) ^ 3)
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#define H4(x) ((x) ^ 1)
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#else
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#define H1(x) (x)
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#define H1_2(x) (x)
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#define H1_4(x) (x)
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#define H2(x) (x)
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#define H4(x) (x)
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#endif
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/* Return a value for NZCV as per the ARM PredTest pseudofunction.
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*
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* The return value has bit 31 set if N is set, bit 1 set if Z is clear,
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@ -116,6 +132,184 @@ LOGICAL_PPPP(sve_nand_pppp, DO_NAND)
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#undef DO_SEL
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#undef LOGICAL_PPPP
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/* Fully general three-operand expander, controlled by a predicate.
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* This is complicated by the host-endian storage of the register file.
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*/
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/* ??? I don't expect the compiler could ever vectorize this itself.
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* With some tables we can convert bit masks to byte masks, and with
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* extra care wrt byte/word ordering we could use gcc generic vectors
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* and do 16 bytes at a time.
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*/
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#define DO_ZPZZ(NAME, TYPE, H, OP) \
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void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \
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{ \
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intptr_t i, opr_sz = simd_oprsz(desc); \
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for (i = 0; i < opr_sz; ) { \
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
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do { \
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if (pg & 1) { \
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TYPE nn = *(TYPE *)(vn + H(i)); \
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TYPE mm = *(TYPE *)(vm + H(i)); \
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*(TYPE *)(vd + H(i)) = OP(nn, mm); \
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} \
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i += sizeof(TYPE), pg >>= sizeof(TYPE); \
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} while (i & 15); \
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} \
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}
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/* Similarly, specialized for 64-bit operands. */
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#define DO_ZPZZ_D(NAME, TYPE, OP) \
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void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \
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{ \
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intptr_t i, opr_sz = simd_oprsz(desc) / 8; \
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TYPE *d = vd, *n = vn, *m = vm; \
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uint8_t *pg = vg; \
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for (i = 0; i < opr_sz; i += 1) { \
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if (pg[H1(i)] & 1) { \
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TYPE nn = n[i], mm = m[i]; \
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d[i] = OP(nn, mm); \
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} \
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} \
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}
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#define DO_AND(N, M) (N & M)
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#define DO_EOR(N, M) (N ^ M)
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#define DO_ORR(N, M) (N | M)
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#define DO_BIC(N, M) (N & ~M)
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#define DO_ADD(N, M) (N + M)
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#define DO_SUB(N, M) (N - M)
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#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
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#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
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#define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N))
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#define DO_MUL(N, M) (N * M)
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#define DO_DIV(N, M) (M ? N / M : 0)
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DO_ZPZZ(sve_and_zpzz_b, uint8_t, H1, DO_AND)
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DO_ZPZZ(sve_and_zpzz_h, uint16_t, H1_2, DO_AND)
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DO_ZPZZ(sve_and_zpzz_s, uint32_t, H1_4, DO_AND)
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DO_ZPZZ_D(sve_and_zpzz_d, uint64_t, DO_AND)
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DO_ZPZZ(sve_orr_zpzz_b, uint8_t, H1, DO_ORR)
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DO_ZPZZ(sve_orr_zpzz_h, uint16_t, H1_2, DO_ORR)
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DO_ZPZZ(sve_orr_zpzz_s, uint32_t, H1_4, DO_ORR)
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DO_ZPZZ_D(sve_orr_zpzz_d, uint64_t, DO_ORR)
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DO_ZPZZ(sve_eor_zpzz_b, uint8_t, H1, DO_EOR)
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||||
DO_ZPZZ(sve_eor_zpzz_h, uint16_t, H1_2, DO_EOR)
|
||||
DO_ZPZZ(sve_eor_zpzz_s, uint32_t, H1_4, DO_EOR)
|
||||
DO_ZPZZ_D(sve_eor_zpzz_d, uint64_t, DO_EOR)
|
||||
|
||||
DO_ZPZZ(sve_bic_zpzz_b, uint8_t, H1, DO_BIC)
|
||||
DO_ZPZZ(sve_bic_zpzz_h, uint16_t, H1_2, DO_BIC)
|
||||
DO_ZPZZ(sve_bic_zpzz_s, uint32_t, H1_4, DO_BIC)
|
||||
DO_ZPZZ_D(sve_bic_zpzz_d, uint64_t, DO_BIC)
|
||||
|
||||
DO_ZPZZ(sve_add_zpzz_b, uint8_t, H1, DO_ADD)
|
||||
DO_ZPZZ(sve_add_zpzz_h, uint16_t, H1_2, DO_ADD)
|
||||
DO_ZPZZ(sve_add_zpzz_s, uint32_t, H1_4, DO_ADD)
|
||||
DO_ZPZZ_D(sve_add_zpzz_d, uint64_t, DO_ADD)
|
||||
|
||||
DO_ZPZZ(sve_sub_zpzz_b, uint8_t, H1, DO_SUB)
|
||||
DO_ZPZZ(sve_sub_zpzz_h, uint16_t, H1_2, DO_SUB)
|
||||
DO_ZPZZ(sve_sub_zpzz_s, uint32_t, H1_4, DO_SUB)
|
||||
DO_ZPZZ_D(sve_sub_zpzz_d, uint64_t, DO_SUB)
|
||||
|
||||
DO_ZPZZ(sve_smax_zpzz_b, int8_t, H1, DO_MAX)
|
||||
DO_ZPZZ(sve_smax_zpzz_h, int16_t, H1_2, DO_MAX)
|
||||
DO_ZPZZ(sve_smax_zpzz_s, int32_t, H1_4, DO_MAX)
|
||||
DO_ZPZZ_D(sve_smax_zpzz_d, int64_t, DO_MAX)
|
||||
|
||||
DO_ZPZZ(sve_umax_zpzz_b, uint8_t, H1, DO_MAX)
|
||||
DO_ZPZZ(sve_umax_zpzz_h, uint16_t, H1_2, DO_MAX)
|
||||
DO_ZPZZ(sve_umax_zpzz_s, uint32_t, H1_4, DO_MAX)
|
||||
DO_ZPZZ_D(sve_umax_zpzz_d, uint64_t, DO_MAX)
|
||||
|
||||
DO_ZPZZ(sve_smin_zpzz_b, int8_t, H1, DO_MIN)
|
||||
DO_ZPZZ(sve_smin_zpzz_h, int16_t, H1_2, DO_MIN)
|
||||
DO_ZPZZ(sve_smin_zpzz_s, int32_t, H1_4, DO_MIN)
|
||||
DO_ZPZZ_D(sve_smin_zpzz_d, int64_t, DO_MIN)
|
||||
|
||||
DO_ZPZZ(sve_umin_zpzz_b, uint8_t, H1, DO_MIN)
|
||||
DO_ZPZZ(sve_umin_zpzz_h, uint16_t, H1_2, DO_MIN)
|
||||
DO_ZPZZ(sve_umin_zpzz_s, uint32_t, H1_4, DO_MIN)
|
||||
DO_ZPZZ_D(sve_umin_zpzz_d, uint64_t, DO_MIN)
|
||||
|
||||
DO_ZPZZ(sve_sabd_zpzz_b, int8_t, H1, DO_ABD)
|
||||
DO_ZPZZ(sve_sabd_zpzz_h, int16_t, H1_2, DO_ABD)
|
||||
DO_ZPZZ(sve_sabd_zpzz_s, int32_t, H1_4, DO_ABD)
|
||||
DO_ZPZZ_D(sve_sabd_zpzz_d, int64_t, DO_ABD)
|
||||
|
||||
DO_ZPZZ(sve_uabd_zpzz_b, uint8_t, H1, DO_ABD)
|
||||
DO_ZPZZ(sve_uabd_zpzz_h, uint16_t, H1_2, DO_ABD)
|
||||
DO_ZPZZ(sve_uabd_zpzz_s, uint32_t, H1_4, DO_ABD)
|
||||
DO_ZPZZ_D(sve_uabd_zpzz_d, uint64_t, DO_ABD)
|
||||
|
||||
/* Because the computation type is at least twice as large as required,
|
||||
these work for both signed and unsigned source types. */
|
||||
static inline uint8_t do_mulh_b(int32_t n, int32_t m)
|
||||
{
|
||||
return (n * m) >> 8;
|
||||
}
|
||||
|
||||
static inline uint16_t do_mulh_h(int32_t n, int32_t m)
|
||||
{
|
||||
return (n * m) >> 16;
|
||||
}
|
||||
|
||||
static inline uint32_t do_mulh_s(int64_t n, int64_t m)
|
||||
{
|
||||
return (n * m) >> 32;
|
||||
}
|
||||
|
||||
static inline uint64_t do_smulh_d(uint64_t n, uint64_t m)
|
||||
{
|
||||
uint64_t lo, hi;
|
||||
muls64(&lo, &hi, n, m);
|
||||
return hi;
|
||||
}
|
||||
|
||||
static inline uint64_t do_umulh_d(uint64_t n, uint64_t m)
|
||||
{
|
||||
uint64_t lo, hi;
|
||||
mulu64(&lo, &hi, n, m);
|
||||
return hi;
|
||||
}
|
||||
|
||||
DO_ZPZZ(sve_mul_zpzz_b, uint8_t, H1, DO_MUL)
|
||||
DO_ZPZZ(sve_mul_zpzz_h, uint16_t, H1_2, DO_MUL)
|
||||
DO_ZPZZ(sve_mul_zpzz_s, uint32_t, H1_4, DO_MUL)
|
||||
DO_ZPZZ_D(sve_mul_zpzz_d, uint64_t, DO_MUL)
|
||||
|
||||
DO_ZPZZ(sve_smulh_zpzz_b, int8_t, H1, do_mulh_b)
|
||||
DO_ZPZZ(sve_smulh_zpzz_h, int16_t, H1_2, do_mulh_h)
|
||||
DO_ZPZZ(sve_smulh_zpzz_s, int32_t, H1_4, do_mulh_s)
|
||||
DO_ZPZZ_D(sve_smulh_zpzz_d, uint64_t, do_smulh_d)
|
||||
|
||||
DO_ZPZZ(sve_umulh_zpzz_b, uint8_t, H1, do_mulh_b)
|
||||
DO_ZPZZ(sve_umulh_zpzz_h, uint16_t, H1_2, do_mulh_h)
|
||||
DO_ZPZZ(sve_umulh_zpzz_s, uint32_t, H1_4, do_mulh_s)
|
||||
DO_ZPZZ_D(sve_umulh_zpzz_d, uint64_t, do_umulh_d)
|
||||
|
||||
DO_ZPZZ(sve_sdiv_zpzz_s, int32_t, H1_4, DO_DIV)
|
||||
DO_ZPZZ_D(sve_sdiv_zpzz_d, int64_t, DO_DIV)
|
||||
|
||||
DO_ZPZZ(sve_udiv_zpzz_s, uint32_t, H1_4, DO_DIV)
|
||||
DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_DIV)
|
||||
|
||||
#undef DO_ZPZZ
|
||||
#undef DO_ZPZZ_D
|
||||
#undef DO_AND
|
||||
#undef DO_ORR
|
||||
#undef DO_EOR
|
||||
#undef DO_BIC
|
||||
#undef DO_ADD
|
||||
#undef DO_SUB
|
||||
#undef DO_MAX
|
||||
#undef DO_MIN
|
||||
#undef DO_ABD
|
||||
#undef DO_MUL
|
||||
#undef DO_DIV
|
||||
|
||||
/* Similar to the ARM LastActiveElement pseudocode function, except the
|
||||
result is multiplied by the element size. This includes the not found
|
||||
indication; e.g. not found for esz=3 is -8. */
|
||||
|
|
|
|||
|
|
@ -227,6 +227,74 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
|
|||
return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
|
||||
}
|
||||
|
||||
/*
|
||||
*** SVE Integer Arithmetic - Binary Predicated Group
|
||||
*/
|
||||
|
||||
static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
|
||||
{
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
if (fn == NULL) {
|
||||
return false;
|
||||
}
|
||||
if (sve_access_check(s)) {
|
||||
tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
vec_full_reg_offset(s, a->rm),
|
||||
pred_full_reg_offset(s, a->pg),
|
||||
vsz, vsz, 0, fn);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
#define DO_ZPZZ(NAME, name) \
|
||||
static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a, \
|
||||
uint32_t insn) \
|
||||
{ \
|
||||
static gen_helper_gvec_4 * const fns[4] = { \
|
||||
gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \
|
||||
gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \
|
||||
}; \
|
||||
return do_zpzz_ool(s, a, fns[a->esz]); \
|
||||
}
|
||||
|
||||
DO_ZPZZ(AND, and)
|
||||
DO_ZPZZ(EOR, eor)
|
||||
DO_ZPZZ(ORR, orr)
|
||||
DO_ZPZZ(BIC, bic)
|
||||
|
||||
DO_ZPZZ(ADD, add)
|
||||
DO_ZPZZ(SUB, sub)
|
||||
|
||||
DO_ZPZZ(SMAX, smax)
|
||||
DO_ZPZZ(UMAX, umax)
|
||||
DO_ZPZZ(SMIN, smin)
|
||||
DO_ZPZZ(UMIN, umin)
|
||||
DO_ZPZZ(SABD, sabd)
|
||||
DO_ZPZZ(UABD, uabd)
|
||||
|
||||
DO_ZPZZ(MUL, mul)
|
||||
DO_ZPZZ(SMULH, smulh)
|
||||
DO_ZPZZ(UMULH, umulh)
|
||||
|
||||
static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
|
||||
{
|
||||
static gen_helper_gvec_4 * const fns[4] = {
|
||||
NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
|
||||
};
|
||||
return do_zpzz_ool(s, a, fns[a->esz]);
|
||||
}
|
||||
|
||||
static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
|
||||
{
|
||||
static gen_helper_gvec_4 * const fns[4] = {
|
||||
NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
|
||||
};
|
||||
return do_zpzz_ool(s, a, fns[a->esz]);
|
||||
}
|
||||
|
||||
#undef DO_ZPZZ
|
||||
|
||||
/*
|
||||
*** SVE Predicate Logical Operations Group
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue