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x86: ioapic: ignore level irq during processing

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For level triggered interrupts, we will get Remote IRR bit cleared after
guest kernel finished processing specific request. Before that, we
should ignore the same interrupt from triggering again.

Signed-off-by: Peter Xu <peterx@redhat.com>
Message-Id: <1469974685-4144-1-git-send-email-peterx@redhat.com>
[Push new "if" up so that it covers KVM split irqchip as well. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Peter Xu 2016-07-31 22:18:05 +08:00 committed by Paolo Bonzini
parent 7298d4fd51
commit f99b86b949
1 changed files with 9 additions and 5 deletions
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14
hw/intc/ioapic.c
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@ -117,21 +117,25 @@ static void ioapic_service(IOAPICCommonState *s)
s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
}
if (coalesce) {
/* We are level triggered interrupts, and the
* guest should be still working on previous one,
* so skip it. */
continue;
}
#ifdef CONFIG_KVM
if (kvm_irqchip_is_split()) {
if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
kvm_set_irq(kvm_state, i, 1);
kvm_set_irq(kvm_state, i, 0);
} else {
if (!coalesce) {
kvm_set_irq(kvm_state, i, 1);
}
kvm_set_irq(kvm_state, i, 1);
}
continue;
}
#else
(void)coalesce;
#endif
/* No matter whether IR is enabled, we translate
* the IOAPIC message into a MSI one, and its
* address space will decide whether we need a