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target-mips: fix conditional moves off fp condition codes

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Conditional moves off fp condition codes were using the result of
get_fp_bit to isolate and test the relevant condition code.  However,
get_fp_bit returns the bit number of the condition code, not a
bitmask.  (Compare the use of get_fp_bit in gen_compute_branch1, for
instance.)

Fixed by shifting a bitmask into place using the result of get_fp_bit in
the relevant functions (gen_mov{ci,cf_s,cf_d,cf_ps}).

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Nathan Froyd 2009-08-25 08:20:00 -07:00 committed by Aurelien Jarno
parent 4e6f6d4c20
commit fa31af0e63
1 changed files with 5 additions and 5 deletions
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10
target-mips/translate.c
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@ -5896,7 +5896,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
l1 = gen_new_label();
t0 = tcg_temp_new_i32();
tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
tcg_temp_free_i32(t0);
if (rs == 0) {
@ -5918,7 +5918,7 @@ static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
else
cond = TCG_COND_NE;
tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
gen_load_fpr32(t0, fs);
gen_store_fpr32(t0, fd);
@ -5938,7 +5938,7 @@ static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int t
else
cond = TCG_COND_NE;
tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
tcg_temp_free_i32(t0);
fp0 = tcg_temp_new_i64();
@ -5960,13 +5960,13 @@ static inline void gen_movcf_ps (int fs, int fd, int cc, int tf)
else
cond = TCG_COND_NE;
tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
gen_load_fpr32(t0, fs);
gen_store_fpr32(t0, fd);
gen_set_label(l1);
tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc+1));
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1));
tcg_gen_brcondi_i32(cond, t0, 0, l2);
gen_load_fpr32h(t0, fs);
gen_store_fpr32h(t0, fd);