tests/tcg: i386: add MMX and 3DNow! tests
Adjust the test-avx.py generator to produce tests specifically for MMX and 3DNow. Using a separate generator introduces some code duplication, but is a simpler approach because of test-avx's extra complexity to support 3- and 4-operand AVX instructions. If needed, a common library can be introduced later. While at it, for consistency move all the -cpu max rules to the same place. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
4ce4a1a714
commit
fa7ce0b028
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@ -7,8 +7,8 @@ VPATH += $(I386_SRC)
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I386_SRCS=$(notdir $(wildcard $(I386_SRC)/*.c))
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ALL_X86_TESTS=$(I386_SRCS:.c=)
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SKIP_I386_TESTS=test-i386-ssse3 test-avx
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X86_64_TESTS:=$(filter test-i386-bmi2 test-i386-ssse3 test-avx, $(ALL_X86_TESTS))
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SKIP_I386_TESTS=test-i386-ssse3 test-avx test-3dnow test-mmx
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X86_64_TESTS:=$(filter test-i386-bmi2 $(SKIP_I386_TESTS), $(ALL_X86_TESTS))
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test-i386-sse-exceptions: CFLAGS += -msse4.1 -mfpmath=sse
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run-test-i386-sse-exceptions: QEMU_OPTS += -cpu max
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@ -82,9 +82,27 @@ run-plugin-sha512-sse-with-%: QEMU_OPTS+=-cpu max
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TESTS+=sha512-sse
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CLEANFILES += test-avx.h
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CLEANFILES += test-avx.h test-mmx.h test-3dnow.h
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test-3dnow.h: test-mmx.py x86.csv
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$(PYTHON) $(I386_SRC)/test-mmx.py $(I386_SRC)/x86.csv $@ 3DNOW
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test-mmx.h: test-mmx.py x86.csv
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$(PYTHON) $(I386_SRC)/test-mmx.py $(I386_SRC)/x86.csv $@ MMX SSE SSE2 SSE3 SSSE3
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test-avx.h: test-avx.py x86.csv
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$(PYTHON) $(I386_SRC)/test-avx.py $(I386_SRC)/x86.csv $@
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test-3dnow: CFLAGS += -masm=intel -O -I.
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run-test-3dnow: QEMU_OPTS += -cpu max
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run-plugin-test-3dnow: QEMU_OPTS += -cpu max
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test-3dnow: test-3dnow.h
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test-mmx: CFLAGS += -masm=intel -O -I.
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run-test-mmx: QEMU_OPTS += -cpu max
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run-plugin-test-mmx: QEMU_OPTS += -cpu max
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test-mmx: test-mmx.h
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test-avx: CFLAGS += -masm=intel -O -I.
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run-test-avx: QEMU_OPTS += -cpu max
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run-plugin-test-avx: QEMU_OPTS += -cpu max
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test-avx: test-avx.h
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@ -0,0 +1,3 @@
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#define EMMS "femms"
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#define TEST_FILE "test-3dnow.h"
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#include "test-mmx.c"
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@ -7,7 +7,6 @@ import sys
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from fnmatch import fnmatch
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archs = [
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# TODO: MMX?
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"SSE", "SSE2", "SSE3", "SSSE3", "SSE4_1", "SSE4_2",
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]
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@ -0,0 +1,315 @@
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#ifndef TEST_FILE
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#define TEST_FILE "test-mmx.h"
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#endif
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#ifndef EMMS
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#define EMMS "emms"
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#endif
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typedef void (*testfn)(void);
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typedef struct {
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uint64_t q0, q1;
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} __attribute__((aligned(16))) v2di;
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typedef struct {
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uint64_t mm[8];
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v2di xmm[8];
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uint64_t r[16];
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uint64_t flags;
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uint32_t ff;
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uint64_t pad;
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v2di mem[4];
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v2di mem0[4];
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} reg_state;
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typedef struct {
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int n;
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testfn fn;
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const char *s;
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reg_state *init;
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} TestDef;
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reg_state initI;
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reg_state initF32;
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reg_state initF64;
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static void dump_mmx(int n, const uint64_t *r, int ff)
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{
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if (ff == 32) {
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float v[2];
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memcpy(v, r, sizeof(v));
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printf("MM%d = %016lx %8g %8g\n", n, *r, v[1], v[0]);
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} else {
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printf("MM%d = %016lx\n", n, *r);
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}
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}
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static void dump_xmm(const char *name, int n, const v2di *r, int ff)
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{
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printf("%s%d = %016lx %016lx\n",
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name, n, r->q1, r->q0);
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if (ff == 32) {
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float v[4];
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memcpy(v, r, sizeof(v));
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printf(" %8g %8g %8g %8g\n",
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v[3], v[2], v[1], v[0]);
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}
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}
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static void dump_regs(reg_state *s, int ff)
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{
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int i;
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for (i = 0; i < 8; i++) {
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dump_mmx(i, &s->mm[i], ff);
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}
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for (i = 0; i < 4; i++) {
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dump_xmm("mem", i, &s->mem0[i], 0);
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}
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}
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static void compare_state(const reg_state *a, const reg_state *b)
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{
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int i;
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for (i = 0; i < 8; i++) {
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if (a->mm[i] != b->mm[i]) {
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printf("MM%d = %016lx\n", i, b->mm[i]);
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}
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}
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for (i = 0; i < 16; i++) {
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if (a->r[i] != b->r[i]) {
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printf("r%d = %016lx\n", i, b->r[i]);
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}
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}
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for (i = 0; i < 8; i++) {
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if (memcmp(&a->xmm[i], &b->xmm[i], 8)) {
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dump_xmm("xmm", i, &b->xmm[i], a->ff);
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}
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}
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for (i = 0; i < 4; i++) {
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if (memcmp(&a->mem0[i], &a->mem[i], 16)) {
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dump_xmm("mem", i, &a->mem[i], a->ff);
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}
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}
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if (a->flags != b->flags) {
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printf("FLAGS = %016lx\n", b->flags);
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}
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}
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#define LOADMM(r, o) "movq " #r ", " #o "[%0]\n\t"
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#define LOADXMM(r, o) "movdqa " #r ", " #o "[%0]\n\t"
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#define STOREMM(r, o) "movq " #o "[%1], " #r "\n\t"
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#define STOREXMM(r, o) "movdqa " #o "[%1], " #r "\n\t"
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#define MMREG(F) \
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F(mm0, 0x00) \
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F(mm1, 0x08) \
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F(mm2, 0x10) \
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F(mm3, 0x18) \
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F(mm4, 0x20) \
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F(mm5, 0x28) \
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F(mm6, 0x30) \
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F(mm7, 0x38)
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#define XMMREG(F) \
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F(xmm0, 0x040) \
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F(xmm1, 0x050) \
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F(xmm2, 0x060) \
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F(xmm3, 0x070) \
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F(xmm4, 0x080) \
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F(xmm5, 0x090) \
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F(xmm6, 0x0a0) \
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F(xmm7, 0x0b0)
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#define LOADREG(r, o) "mov " #r ", " #o "[rax]\n\t"
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#define STOREREG(r, o) "mov " #o "[rax], " #r "\n\t"
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#define REG(F) \
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F(rbx, 0xc8) \
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F(rcx, 0xd0) \
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F(rdx, 0xd8) \
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F(rsi, 0xe0) \
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F(rdi, 0xe8) \
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F(r8, 0x100) \
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F(r9, 0x108) \
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F(r10, 0x110) \
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F(r11, 0x118) \
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F(r12, 0x120) \
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F(r13, 0x128) \
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F(r14, 0x130) \
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F(r15, 0x138) \
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static void run_test(const TestDef *t)
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{
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reg_state result;
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reg_state *init = t->init;
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memcpy(init->mem, init->mem0, sizeof(init->mem));
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printf("%5d %s\n", t->n, t->s);
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asm volatile(
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MMREG(LOADMM)
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XMMREG(LOADXMM)
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"sub rsp, 128\n\t"
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"push rax\n\t"
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"push rbx\n\t"
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"push rcx\n\t"
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"push rdx\n\t"
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"push %1\n\t"
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"push %2\n\t"
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"mov rax, %0\n\t"
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"pushf\n\t"
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"pop rbx\n\t"
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"shr rbx, 8\n\t"
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"shl rbx, 8\n\t"
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"mov rcx, 0x140[rax]\n\t"
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"and rcx, 0xff\n\t"
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"or rbx, rcx\n\t"
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"push rbx\n\t"
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"popf\n\t"
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REG(LOADREG)
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"mov rax, 0xc0[rax]\n\t"
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"call [rsp]\n\t"
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"mov [rsp], rax\n\t"
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"mov rax, 8[rsp]\n\t"
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REG(STOREREG)
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"mov rbx, [rsp]\n\t"
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"mov 0xc0[rax], rbx\n\t"
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"mov rbx, 0\n\t"
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"mov 0xf0[rax], rbx\n\t"
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"mov 0xf8[rax], rbx\n\t"
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"pushf\n\t"
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"pop rbx\n\t"
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"and rbx, 0xff\n\t"
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"mov 0x140[rax], rbx\n\t"
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"add rsp, 16\n\t"
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"pop rdx\n\t"
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"pop rcx\n\t"
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"pop rbx\n\t"
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"pop rax\n\t"
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"add rsp, 128\n\t"
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MMREG(STOREMM)
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EMMS "\n\t"
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XMMREG(STOREXMM)
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: : "r"(init), "r"(&result), "r"(t->fn)
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: "memory", "cc",
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"rsi", "rdi",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
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"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5",
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"xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11",
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"xmm12", "xmm13", "xmm14", "xmm15"
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);
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compare_state(init, &result);
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}
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#define TEST(n, cmd, type) \
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static void __attribute__((naked)) test_##n(void) \
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{ \
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asm volatile(cmd); \
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asm volatile("ret"); \
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}
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#include TEST_FILE
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static const TestDef test_table[] = {
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#define TEST(n, cmd, type) {n, test_##n, cmd, &init##type},
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#include TEST_FILE
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{-1, NULL, "", NULL}
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};
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static void run_all(void)
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{
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const TestDef *t;
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for (t = test_table; t->fn; t++) {
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run_test(t);
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}
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}
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#define ARRAY_LEN(x) (sizeof(x) / sizeof(x[0]))
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float val_f32[] = {2.0, -1.0, 4.8, 0.8, 3, -42.0, 5e6, 7.5, 8.3};
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uint64_t val_i64[] = {
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0x3d6b3b6a9e4118f2lu, 0x355ae76d2774d78clu,
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0xd851c54a56bf1f29lu, 0x4a84d1d50bf4c4fflu,
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0x5826475e2c5fd799lu, 0xfd32edc01243f5e9lu,
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};
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v2di deadbeef = {0xa5a5a5a5deadbeefull, 0xa5a5a5a5deadbeefull};
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void init_f32reg(uint64_t *r)
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{
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static int n;
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float v[2];
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int i;
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for (i = 0; i < 2; i++) {
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v[i] = val_f32[n++];
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if (n == ARRAY_LEN(val_f32)) {
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n = 0;
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}
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}
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memcpy(r, v, sizeof(*r));
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}
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void init_intreg(uint64_t *r)
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{
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static uint64_t mask;
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static int n;
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*r = val_i64[n] ^ mask;
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n++;
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if (n == ARRAY_LEN(val_i64)) {
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n = 0;
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mask *= 0x104C11DB7;
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}
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}
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static void init_all(reg_state *s)
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{
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int i;
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for (i = 0; i < 16; i++) {
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init_intreg(&s->r[i]);
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}
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s->r[3] = (uint64_t)&s->mem[0]; /* rdx */
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s->r[5] = (uint64_t)&s->mem[2]; /* rdi */
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s->r[6] = 0;
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s->r[7] = 0;
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s->flags = 2;
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for (i = 0; i < 8; i++) {
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s->xmm[i] = deadbeef;
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memcpy(&s->mm[i], &s->xmm[i], sizeof(s->mm[i]));
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}
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for (i = 0; i < 2; i++) {
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s->mem0[i] = deadbeef;
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}
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}
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int main(int argc, char *argv[])
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{
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init_all(&initI);
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init_intreg(&initI.mm[5]);
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init_intreg(&initI.mm[6]);
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init_intreg(&initI.mm[7]);
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init_intreg(&initI.mem0[1].q0);
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init_intreg(&initI.mem0[1].q1);
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printf("Int:\n");
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dump_regs(&initI, 0);
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init_all(&initF32);
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init_f32reg(&initF32.mm[5]);
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init_f32reg(&initF32.mm[6]);
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init_f32reg(&initF32.mm[7]);
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init_f32reg(&initF32.mem0[1].q0);
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init_f32reg(&initF32.mem0[1].q1);
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initF32.ff = 32;
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printf("F32:\n");
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dump_regs(&initF32, 32);
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if (argc > 1) {
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int n = atoi(argv[1]);
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run_test(&test_table[n]);
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} else {
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run_all();
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}
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return 0;
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}
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@ -0,0 +1,244 @@
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#! /usr/bin/env python3
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# Generate test-avx.h from x86.csv
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import csv
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import sys
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from fnmatch import fnmatch
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ignore = set(["EMMS", "FEMMS", "FISTTP",
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"LDMXCSR", "VLDMXCSR", "STMXCSR", "VSTMXCSR"])
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imask = {
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'PALIGNR': 0x3f,
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'PEXTRB': 0x0f,
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'PEXTRW': 0x07,
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'PEXTRD': 0x03,
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'PEXTRQ': 0x01,
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'PINSRB': 0x0f,
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'PINSRW': 0x07,
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'PINSRD': 0x03,
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'PINSRQ': 0x01,
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'PSHUF[DW]': 0xff,
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'PSHUF[LH]W': 0xff,
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'PS[LR][AL][WDQ]': 0x3f,
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}
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def strip_comments(x):
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for l in x:
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if l != '' and l[0] != '#':
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yield l
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def reg_w(w):
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if w == 8:
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return 'al'
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elif w == 16:
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return 'ax'
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elif w == 32:
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return 'eax'
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elif w == 64:
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return 'rax'
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raise Exception("bad reg_w %d" % w)
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def mem_w(w):
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if w == 8:
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t = "BYTE"
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elif w == 16:
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t = "WORD"
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elif w == 32:
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t = "DWORD"
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elif w == 64:
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t = "QWORD"
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else:
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raise Exception()
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return t + " PTR 32[rdx]"
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class MMArg():
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isxmm = True
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def __init__(self, mw):
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if mw not in [0, 32, 64]:
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raise Exception("Bad /m width: %s" % w)
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self.mw = mw
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self.ismem = mw != 0
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def regstr(self, n):
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if n < 0:
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return mem_w(self.mw)
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else:
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return "mm%d" % (n, )
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||||
def match(op, pattern):
|
||||
return fnmatch(op, pattern)
|
||||
|
||||
class ArgImm8u():
|
||||
isxmm = False
|
||||
ismem = False
|
||||
def __init__(self, op):
|
||||
for k, v in imask.items():
|
||||
if match(op, k):
|
||||
self.mask = imask[k];
|
||||
return
|
||||
raise Exception("Unknown immediate")
|
||||
def vals(self):
|
||||
mask = self.mask
|
||||
yield 0
|
||||
n = 0
|
||||
while n != mask:
|
||||
n += 1
|
||||
while (n & ~mask) != 0:
|
||||
n += (n & ~mask)
|
||||
yield n
|
||||
|
||||
class ArgRM():
|
||||
isxmm = False
|
||||
def __init__(self, rw, mw):
|
||||
if rw not in [8, 16, 32, 64]:
|
||||
raise Exception("Bad r/w width: %s" % w)
|
||||
if mw not in [0, 8, 16, 32, 64]:
|
||||
raise Exception("Bad r/w width: %s" % w)
|
||||
self.rw = rw
|
||||
self.mw = mw
|
||||
self.ismem = mw != 0
|
||||
def regstr(self, n):
|
||||
if n < 0:
|
||||
return mem_w(self.mw)
|
||||
else:
|
||||
return reg_w(self.rw)
|
||||
|
||||
class ArgMem():
|
||||
isxmm = False
|
||||
ismem = True
|
||||
def __init__(self, w):
|
||||
if w not in [8, 16, 32, 64, 128, 256]:
|
||||
raise Exception("Bad mem width: %s" % w)
|
||||
self.w = w
|
||||
def regstr(self, n):
|
||||
return mem_w(self.w)
|
||||
|
||||
class SkipInstruction(Exception):
|
||||
pass
|
||||
|
||||
def ArgGenerator(arg, op):
|
||||
if arg[:2] == 'mm':
|
||||
if "/" in arg:
|
||||
r, m = arg.split('/')
|
||||
if (m[0] != 'm'):
|
||||
raise Exception("Expected /m: %s", arg)
|
||||
return MMArg(int(m[1:]));
|
||||
else:
|
||||
return MMArg(0);
|
||||
elif arg[:4] == 'imm8':
|
||||
return ArgImm8u(op);
|
||||
elif arg[0] == 'r':
|
||||
if '/m' in arg:
|
||||
r, m = arg.split('/')
|
||||
if (m[0] != 'm'):
|
||||
raise Exception("Expected /m: %s", arg)
|
||||
mw = int(m[1:])
|
||||
if r == 'r':
|
||||
rw = mw
|
||||
else:
|
||||
rw = int(r[1:])
|
||||
return ArgRM(rw, mw)
|
||||
|
||||
return ArgRM(int(arg[1:]), 0);
|
||||
elif arg[0] == 'm':
|
||||
return ArgMem(int(arg[1:]))
|
||||
else:
|
||||
raise SkipInstruction
|
||||
|
||||
class InsnGenerator:
|
||||
def __init__(self, op, args):
|
||||
self.op = op
|
||||
if op[0:2] == "PF":
|
||||
self.optype = 'F32'
|
||||
else:
|
||||
self.optype = 'I'
|
||||
|
||||
try:
|
||||
self.args = list(ArgGenerator(a, op) for a in args)
|
||||
if len(self.args) > 0 and self.args[-1] is None:
|
||||
self.args = self.args[:-1]
|
||||
except SkipInstruction:
|
||||
raise
|
||||
except Exception as e:
|
||||
raise Exception("Bad arg %s: %s" % (op, e))
|
||||
|
||||
def gen(self):
|
||||
regs = (5, 6, 7)
|
||||
dest = 4
|
||||
|
||||
nreg = len(self.args)
|
||||
if nreg == 0:
|
||||
yield self.op
|
||||
return
|
||||
if isinstance(self.args[-1], ArgImm8u):
|
||||
nreg -= 1
|
||||
immarg = self.args[-1]
|
||||
else:
|
||||
immarg = None
|
||||
memarg = -1
|
||||
for n, arg in enumerate(self.args):
|
||||
if arg.ismem:
|
||||
memarg = n
|
||||
|
||||
if nreg == 1:
|
||||
regset = [(regs[0],)]
|
||||
if memarg == 0:
|
||||
regset += [(-1,)]
|
||||
elif nreg == 2:
|
||||
regset = [
|
||||
(regs[0], regs[1]),
|
||||
(regs[0], regs[0]),
|
||||
]
|
||||
if memarg == 0:
|
||||
regset += [(-1, regs[0])]
|
||||
elif memarg == 1:
|
||||
regset += [(dest, -1)]
|
||||
else:
|
||||
raise Exception("Too many regs: %s(%d)" % (self.op, nreg))
|
||||
|
||||
for regv in regset:
|
||||
argstr = []
|
||||
for i in range(nreg):
|
||||
arg = self.args[i]
|
||||
argstr.append(arg.regstr(regv[i]))
|
||||
if immarg is None:
|
||||
yield self.op + ' ' + ','.join(argstr)
|
||||
else:
|
||||
for immval in immarg.vals():
|
||||
yield self.op + ' ' + ','.join(argstr) + ',' + str(immval)
|
||||
|
||||
def split0(s):
|
||||
if s == '':
|
||||
return []
|
||||
return s.split(',')
|
||||
|
||||
def main():
|
||||
n = 0
|
||||
if len(sys.argv) <= 3:
|
||||
print("Usage: test-mmx.py x86.csv test-mmx.h CPUID...")
|
||||
exit(1)
|
||||
csvfile = open(sys.argv[1], 'r', newline='')
|
||||
archs = sys.argv[3:]
|
||||
with open(sys.argv[2], "w") as outf:
|
||||
outf.write("// Generated by test-mmx.py. Do not edit.\n")
|
||||
for row in csv.reader(strip_comments(csvfile)):
|
||||
insn = row[0].replace(',', '').split()
|
||||
if insn[0] in ignore:
|
||||
continue
|
||||
cpuid = row[6]
|
||||
if cpuid in archs:
|
||||
try:
|
||||
g = InsnGenerator(insn[0], insn[1:])
|
||||
for insn in g.gen():
|
||||
outf.write('TEST(%d, "%s", %s)\n' % (n, insn, g.optype))
|
||||
n += 1
|
||||
except SkipInstruction:
|
||||
pass
|
||||
outf.write("#undef TEST\n")
|
||||
csvfile.close()
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -17,7 +17,6 @@ TESTS=$(MULTIARCH_TESTS)
|
|||
endif
|
||||
|
||||
run-test-i386-ssse3: QEMU_OPTS += -cpu max
|
||||
run-test-avx: QEMU_OPTS += -cpu max
|
||||
run-plugin-test-i386-ssse3-%: QEMU_OPTS += -cpu max
|
||||
|
||||
test-x86_64: LDFLAGS+=-lm -lc
|
||||
|
|
|
|||
Loading…
Reference in New Issue