target/arm: Make stage_2_format for cache attributes optional
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike VMSAv8, the stage 2 attributes are in the same format as the stage 1 attributes (8-bit MAIR format). Rather than converting the MAIR format to the format used for VMSA stage 2 (bits [5:2] of a VMSA stage 2 descriptor) and then converting back to do the attribute combination, allow combined_attrs_nofwb() to accept s2 attributes that are already in the MAIR format. We move the assert() to combined_attrs_fwb(), because that function really does require a VMSA stage 2 attribute format. (We will never get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.) Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20221206102504.165775-4-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2361,7 +2361,11 @@ static uint8_t combined_attrs_nofwb(uint64_t hcr,
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{
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uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
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if (s2.is_s2_format) {
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s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
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} else {
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s2_mair_attrs = s2.attrs;
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}
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s1lo = extract32(s1.attrs, 0, 4);
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s2lo = extract32(s2_mair_attrs, 0, 4);
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@ -2418,6 +2422,8 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
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*/
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static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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assert(s2.is_s2_format && !s1.is_s2_format);
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switch (s2.attrs) {
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case 7:
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/* Use stage 1 attributes */
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@ -2467,7 +2473,7 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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ARMCacheAttrs ret;
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bool tagged = false;
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assert(s2.is_s2_format && !s1.is_s2_format);
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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if (s1.attrs == 0xf0) {
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