esp: add AMD PCscsi emulation (PCI SCSI adapter)
The PCI version is supported in lots of Operating Systems, and has been successfully tested on: - MS DOS 6.22 (using DC390 driver) - MS Windows 3.11 (using DC390 driver) - MS Windows 98 SE (using default driver) - MS Windows NT 3.1 (using DC390 driver) - MS Windows NT 4.0 (using default driver) Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Hervé Poussineau
Blue Swirl
parent
0883c5159f
commit
fabaaf1d1f
@ -25,3 +25,4 @@ CONFIG_HPET=y
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CONFIG_APPLESMC=y
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CONFIG_I8259=y
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CONFIG_PFLASH_CFI01=y
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CONFIG_ESP=y
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366
hw/esp.c
366
hw/esp.c
@ -2,6 +2,7 @@
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* QEMU ESP/NCR53C9x emulation
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*
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* Copyright (c) 2005-2006 Fabrice Bellard
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* Copyright (c) 2012 Herve Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -23,6 +24,7 @@
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*/
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#include "sysbus.h"
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#include "pci.h"
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#include "scsi.h"
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#include "esp.h"
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#include "trace.h"
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@ -142,6 +144,7 @@ struct ESPState {
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#define CFG1_RESREPT 0x40
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#define TCHI_FAS100A 0x4
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#define TCHI_AM53C974 0x12
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static void esp_raise_irq(ESPState *s)
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{
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@ -820,9 +823,372 @@ static TypeInfo sysbus_esp_info = {
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.class_init = sysbus_esp_class_init,
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};
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#define DMA_CMD 0x0
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#define DMA_STC 0x1
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#define DMA_SPA 0x2
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#define DMA_WBC 0x3
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#define DMA_WAC 0x4
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#define DMA_STAT 0x5
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#define DMA_SMDLA 0x6
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#define DMA_WMAC 0x7
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#define DMA_CMD_MASK 0x03
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#define DMA_CMD_DIAG 0x04
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#define DMA_CMD_MDL 0x10
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#define DMA_CMD_INTE_P 0x20
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#define DMA_CMD_INTE_D 0x40
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#define DMA_CMD_DIR 0x80
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#define DMA_STAT_PWDN 0x01
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#define DMA_STAT_ERROR 0x02
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#define DMA_STAT_ABORT 0x04
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#define DMA_STAT_DONE 0x08
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#define DMA_STAT_SCSIINT 0x10
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#define DMA_STAT_BCMBLT 0x20
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#define SBAC_STATUS 0x1000
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typedef struct PCIESPState {
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PCIDevice dev;
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MemoryRegion io;
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uint32_t dma_regs[8];
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uint32_t sbac;
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ESPState esp;
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} PCIESPState;
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static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
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{
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trace_esp_pci_dma_idle(val);
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esp_dma_enable(&pci->esp, 0, 0);
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}
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static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
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{
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trace_esp_pci_dma_blast(val);
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qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
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}
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static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
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{
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trace_esp_pci_dma_abort(val);
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if (pci->esp.current_req) {
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scsi_req_cancel(pci->esp.current_req);
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}
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}
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static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
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{
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trace_esp_pci_dma_start(val);
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pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
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pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
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pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
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pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
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| DMA_STAT_DONE | DMA_STAT_ABORT
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| DMA_STAT_ERROR | DMA_STAT_PWDN);
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esp_dma_enable(&pci->esp, 0, 1);
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}
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static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
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{
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trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
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switch (saddr) {
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case DMA_CMD:
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pci->dma_regs[saddr] = val;
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switch (val & DMA_CMD_MASK) {
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case 0x0: /* IDLE */
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esp_pci_handle_idle(pci, val);
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break;
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case 0x1: /* BLAST */
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esp_pci_handle_blast(pci, val);
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break;
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case 0x2: /* ABORT */
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esp_pci_handle_abort(pci, val);
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break;
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case 0x3: /* START */
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esp_pci_handle_start(pci, val);
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break;
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default: /* can't happen */
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abort();
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}
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break;
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case DMA_STC:
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case DMA_SPA:
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case DMA_SMDLA:
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pci->dma_regs[saddr] = val;
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break;
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case DMA_STAT:
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if (!(pci->sbac & SBAC_STATUS)) {
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/* clear some bits on write */
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uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
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pci->dma_regs[DMA_STAT] &= ~(val & mask);
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}
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break;
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default:
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trace_esp_pci_error_invalid_write_dma(val, saddr);
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return;
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}
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}
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static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
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{
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uint32_t val;
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val = pci->dma_regs[saddr];
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if (saddr == DMA_STAT) {
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if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
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val |= DMA_STAT_SCSIINT;
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}
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if (pci->sbac & SBAC_STATUS) {
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pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
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DMA_STAT_DONE);
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}
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}
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trace_esp_pci_dma_read(saddr, val);
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return val;
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}
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static void esp_pci_io_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned int size)
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{
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PCIESPState *pci = opaque;
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if (size < 4 || addr & 3) {
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/* need to upgrade request: we only support 4-bytes accesses */
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uint32_t current = 0, mask;
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int shift;
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if (addr < 0x40) {
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current = pci->esp.wregs[addr >> 2];
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} else if (addr < 0x60) {
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current = pci->dma_regs[(addr - 0x40) >> 2];
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} else if (addr < 0x74) {
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current = pci->sbac;
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}
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shift = (4 - size) * 8;
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mask = (~(uint32_t)0 << shift) >> shift;
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shift = ((4 - (addr & 3)) & 3) * 8;
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val <<= shift;
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val |= current & ~(mask << shift);
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addr &= ~3;
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size = 4;
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}
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if (addr < 0x40) {
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/* SCSI core reg */
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esp_reg_write(&pci->esp, addr >> 2, val);
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} else if (addr < 0x60) {
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/* PCI DMA CCB */
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esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
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} else if (addr == 0x70) {
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/* DMA SCSI Bus and control */
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trace_esp_pci_sbac_write(pci->sbac, val);
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pci->sbac = val;
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} else {
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trace_esp_pci_error_invalid_write((int)addr);
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}
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}
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static uint64_t esp_pci_io_read(void *opaque, target_phys_addr_t addr,
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unsigned int size)
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{
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PCIESPState *pci = opaque;
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uint32_t ret;
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if (addr < 0x40) {
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/* SCSI core reg */
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ret = esp_reg_read(&pci->esp, addr >> 2);
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} else if (addr < 0x60) {
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/* PCI DMA CCB */
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ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
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} else if (addr == 0x70) {
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/* DMA SCSI Bus and control */
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trace_esp_pci_sbac_read(pci->sbac);
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ret = pci->sbac;
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} else {
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/* Invalid region */
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trace_esp_pci_error_invalid_read((int)addr);
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ret = 0;
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}
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/* give only requested data */
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ret >>= (addr & 3) * 8;
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ret &= ~(~(uint64_t)0 << (8 * size));
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return ret;
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}
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static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
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DMADirection dir)
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{
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dma_addr_t addr;
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DMADirection expected_dir;
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if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
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expected_dir = DMA_DIRECTION_FROM_DEVICE;
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} else {
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expected_dir = DMA_DIRECTION_TO_DEVICE;
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}
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if (dir != expected_dir) {
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trace_esp_pci_error_invalid_dma_direction();
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return;
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}
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if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
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qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
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}
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addr = pci->dma_regs[DMA_SPA];
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if (pci->dma_regs[DMA_WBC] < len) {
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len = pci->dma_regs[DMA_WBC];
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}
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pci_dma_rw(&pci->dev, addr, buf, len, dir);
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/* update status registers */
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pci->dma_regs[DMA_WBC] -= len;
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pci->dma_regs[DMA_WAC] += len;
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}
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static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
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{
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PCIESPState *pci = opaque;
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esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
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}
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static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
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{
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PCIESPState *pci = opaque;
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esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
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}
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static const MemoryRegionOps esp_pci_io_ops = {
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.read = esp_pci_io_read,
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.write = esp_pci_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void esp_pci_hard_reset(DeviceState *dev)
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{
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PCIESPState *pci = DO_UPCAST(PCIESPState, dev.qdev, dev);
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esp_hard_reset(&pci->esp);
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pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
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| DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
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pci->dma_regs[DMA_WBC] &= ~0xffff;
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pci->dma_regs[DMA_WAC] = 0xffffffff;
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pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
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| DMA_STAT_DONE | DMA_STAT_ABORT
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| DMA_STAT_ERROR);
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pci->dma_regs[DMA_WMAC] = 0xfffffffd;
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}
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static const VMStateDescription vmstate_esp_pci_scsi = {
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.name = "pciespscsi",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, PCIESPState),
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VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
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VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
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size_t resid)
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{
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ESPState *s = req->hba_private;
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PCIESPState *pci = container_of(s, PCIESPState, esp);
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esp_command_complete(req, status, resid);
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pci->dma_regs[DMA_WBC] = 0;
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pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
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}
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static const struct SCSIBusInfo esp_pci_scsi_info = {
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.tcq = false,
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.max_target = ESP_MAX_DEVS,
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.max_lun = 7,
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.transfer_data = esp_transfer_data,
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.complete = esp_pci_command_complete,
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.cancel = esp_request_cancelled,
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};
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static int esp_pci_scsi_init(PCIDevice *dev)
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{
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PCIESPState *pci = DO_UPCAST(PCIESPState, dev, dev);
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ESPState *s = &pci->esp;
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uint8_t *pci_conf;
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pci_conf = pci->dev.config;
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/* Interrupt pin A */
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pci_conf[PCI_INTERRUPT_PIN] = 0x01;
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s->dma_memory_read = esp_pci_dma_memory_read;
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s->dma_memory_write = esp_pci_dma_memory_write;
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s->dma_opaque = pci;
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s->chip_id = TCHI_AM53C974;
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memory_region_init_io(&pci->io, &esp_pci_io_ops, pci, "esp-io", 0x80);
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pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
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s->irq = pci->dev.irq[0];
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scsi_bus_new(&s->bus, &dev->qdev, &esp_pci_scsi_info);
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if (!dev->qdev.hotplugged) {
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return scsi_bus_legacy_handle_cmdline(&s->bus);
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}
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return 0;
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}
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static int esp_pci_scsi_uninit(PCIDevice *d)
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{
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PCIESPState *pci = DO_UPCAST(PCIESPState, dev, d);
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memory_region_destroy(&pci->io);
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return 0;
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}
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static void esp_pci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->init = esp_pci_scsi_init;
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k->exit = esp_pci_scsi_uninit;
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k->vendor_id = PCI_VENDOR_ID_AMD;
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k->device_id = PCI_DEVICE_ID_AMD_SCSI;
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k->revision = 0x10;
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k->class_id = PCI_CLASS_STORAGE_SCSI;
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dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
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dc->reset = esp_pci_hard_reset;
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dc->vmsd = &vmstate_esp_pci_scsi;
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}
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static TypeInfo esp_pci_info = {
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.name = "am53c974",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIESPState),
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.class_init = esp_pci_class_init,
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};
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static void esp_register_types(void)
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{
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type_register_static(&sysbus_esp_info);
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type_register_static(&esp_pci_info);
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}
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type_init(esp_register_types)
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@ -59,6 +59,7 @@
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#define PCI_VENDOR_ID_AMD 0x1022
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#define PCI_DEVICE_ID_AMD_LANCE 0x2000
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#define PCI_DEVICE_ID_AMD_SCSI 0x2020
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#define PCI_VENDOR_ID_TI 0x104c
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12
trace-events
12
trace-events
@ -760,6 +760,18 @@ esp_mem_writeb_cmd_selatn(uint32_t val) "Select with ATN (%2.2x)"
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esp_mem_writeb_cmd_selatns(uint32_t val) "Select with ATN & stop (%2.2x)"
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esp_mem_writeb_cmd_ensel(uint32_t val) "Enable selection (%2.2x)"
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esp_mem_writeb_cmd_dissel(uint32_t val) "Disable selection (%2.2x)"
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esp_pci_error_invalid_dma_direction(void) "invalid DMA transfer direction"
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esp_pci_error_invalid_read(uint32_t reg) "read access outside bounds (reg 0x%x)"
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esp_pci_error_invalid_write(uint32_t reg) "write access outside bounds (reg 0x%x)"
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esp_pci_error_invalid_write_dma(uint32_t val, uint32_t addr) "invalid write of 0x%02x at [0x%x]"
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esp_pci_dma_read(uint32_t saddr, uint32_t reg) "reg[%d]: 0x%8.8x"
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esp_pci_dma_write(uint32_t saddr, uint32_t reg, uint32_t val) "reg[%d]: 0x%8.8x -> 0x%8.8x"
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esp_pci_dma_idle(uint32_t val) "IDLE (%.8x)"
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esp_pci_dma_blast(uint32_t val) "BLAST (%.8x)"
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esp_pci_dma_abort(uint32_t val) "ABORT (%.8x)"
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esp_pci_dma_start(uint32_t val) "START (%.8x)"
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esp_pci_sbac_read(uint32_t reg) "sbac: 0x%8.8x"
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esp_pci_sbac_write(uint32_t reg, uint32_t val) "sbac: 0x%8.8x -> 0x%8.8x"
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# monitor.c
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handle_qmp_command(void *mon, const char *cmd_name) "mon %p cmd_name \"%s\""
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