target/i386: EPYC-Rome model without XSAVES
Based on the kernel commit "b0563468ee x86/CPU/AMD: Disable XSAVES on AMD family 0x17", host system with EPYC-Rome can clear XSAVES capability bit. In another words, EPYC-Rome host without XSAVES can occur. Thus, we need an EPYC-Rome cpu model (without this feature) that matches the solution of fixing this erratum Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru> Message-Id: <20230524213748.8918-1-davydov-max@yandex-team.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -4466,6 +4466,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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},
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.cache_info = &epyc_rome_v3_cache_info
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},
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{
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.version = 4,
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.props = (PropValue[]) {
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/* Erratum 1386 */
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{ "model-id",
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"AMD EPYC-Rome-v4 Processor (no XSAVES)" },
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{ "xsaves", "off" },
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{ /* end of list */ }
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},
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},
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{ /* end of list */ }
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}
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},
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