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target/i386: EPYC-Rome model without XSAVES

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Based on the kernel commit "b0563468ee x86/CPU/AMD: Disable XSAVES on
AMD family 0x17", host system with EPYC-Rome can clear XSAVES capability
bit. In another words, EPYC-Rome host without XSAVES can occur. Thus, we
need an EPYC-Rome cpu model (without this feature) that matches the
solution of fixing this erratum

Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
Message-Id: <20230524213748.8918-1-davydov-max@yandex-team.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Maksim Davydov 2023-05-25 00:37:48 +03:00 committed by Paolo Bonzini
parent 886c0453cb
commit fb00aa6126
1 changed files with 10 additions and 0 deletions
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10
target/i386/cpu.c
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@ -4466,6 +4466,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
},
.cache_info = &epyc_rome_v3_cache_info
},
{
.version = 4,
.props = (PropValue[]) {
/* Erratum 1386 */
{ "model-id",
"AMD EPYC-Rome-v4 Processor (no XSAVES)" },
{ "xsaves", "off" },
{ /* end of list */ }
},
},
{ /* end of list */ }
}
},