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target/sparc: Move MOVcc, MOVR to decodetree

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-04 15:37:54 -07:00
parent 5fc546ee35
commit fb4ed7aad4
2 changed files with 64 additions and 56 deletions
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4
target/sparc/insns.decode
View File

@ -209,3 +209,7 @@ Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
# Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
}
MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11
MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11
MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10

116
target/sparc/translate.c
View File

@ -4324,6 +4324,64 @@ TRANS(SLL_i, ALL, do_shift_i, a, true, true)
TRANS(SRL_i, ALL, do_shift_i, a, false, true)
TRANS(SRA_i, ALL, do_shift_i, a, false, false)
static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm)
{
/* For simplicity, we under-decoded the rs2 form. */
if (!imm && rs2_or_imm & ~0x1f) {
return NULL;
}
if (imm || rs2_or_imm == 0) {
return tcg_constant_tl(rs2_or_imm);
} else {
return cpu_regs[rs2_or_imm];
}
}
static bool do_mov_cond(DisasContext *dc, DisasCompare *cmp, int rd, TCGv src2)
{
TCGv dst = gen_load_gpr(dc, rd);
tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, cmp->c2, src2, dst);
gen_store_gpr(dc, rd, dst);
return advance_pc(dc);
}
static bool trans_MOVcc(DisasContext *dc, arg_MOVcc *a)
{
TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
DisasCompare cmp;
if (src2 == NULL) {
return false;
}
gen_compare(&cmp, a->cc, a->cond, dc);
return do_mov_cond(dc, &cmp, a->rd, src2);
}
static bool trans_MOVfcc(DisasContext *dc, arg_MOVfcc *a)
{
TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
DisasCompare cmp;
if (src2 == NULL) {
return false;
}
gen_fcompare(&cmp, a->cc, a->cond);
return do_mov_cond(dc, &cmp, a->rd, src2);
}
static bool trans_MOVR(DisasContext *dc, arg_MOVR *a)
{
TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
DisasCompare cmp;
if (src2 == NULL) {
return false;
}
gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
return do_mov_cond(dc, &cmp, a->rd, src2);
}
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@ -4696,66 +4754,12 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
goto illegal_insn; /* WRTBR, WRHPR in decodetree */
#ifdef TARGET_SPARC64
case 0x2c: /* V9 movcc */
{
int cc = GET_FIELD_SP(insn, 11, 12);
int cond = GET_FIELD_SP(insn, 14, 17);
DisasCompare cmp;
TCGv dst;
if (insn & (1 << 18)) {
if (cc == 0) {
gen_compare(&cmp, 0, cond, dc);
} else if (cc == 2) {
gen_compare(&cmp, 1, cond, dc);
} else {
goto illegal_insn;
}
} else {
gen_fcompare(&cmp, cc, cond);
}
/* The get_src2 above loaded the normal 13-bit
immediate field, not the 11-bit field we have
in movcc. But it did handle the reg case. */
if (IS_IMM) {
simm = GET_FIELD_SPs(insn, 0, 10);
tcg_gen_movi_tl(cpu_src2, simm);
}
dst = gen_load_gpr(dc, rd);
tcg_gen_movcond_tl(cmp.cond, dst,
cmp.c1, cmp.c2,
cpu_src2, dst);
gen_store_gpr(dc, rd, dst);
break;
}
case 0x2f: /* V9 movr */
goto illegal_insn; /* in decodetree */
case 0x2e: /* V9 popc */
tcg_gen_ctpop_tl(cpu_dst, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x2f: /* V9 movr */
{
int cond = GET_FIELD_SP(insn, 10, 12);
DisasCompare cmp;
TCGv dst;
gen_compare_reg(&cmp, cond, cpu_src1);
/* The get_src2 above loaded the normal 13-bit
immediate field, not the 10-bit field we have
in movr. But it did handle the reg case. */
if (IS_IMM) {
simm = GET_FIELD_SPs(insn, 0, 9);
tcg_gen_movi_tl(cpu_src2, simm);
}
dst = gen_load_gpr(dc, rd);
tcg_gen_movcond_tl(cmp.cond, dst,
cmp.c1, cmp.c2,
cpu_src2, dst);
gen_store_gpr(dc, rd, dst);
break;
}
#endif
default:
goto illegal_insn;