target/ppc: Move load and store floating point instructions to decodetree
Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux) and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx, stfdux) from legacy system to decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211029202424.175401-4-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Fernando Eckhardt Valle
David Gibson
parent
725b2d4dac
commit
fbd2e60ef1
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@ -114,6 +114,30 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
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CFUGED 011111 ..... ..... ..... 0011011100 - @X
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### Float-Point Load Instructions
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LFS 110000 ..... ..... ................ @D
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LFSU 110001 ..... ..... ................ @D
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LFSX 011111 ..... ..... ..... 1000010111 - @X
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LFSUX 011111 ..... ..... ..... 1000110111 - @X
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LFD 110010 ..... ..... ................ @D
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LFDU 110011 ..... ..... ................ @D
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LFDX 011111 ..... ..... ..... 1001010111 - @X
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LFDUX 011111 ..... ..... ..... 1001110111 - @X
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### Float-Point Store Instructions
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STFS 110100 ..... ...... ............... @D
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STFSU 110101 ..... ...... ............... @D
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STFSX 011111 ..... ...... .... 1010010111 - @X
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STFSUX 011111 ..... ...... .... 1010110111 - @X
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STFD 110110 ..... ...... ............... @D
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STFDU 110111 ..... ...... ............... @D
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STFDX 011111 ..... ...... .... 1011010111 - @X
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STFDUX 011111 ..... ...... .... 1011110111 - @X
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### Move To/From System Register Instructions
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SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
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@ -854,99 +854,6 @@ static void gen_mtfsfi(DisasContext *ctx)
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gen_helper_float_check_status(cpu_env);
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}
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/*** Floating-point load ***/
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#define GEN_LDF(name, ldop, opc, type) \
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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TCGv_i64 t0; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_FLOAT); \
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EA = tcg_temp_new(); \
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t0 = tcg_temp_new_i64(); \
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gen_addr_imm_index(ctx, EA, 0); \
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gen_qemu_##ldop(ctx, t0, EA); \
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set_fpr(rD(ctx->opcode), t0); \
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tcg_temp_free(EA); \
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tcg_temp_free_i64(t0); \
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}
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#define GEN_LDUF(name, ldop, opc, type) \
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static void glue(gen_, name##u)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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TCGv_i64 t0; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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if (unlikely(rA(ctx->opcode) == 0)) { \
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_FLOAT); \
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EA = tcg_temp_new(); \
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t0 = tcg_temp_new_i64(); \
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gen_addr_imm_index(ctx, EA, 0); \
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gen_qemu_##ldop(ctx, t0, EA); \
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set_fpr(rD(ctx->opcode), t0); \
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
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tcg_temp_free(EA); \
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tcg_temp_free_i64(t0); \
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}
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#define GEN_LDUXF(name, ldop, opc, type) \
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static void glue(gen_, name##ux)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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TCGv_i64 t0; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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t0 = tcg_temp_new_i64(); \
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if (unlikely(rA(ctx->opcode) == 0)) { \
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_FLOAT); \
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EA = tcg_temp_new(); \
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gen_addr_reg_index(ctx, EA); \
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gen_qemu_##ldop(ctx, t0, EA); \
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set_fpr(rD(ctx->opcode), t0); \
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
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tcg_temp_free(EA); \
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tcg_temp_free_i64(t0); \
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}
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#define GEN_LDXF(name, ldop, opc2, opc3, type) \
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static void glue(gen_, name##x)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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TCGv_i64 t0; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_FLOAT); \
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EA = tcg_temp_new(); \
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t0 = tcg_temp_new_i64(); \
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gen_addr_reg_index(ctx, EA); \
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gen_qemu_##ldop(ctx, t0, EA); \
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set_fpr(rD(ctx->opcode), t0); \
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tcg_temp_free(EA); \
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tcg_temp_free_i64(t0); \
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}
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#define GEN_LDFS(name, ldop, op, type) \
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GEN_LDF(name, ldop, op | 0x20, type); \
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GEN_LDUF(name, ldop, op | 0x21, type); \
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GEN_LDUXF(name, ldop, op | 0x01, type); \
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GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
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static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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@ -955,11 +862,6 @@ static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
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tcg_temp_free_i32(tmp);
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}
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/* lfd lfdu lfdux lfdx */
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GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT);
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/* lfs lfsu lfsux lfsx */
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GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
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/* lfdepx (external PID lfdx) */
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static void gen_lfdepx(DisasContext *ctx)
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{
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@ -1089,73 +991,6 @@ static void gen_lfiwzx(DisasContext *ctx)
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tcg_temp_free(EA);
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tcg_temp_free_i64(t0);
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}
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/*** Floating-point store ***/
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#define GEN_STF(name, stop, opc, type) \
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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TCGv_i64 t0; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_FLOAT); \
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EA = tcg_temp_new(); \
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t0 = tcg_temp_new_i64(); \
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gen_addr_imm_index(ctx, EA, 0); \
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get_fpr(t0, rS(ctx->opcode)); \
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gen_qemu_##stop(ctx, t0, EA); \
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tcg_temp_free(EA); \
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tcg_temp_free_i64(t0); \
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}
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#define GEN_STUF(name, stop, opc, type) \
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static void glue(gen_, name##u)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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TCGv_i64 t0; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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if (unlikely(rA(ctx->opcode) == 0)) { \
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_FLOAT); \
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EA = tcg_temp_new(); \
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t0 = tcg_temp_new_i64(); \
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gen_addr_imm_index(ctx, EA, 0); \
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get_fpr(t0, rS(ctx->opcode)); \
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gen_qemu_##stop(ctx, t0, EA); \
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
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tcg_temp_free(EA); \
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tcg_temp_free_i64(t0); \
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}
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#define GEN_STUXF(name, stop, opc, type) \
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static void glue(gen_, name##ux)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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TCGv_i64 t0; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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if (unlikely(rA(ctx->opcode) == 0)) { \
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_FLOAT); \
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EA = tcg_temp_new(); \
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t0 = tcg_temp_new_i64(); \
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gen_addr_reg_index(ctx, EA); \
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get_fpr(t0, rS(ctx->opcode)); \
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gen_qemu_##stop(ctx, t0, EA); \
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
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tcg_temp_free(EA); \
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tcg_temp_free_i64(t0); \
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}
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#define GEN_STXF(name, stop, opc2, opc3, type) \
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static void glue(gen_, name##x)(DisasContext *ctx) \
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@ -1176,12 +1011,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
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tcg_temp_free_i64(t0); \
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}
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#define GEN_STFS(name, stop, op, type) \
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GEN_STF(name, stop, op | 0x20, type); \
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GEN_STUF(name, stop, op | 0x21, type); \
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GEN_STUXF(name, stop, op | 0x01, type); \
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GEN_STXF(name, stop, 0x17, op | 0x00, type)
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static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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@ -1190,11 +1019,6 @@ static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
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tcg_temp_free_i32(tmp);
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}
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/* stfd stfdu stfdux stfdx */
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GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT);
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/* stfs stfsu stfsux stfsx */
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GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
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/* stfdepx (external PID lfdx) */
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static void gen_stfdepx(DisasContext *ctx)
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{
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@ -1473,6 +1297,77 @@ static void gen_stfqx(DisasContext *ctx)
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tcg_temp_free_i64(t1);
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}
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/* Floating-point Load/Store Instructions */
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static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ,
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bool update, bool store, bool single)
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{
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TCGv ea;
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TCGv_i64 t0;
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REQUIRE_INSNS_FLAGS(ctx, FLOAT);
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REQUIRE_FPU(ctx);
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if (update && ra == 0) {
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gen_invalid(ctx);
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return true;
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}
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gen_set_access_type(ctx, ACCESS_FLOAT);
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t0 = tcg_temp_new_i64();
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ea = do_ea_calc(ctx, ra, displ);
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if (store) {
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get_fpr(t0, rt);
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if (single) {
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gen_qemu_st32fs(ctx, t0, ea);
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} else {
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gen_qemu_st64_i64(ctx, t0, ea);
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}
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} else {
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if (single) {
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gen_qemu_ld32fs(ctx, t0, ea);
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} else {
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gen_qemu_ld64_i64(ctx, t0, ea);
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}
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set_fpr(rt, t0);
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}
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if (update) {
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tcg_gen_mov_tl(cpu_gpr[rt], ea);
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}
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tcg_temp_free_i64(t0);
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tcg_temp_free(ea);
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return true;
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}
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static bool do_lsfp_D(DisasContext *ctx, arg_D *a, bool update, bool store,
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bool single)
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{
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return do_lsfpsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store,
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single);
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}
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static bool do_lsfp_X(DisasContext *ctx, arg_X *a, bool update,
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bool store, bool single)
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{
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return do_lsfpsd(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, single);
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}
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TRANS(LFS, do_lsfp_D, false, false, true)
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TRANS(LFSU, do_lsfp_D, true, false, true)
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TRANS(LFSX, do_lsfp_X, false, false, true)
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TRANS(LFSUX, do_lsfp_X, true, false, true)
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TRANS(LFD, do_lsfp_D, false, false, false)
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TRANS(LFDU, do_lsfp_D, true, false, false)
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TRANS(LFDX, do_lsfp_X, false, false, false)
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TRANS(LFDUX, do_lsfp_X, true, false, false)
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TRANS(STFS, do_lsfp_D, false, true, true)
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TRANS(STFSU, do_lsfp_D, true, true, true)
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TRANS(STFSX, do_lsfp_X, false, true, true)
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TRANS(STFSUX, do_lsfp_X, true, true, true)
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TRANS(STFD, do_lsfp_D, false, true, false)
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TRANS(STFDU, do_lsfp_D, true, true, false)
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TRANS(STFDX, do_lsfp_X, false, true, false)
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TRANS(STFDUX, do_lsfp_X, true, true, false)
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#undef _GEN_FLOAT_ACB
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#undef GEN_FLOAT_ACB
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#undef _GEN_FLOAT_AB
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@ -50,43 +50,14 @@ GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
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GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
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GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
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#define GEN_LDF(name, ldop, opc, type) \
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GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
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#define GEN_LDUF(name, ldop, opc, type) \
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GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
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#define GEN_LDUXF(name, ldop, opc, type) \
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GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
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#define GEN_LDXF(name, ldop, opc2, opc3, type) \
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GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
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#define GEN_LDFS(name, ldop, op, type) \
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GEN_LDF(name, ldop, op | 0x20, type) \
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GEN_LDUF(name, ldop, op | 0x21, type) \
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GEN_LDUXF(name, ldop, op | 0x01, type) \
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GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
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GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
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GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
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GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206),
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GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
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GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
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GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
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#define GEN_STF(name, stop, opc, type) \
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GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
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#define GEN_STUF(name, stop, opc, type) \
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GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
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#define GEN_STUXF(name, stop, opc, type) \
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GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
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#define GEN_STXF(name, stop, opc2, opc3, type) \
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GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
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#define GEN_STFS(name, stop, op, type) \
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GEN_STF(name, stop, op | 0x20, type) \
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GEN_STUF(name, stop, op | 0x21, type) \
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GEN_STUXF(name, stop, op | 0x01, type) \
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GEN_STXF(name, stop, 0x17, op | 0x00, type)
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GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
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GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
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GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
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GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
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GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
|
||||
|
|
|
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Reference in New Issue