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hw/usb: hcd-xhci-pci: Fix spec violation of IP flag for MSI/MSI-X

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Per xHCI spec v1.2 chapter 4.17.5 page 296:

  If MSI or MSI-X interrupts are enabled, Interrupt Pending (IP)
  shall be cleared automatically when the PCI dword write generated
  by the interrupt assertion is complete.

Currently QEMU does not clear the IP flag in the MSI / MSI-X mode.
This causes subsequent spurious interrupt to be delivered to guests.
To solve this, we change the xhci intr_raise() hook routine to have
a bool return value that is passed to its caller (the xhci core),
with true indicating that IP should be self-cleared.

Fixes: 62c6ae04cf ("xhci: Initial xHCI implementation")
Fixes: 4c47f80063 ("xhci: add msix support")
Signed-off-by: Ruimei Yan <ruimei.yan@windriver.com>
[bmeng: move IP clear codes from xhci pci to xhci core]
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20210521024224.2277634-2-bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Ruimei Yan 2021-05-21 10:42:24 +08:00 committed by Gerd Hoffmann
parent 3c6151cd11
commit fc967aad40
4 changed files with 15 additions and 7 deletions
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8
hw/usb/hcd-xhci-pci.c
View File

@ -57,7 +57,7 @@ static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
} }
} }
static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) static bool xhci_pci_intr_raise(XHCIState *xhci, int n, bool level)
{ {
XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); XHCIPciState *s = container_of(xhci, XHCIPciState, xhci);
PCIDevice *pci_dev = PCI_DEVICE(s); PCIDevice *pci_dev = PCI_DEVICE(s);
@ -70,13 +70,15 @@ static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level)
if (msix_enabled(pci_dev) && level) { if (msix_enabled(pci_dev) && level) {
msix_notify(pci_dev, n); msix_notify(pci_dev, n);
return; return true;
} }
if (msi_enabled(pci_dev) && level) { if (msi_enabled(pci_dev) && level) {
msi_notify(pci_dev, n); msi_notify(pci_dev, n);
return; return true;
} }
return false;
} }
static void xhci_pci_reset(DeviceState *dev) static void xhci_pci_reset(DeviceState *dev)

4
hw/usb/hcd-xhci-sysbus.c
View File

@ -16,11 +16,13 @@
#include "hw/acpi/aml-build.h" #include "hw/acpi/aml-build.h"
#include "hw/irq.h" #include "hw/irq.h"
static void xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level) static bool xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level)
{ {
XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci); XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci);
qemu_set_irq(s->irq[n], level); qemu_set_irq(s->irq[n], level);
return false;
} }
void xhci_sysbus_reset(DeviceState *dev) void xhci_sysbus_reset(DeviceState *dev)

8
hw/usb/hcd-xhci.c
View File

@ -551,7 +551,9 @@ static void xhci_intr_update(XHCIState *xhci, int v)
level = 1; level = 1;
} }
if (xhci->intr_raise) { if (xhci->intr_raise) {
xhci->intr_raise(xhci, 0, level); if (xhci->intr_raise(xhci, 0, level)) {
xhci->intr[0].iman &= ~IMAN_IP;
}
} }
} }
if (xhci->intr_update) { if (xhci->intr_update) {
@ -579,7 +581,9 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
return; return;
} }
if (xhci->intr_raise) { if (xhci->intr_raise) {
xhci->intr_raise(xhci, v, true); if (xhci->intr_raise(xhci, v, true)) {
xhci->intr[v].iman &= ~IMAN_IP;
}
} }
} }

2
hw/usb/hcd-xhci.h
View File

@ -194,7 +194,7 @@ typedef struct XHCIState {
uint32_t flags; uint32_t flags;
uint32_t max_pstreams_mask; uint32_t max_pstreams_mask;
void (*intr_update)(XHCIState *s, int n, bool enable); void (*intr_update)(XHCIState *s, int n, bool enable);
void (*intr_raise)(XHCIState *s, int n, bool level); bool (*intr_raise)(XHCIState *s, int n, bool level);
DeviceState *hostOpaque; DeviceState *hostOpaque;
/* Operational Registers */ /* Operational Registers */