target/arm: Add PMSAv8r functionality
Add PMSAv8r translation. Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20221206102504.165775-7-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Tobias Röhmel
Peter Maydell
parent
761c46425e
commit
fca45e3467
126
target/arm/ptw.c
126
target/arm/ptw.c
@ -1758,9 +1758,13 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
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if (arm_feature(env, ARM_FEATURE_M)) {
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return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
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} else {
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return regime_sctlr(env, mmu_idx) & SCTLR_BR;
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}
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if (mmu_idx == ARMMMUIdx_Stage2) {
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return false;
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}
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return regime_sctlr(env, mmu_idx) & SCTLR_BR;
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}
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static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
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@ -1952,6 +1956,26 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
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return !(result->f.prot & (1 << access_type));
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}
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static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx,
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uint32_t secure)
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{
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if (regime_el(env, mmu_idx) == 2) {
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return env->pmsav8.hprbar;
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} else {
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return env->pmsav8.rbar[secure];
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}
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}
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static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx,
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uint32_t secure)
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{
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if (regime_el(env, mmu_idx) == 2) {
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return env->pmsav8.hprlar;
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} else {
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return env->pmsav8.rlar[secure];
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}
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}
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bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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bool secure, GetPhysAddrResult *result,
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@ -1974,6 +1998,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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bool hit = false;
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uint32_t addr_page_base = address & TARGET_PAGE_MASK;
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uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
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int region_counter;
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if (regime_el(env, mmu_idx) == 2) {
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region_counter = cpu->pmsav8r_hdregion;
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} else {
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region_counter = cpu->pmsav7_dregion;
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}
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result->f.lg_page_size = TARGET_PAGE_BITS;
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result->f.phys_addr = address;
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@ -1982,6 +2013,10 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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*mregion = -1;
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}
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if (mmu_idx == ARMMMUIdx_Stage2) {
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fi->stage2 = true;
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}
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/*
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* Unlike the ARM ARM pseudocode, we don't need to check whether this
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* was an exception vector read from the vector table (which is always
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@ -1998,17 +2033,26 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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hit = true;
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}
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for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
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uint32_t bitmask;
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if (arm_feature(env, ARM_FEATURE_M)) {
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bitmask = 0x1f;
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} else {
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bitmask = 0x3f;
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fi->level = 0;
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}
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for (n = region_counter - 1; n >= 0; n--) {
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/* region search */
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/*
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* Note that the base address is bits [31:5] from the register
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* with bits [4:0] all zeroes, but the limit address is bits
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* [31:5] from the register with bits [4:0] all ones.
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* Note that the base address is bits [31:x] from the register
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* with bits [x-1:0] all zeroes, but the limit address is bits
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* [31:x] from the register with bits [x:0] all ones. Where x is
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* 5 for Cortex-M and 6 for Cortex-R
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*/
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uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
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uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
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uint32_t base = regime_rbar(env, mmu_idx, secure)[n] & ~bitmask;
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uint32_t limit = regime_rlar(env, mmu_idx, secure)[n] | bitmask;
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if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
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if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) {
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/* Region disabled */
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continue;
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}
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@ -2042,7 +2086,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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* PMSAv7 where highest-numbered-region wins)
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*/
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fi->type = ARMFault_Permission;
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fi->level = 1;
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if (arm_feature(env, ARM_FEATURE_M)) {
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fi->level = 1;
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}
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return true;
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}
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@ -2052,8 +2098,11 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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}
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if (!hit) {
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/* background fault */
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fi->type = ARMFault_Background;
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if (arm_feature(env, ARM_FEATURE_M)) {
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fi->type = ARMFault_Background;
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} else {
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fi->type = ARMFault_Permission;
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}
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return true;
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}
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@ -2061,12 +2110,14 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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/* hit using the background region */
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get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
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} else {
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uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
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uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
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uint32_t matched_rbar = regime_rbar(env, mmu_idx, secure)[matchregion];
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uint32_t matched_rlar = regime_rlar(env, mmu_idx, secure)[matchregion];
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uint32_t ap = extract32(matched_rbar, 1, 2);
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uint32_t xn = extract32(matched_rbar, 0, 1);
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bool pxn = false;
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if (arm_feature(env, ARM_FEATURE_V8_1M)) {
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pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
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pxn = extract32(matched_rlar, 4, 1);
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}
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if (m_is_system_region(env, address)) {
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@ -2074,21 +2125,46 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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xn = 1;
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}
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result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
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if (regime_el(env, mmu_idx) == 2) {
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result->f.prot = simple_ap_to_rw_prot_is_user(ap,
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mmu_idx != ARMMMUIdx_E2);
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} else {
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result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
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}
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if (!arm_feature(env, ARM_FEATURE_M)) {
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uint8_t attrindx = extract32(matched_rlar, 1, 3);
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uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
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uint8_t sh = extract32(matched_rlar, 3, 2);
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if (regime_sctlr(env, mmu_idx) & SCTLR_WXN &&
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result->f.prot & PAGE_WRITE && mmu_idx != ARMMMUIdx_Stage2) {
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xn = 0x1;
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}
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if ((regime_el(env, mmu_idx) == 1) &&
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regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap == 0x1) {
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pxn = 0x1;
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}
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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result->cacheattrs.shareability = sh;
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}
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if (result->f.prot && !xn && !(pxn && !is_user)) {
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result->f.prot |= PAGE_EXEC;
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}
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/*
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* We don't need to look the attribute up in the MAIR0/MAIR1
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* registers because that only tells us about cacheability.
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*/
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if (mregion) {
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*mregion = matchregion;
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}
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}
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fi->type = ARMFault_Permission;
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fi->level = 1;
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if (arm_feature(env, ARM_FEATURE_M)) {
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fi->level = 1;
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}
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return !(result->f.prot & (1 << access_type));
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}
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@ -2649,7 +2725,13 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
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cacheattrs1 = result->cacheattrs;
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memset(result, 0, sizeof(*result));
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ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi);
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if (arm_feature(env, ARM_FEATURE_PMSA)) {
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ret = get_phys_addr_pmsav8(env, ipa, access_type,
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ptw->in_mmu_idx, is_secure, result, fi);
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} else {
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ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
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is_el0, result, fi);
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}
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fi->s2addr = ipa;
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/* Combine the S1 and S2 perms. */
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