target/riscv/tcg: introduce tcg_cpu_instance_init()
tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG accelerator. It'll be called from within riscv_cpu_post_init(), via accel_cpu_instance_init(), similar to what happens with KVM. In fact, to preserve behavior, the implementation will be similar to what riscv_cpu_post_init() already does. In this patch we'll move riscv_cpu_add_user_properties() and riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c. All multi-extension properties code was moved. The 'multi_ext_user_opts' hash table was also moved to tcg-cpu.c since it's a TCG only structure, meaning that we won't have to worry about initializing a TCG hash table when running a KVM CPU anymore. riscv_cpu_add_user_properties() will remain in cpu.c for now due to how much code it requires to be moved at the same time. We'll do that in the next patch. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-16-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -162,9 +162,6 @@ static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
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};
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/* Hash that stores user set extensions */
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static GHashTable *multi_ext_user_opts;
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bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
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{
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bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
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@ -194,12 +191,6 @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
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g_assert_not_reached();
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}
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bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
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{
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return g_hash_table_contains(multi_ext_user_opts,
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GUINT_TO_POINTER(ext_offset));
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}
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const char * const riscv_int_regnames[] = {
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"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
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"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
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@ -280,9 +271,6 @@ static const char * const riscv_intr_names[] = {
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"reserved"
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};
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static void riscv_cpu_add_user_properties(Object *obj);
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static void riscv_init_max_cpu_extensions(Object *obj);
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const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
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{
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if (async) {
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@ -1206,32 +1194,9 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
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return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
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}
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static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
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{
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return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
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}
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static bool riscv_cpu_has_user_properties(Object *cpu_obj)
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{
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if (kvm_enabled() &&
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object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
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return true;
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}
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return riscv_cpu_is_dynamic(cpu_obj);
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}
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static void riscv_cpu_post_init(Object *obj)
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{
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accel_cpu_instance_init(CPU(obj));
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if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
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riscv_cpu_add_user_properties(obj);
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}
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if (riscv_cpu_has_max_extensions(obj)) {
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riscv_init_max_cpu_extensions(obj);
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}
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}
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static void riscv_cpu_init(Object *obj)
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@ -1240,8 +1205,6 @@ static void riscv_cpu_init(Object *obj)
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qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
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IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
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#endif /* CONFIG_USER_ONLY */
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multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
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}
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typedef struct RISCVCPUMisaExtConfig {
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@ -1527,119 +1490,6 @@ Property riscv_cpu_options[] = {
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DEFINE_PROP_END_OF_LIST(),
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};
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static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
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bool value;
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if (!visit_type_bool(v, name, &value, errp)) {
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return;
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}
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isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
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g_hash_table_insert(multi_ext_user_opts,
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GUINT_TO_POINTER(multi_ext_cfg->offset),
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(gpointer)value);
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}
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static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
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bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
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visit_type_bool(v, name, &value, errp);
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}
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static void cpu_add_multi_ext_prop(Object *cpu_obj,
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const RISCVCPUMultiExtConfig *multi_cfg)
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{
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object_property_add(cpu_obj, multi_cfg->name, "bool",
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cpu_get_multi_ext_cfg,
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cpu_set_multi_ext_cfg,
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NULL, (void *)multi_cfg);
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/*
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* Set def val directly instead of using
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* object_property_set_bool() to save the set()
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* callback hash for user inputs.
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*/
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isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
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multi_cfg->enabled);
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}
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static void riscv_cpu_add_multiext_prop_array(Object *obj,
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const RISCVCPUMultiExtConfig *array)
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{
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const RISCVCPUMultiExtConfig *prop;
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g_assert(array);
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for (prop = array; prop && prop->name; prop++) {
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cpu_add_multi_ext_prop(obj, prop);
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}
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}
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/*
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* Add CPU properties with user-facing flags.
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*
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* This will overwrite existing env->misa_ext values with the
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* defaults set via riscv_cpu_add_misa_properties().
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*/
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static void riscv_cpu_add_user_properties(Object *obj)
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{
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#ifndef CONFIG_USER_ONLY
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riscv_add_satp_mode_properties(obj);
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#endif
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riscv_cpu_add_misa_properties(obj);
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riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
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riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
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riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
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for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
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qdev_property_add_static(DEVICE(obj), prop);
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}
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}
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/*
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* The 'max' type CPU will have all possible ratified
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* non-vendor extensions enabled.
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*/
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static void riscv_init_max_cpu_extensions(Object *obj)
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{
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RISCVCPU *cpu = RISCV_CPU(obj);
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CPURISCVState *env = &cpu->env;
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const RISCVCPUMultiExtConfig *prop;
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/* Enable RVG, RVJ and RVV that are disabled by default */
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riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
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for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
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isa_ext_update_enabled(cpu, prop->offset, true);
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}
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/* set vector version */
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env->vext_ver = VEXT_VERSION_1_00_0;
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/* Zfinx is not compatible with F. Disable it */
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
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if (env->misa_mxl != MXL_RV32) {
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
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}
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}
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static Property riscv_cpu_properties[] = {
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DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
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@ -710,7 +710,6 @@ enum riscv_pmu_event_idx {
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/* used by tcg/tcg-cpu.c*/
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void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
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bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
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bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
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int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
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void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
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@ -24,6 +24,7 @@
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#include "pmu.h"
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#include "time_helper.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "qemu/accel.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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@ -31,6 +32,15 @@
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#include "hw/core/tcg-cpu-ops.h"
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#include "tcg/tcg.h"
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/* Hash that stores user set extensions */
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static GHashTable *multi_ext_user_opts;
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static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
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{
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return g_hash_table_contains(multi_ext_user_opts,
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GUINT_TO_POINTER(ext_offset));
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}
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static void riscv_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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@ -570,6 +580,144 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
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return true;
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}
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static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
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bool value;
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if (!visit_type_bool(v, name, &value, errp)) {
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return;
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}
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isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
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g_hash_table_insert(multi_ext_user_opts,
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GUINT_TO_POINTER(multi_ext_cfg->offset),
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(gpointer)value);
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}
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static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
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bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
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visit_type_bool(v, name, &value, errp);
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}
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static void cpu_add_multi_ext_prop(Object *cpu_obj,
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const RISCVCPUMultiExtConfig *multi_cfg)
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{
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object_property_add(cpu_obj, multi_cfg->name, "bool",
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cpu_get_multi_ext_cfg,
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cpu_set_multi_ext_cfg,
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NULL, (void *)multi_cfg);
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/*
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* Set def val directly instead of using
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* object_property_set_bool() to save the set()
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* callback hash for user inputs.
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*/
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isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
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multi_cfg->enabled);
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}
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static void riscv_cpu_add_multiext_prop_array(Object *obj,
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const RISCVCPUMultiExtConfig *array)
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{
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const RISCVCPUMultiExtConfig *prop;
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g_assert(array);
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for (prop = array; prop && prop->name; prop++) {
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cpu_add_multi_ext_prop(obj, prop);
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}
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}
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/*
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* Add CPU properties with user-facing flags.
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*
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* This will overwrite existing env->misa_ext values with the
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* defaults set via riscv_cpu_add_misa_properties().
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*/
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static void riscv_cpu_add_user_properties(Object *obj)
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{
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#ifndef CONFIG_USER_ONLY
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riscv_add_satp_mode_properties(obj);
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#endif
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riscv_cpu_add_misa_properties(obj);
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riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
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riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
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riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
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for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
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qdev_property_add_static(DEVICE(obj), prop);
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}
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}
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/*
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* The 'max' type CPU will have all possible ratified
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* non-vendor extensions enabled.
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*/
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static void riscv_init_max_cpu_extensions(Object *obj)
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{
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RISCVCPU *cpu = RISCV_CPU(obj);
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CPURISCVState *env = &cpu->env;
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const RISCVCPUMultiExtConfig *prop;
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/* Enable RVG, RVJ and RVV that are disabled by default */
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riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
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for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
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isa_ext_update_enabled(cpu, prop->offset, true);
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}
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/* set vector version */
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env->vext_ver = VEXT_VERSION_1_00_0;
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/* Zfinx is not compatible with F. Disable it */
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
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if (env->misa_mxl != MXL_RV32) {
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isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
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}
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}
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static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
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{
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return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
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}
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static bool riscv_cpu_has_user_properties(Object *cpu_obj)
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{
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return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
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}
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static void tcg_cpu_instance_init(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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Object *obj = OBJECT(cpu);
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if (riscv_cpu_has_user_properties(obj)) {
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multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
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riscv_cpu_add_user_properties(obj);
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}
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if (riscv_cpu_has_max_extensions(obj)) {
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riscv_init_max_cpu_extensions(obj);
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}
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}
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static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
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{
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/*
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@ -588,6 +736,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
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AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
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acc->cpu_class_init = tcg_cpu_class_init;
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acc->cpu_instance_init = tcg_cpu_instance_init;
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acc->cpu_target_realize = tcg_cpu_realize;
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}
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