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target/mips: Add emulation of MMI instruction PCPYUD

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Add emulation of MMI instruction PCPYUD. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551712405-2530-4-git-send-email-mateja.marjanovic@rt-rk.com>
This commit is contained in:
Mateja Marjanovic 2019-03-04 16:13:15 +01:00 committed by Aleksandar Markovic
parent b87eef31f2
commit fd487f83ea
1 changed files with 42 additions and 1 deletions
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43
target/mips/translate.c
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@ -24458,6 +24458,45 @@ static void gen_mmi_pcpyld(DisasContext *ctx)
}
}
/*
* PCPYUD rd, rs, rt
*
* Parallel Copy Upper Doubleword
*
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-----------+---------+---------+---------+---------+-----------+
* | MMI | rs | rt | rd | PCPYUD | MMI3 |
* +-----------+---------+---------+---------+---------+-----------+
*/
static void gen_mmi_pcpyud(DisasContext *ctx)
{
uint32_t rs, rt, rd;
uint32_t opcode;
opcode = ctx->opcode;
rs = extract32(opcode, 21, 5);
rt = extract32(opcode, 16, 5);
rd = extract32(opcode, 11, 5);
if (rd == 0) {
/* nop */
} else {
if (rs == 0) {
tcg_gen_movi_i64(cpu_gpr[rd], 0);
} else {
tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
}
if (rt == 0) {
tcg_gen_movi_i64(cpu_mmr[rd], 0);
} else {
if (rd != rt) {
tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
}
}
}
}
#endif
@ -27508,7 +27547,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PINTEH: /* TODO: MMI_OPC_3_PINTEH */
case MMI_OPC_3_PMULTUW: /* TODO: MMI_OPC_3_PMULTUW */
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
case MMI_OPC_3_PCPYUD: /* TODO: MMI_OPC_3_PCPYUD */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
@ -27518,6 +27556,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PCPYH:
gen_mmi_pcpyh(ctx);
break;
case MMI_OPC_3_PCPYUD:
gen_mmi_pcpyud(ctx);
break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);