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hw/arm/musca: Create and connect ARMSSE Clocks

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Create and connect the two clocks needed by the ARMSSE.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210128114145.20536-16-peter.maydell@linaro.org
Message-id: 20210121190622.22000-16-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-01-28 11:41:35 +00:00
parent dee1515bc3
commit fd630cdad7
1 changed files with 12 additions and 0 deletions
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12
hw/arm/musca.c
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@ -33,6 +33,7 @@
#include "hw/misc/tz-ppc.h"
#include "hw/misc/unimp.h"
#include "hw/rtc/pl031.h"
#include "hw/qdev-clock.h"
#include "qom/object.h"
#define MUSCA_NUMIRQ_MAX 96
@ -82,6 +83,8 @@ struct MuscaMachineState {
UnimplementedDeviceState sdio;
UnimplementedDeviceState gpio;
UnimplementedDeviceState cryptoisland;
Clock *sysclk;
Clock *s32kclk;
};
#define TYPE_MUSCA_MACHINE "musca"
@ -96,6 +99,8 @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE)
* don't model that in our SSE-200 model yet.
*/
#define SYSCLK_FRQ 40000000
/* Slow 32Khz S32KCLK frequency in Hz */
#define S32KCLK_FRQ (32 * 1000)
static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno)
{
@ -367,6 +372,11 @@ static void musca_init(MachineState *machine)
exit(1);
}
mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(mms->sysclk, SYSCLK_FRQ);
mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
object_initialize_child(OBJECT(machine), "sse-200", &mms->sse,
TYPE_SSE200);
ssedev = DEVICE(&mms->sse);
@ -376,6 +386,8 @@ static void musca_init(MachineState *machine)
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk);
qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk);
/*
* Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
* CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.