target-arm queue:
* Remove duplicate 'plus1' function from Neon and SVE decode * Fix offsets for TTBCR for big-endian hosts * docs: fix copyright date * docs: add license/version info to HTML footers * docs: add an About section * docs: document some more arm boards -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmD0ImIZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3gUVEACnpfDCg8KkeNpW/HGo5EXL TFfpyc1y9d8zVFuMCP5c98kv91bmFkgh6WJdnzIwC7pHhDiD7E+JMoB151pcRQPC yCB23YDhBlVDTFWZg8GQ33e6GFoAhgVvkpFQ7JDe8CoAdo28vc7QaZpoZBryKjhJ Pde3GWU1puuihlVHoL2RAOV6j9iHSwpDy8/VeMRiZjFs/p3QhzDwgyJidaMgBN+b Avw86iN4mHgPb5/mxEb51MaSEXcKTot01PPvd7hogTytMBXVCMIcQYauC1bgFi45 zsX4MMNbyrjluu6i+Y7/I6zRwpWR0sCvLn+2Pa/+V1H4mkzsifWGeHrzkEx4qjMP rb0vNbt7juCryfrBeG9jVoQ9SyUl2ml4sW4jCQrg6gA6A42Ic+NPjR6nA0smVHQj DM8ZadK4nv7sUY92pxGT5RsJYODV1fEYXWaGApjp/jqMjGXf+TZjCFcI5cxOltGM W4ijOT9QDKw+82+HM5a0HM6XMSpYMoqcYuJpUAkXqVqs2fidsuGLBJ9R7hWN6Ovu khfxrDMfH8Q61VsKNdGNYRbTRw7a1jakBh3Bf2eYykgT/6XogbpDb/13L2FaTJ8x fM1cPF/Lc2BWbHvna42nFGg5ST1DVKxszwSF1HFnevbNRw+R7z3KAG1KTuFEEbLI Glu71a6zSZhUSVp2IvCMdA== =aAVT -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210718' into staging target-arm queue: * Remove duplicate 'plus1' function from Neon and SVE decode * Fix offsets for TTBCR for big-endian hosts * docs: fix copyright date * docs: add license/version info to HTML footers * docs: add an About section * docs: document some more arm boards # gpg: Signature made Sun 18 Jul 2021 13:45:22 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210718: target/arm: Remove duplicate 'plus1' function from Neon and SVE decode docs: Add skeletal documentation of highbank and midway docs: Add skeletal documentation of the emcraft-sf2 docs: Add skeletal documentation of cubieboard docs: Add QEMU version information to HTML footer docs: Add license note to the HTML page footer docs: Add some actual About text to about/index.rst docs: Move deprecation, build and license info out of system/ docs: Remove "Contents:" lines from top-level subsections docs: Stop calling the top level subsections of our manual 'manuals' docs: Fix documentation Copyright date target/arm: Fix offsets for TTBCR Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
fd79f89c76
@ -560,6 +560,7 @@ S: Odd Fixes
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F: hw/*/allwinner*
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F: include/hw/*/allwinner*
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F: hw/arm/cubieboard.c
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F: docs/system/arm/cubieboard.rst
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Allwinner-h3
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M: Niek Linnenbank <nieklinnenbank@gmail.com>
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@ -642,6 +643,7 @@ L: qemu-arm@nongnu.org
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S: Odd Fixes
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F: hw/arm/highbank.c
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F: hw/net/xgmac.c
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F: docs/system/arm/highbank.rst
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Canon DIGIC
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M: Antony Pavlov <antonynpavlov@gmail.com>
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@ -1023,6 +1025,7 @@ M: Peter Maydell <peter.maydell@linaro.org>
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L: qemu-arm@nongnu.org
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S: Maintained
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F: hw/arm/msf2-som.c
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F: docs/system/arm/emcraft-sf2.rst
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ASPEED BMCs
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M: Cédric Le Goater <clg@kaod.org>
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@ -3451,6 +3454,7 @@ S: Maintained
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F: docs/conf.py
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F: docs/*/conf.py
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F: docs/sphinx/
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F: docs/_templates/
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Miscellaneous
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-------------
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14
docs/_templates/footer.html
vendored
Normal file
14
docs/_templates/footer.html
vendored
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@ -0,0 +1,14 @@
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{% extends "!footer.html" %}
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{% block extrafooter %}
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<!-- Empty para to force a blank line after "Built with Sphinx ..." -->
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<p></p>
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<p>This documentation is for QEMU version {{ version }}.</p>
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{% trans path=pathto('about/license') %}
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<p><a href="{{ path }}">QEMU and this manual are released under the
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GNU General Public License, version 2.</a></p>
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{% endtrans %}
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{{ super() }}
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{% endblock %}
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27
docs/about/index.rst
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27
docs/about/index.rst
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@ -0,0 +1,27 @@
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About QEMU
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==========
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QEMU is a generic and open source machine emulator and virtualizer.
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QEMU can be used in several different ways. The most common is for
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"system emulation", where it provides a virtual model of an
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entire machine (CPU, memory and emulated devices) to run a guest OS.
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In this mode the CPU may be fully emulated, or it may work with
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a hypervisor such as KVM, Xen, Hax or Hypervisor.Framework to
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allow the guest to run directly on the host CPU.
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The second supported way to use QEMU is "user mode emulation",
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where QEMU can launch processes compiled for one CPU on another CPU.
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In this mode the CPU is always emulated.
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QEMU also provides a number of standalone commandline utilities,
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such as the `qemu-img` disk image utility that allows you to create,
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convert and modify disk images.
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.. toctree::
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:maxdepth: 2
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build-platforms
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deprecated
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removed-features
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license
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@ -87,7 +87,7 @@ master_doc = 'index'
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# General information about the project.
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project = u'QEMU'
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copyright = u'2020, The QEMU Project Developers'
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copyright = u'2021, The QEMU Project Developers'
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author = u'The QEMU Project Developers'
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# The version info for the project you're documenting, acts as replacement for
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@ -1,15 +1,10 @@
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.. This is the top level page for the 'devel' manual.
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Developer Information
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=====================
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This manual documents various parts of the internals of QEMU.
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This section of the manual documents various parts of the internals of QEMU.
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You only need to read it if you are interested in reading or
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modifying QEMU's source code.
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Contents:
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.. toctree::
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:maxdepth: 2
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:includehidden:
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@ -10,6 +10,7 @@ Welcome to QEMU's documentation!
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:maxdepth: 2
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:caption: Contents:
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about/index
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system/index
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user/index
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tools/index
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@ -1,13 +1,8 @@
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.. This is the top level page for the 'interop' manual.
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System Emulation Management and Interoperability
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================================================
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This manual contains documents and specifications that are useful
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for making QEMU interoperate with other software.
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Contents:
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This section of the manual contains documents and specifications that
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are useful for making QEMU interoperate with other software.
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.. toctree::
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:maxdepth: 2
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@ -44,6 +44,7 @@ if build_docs
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meson.source_root() / 'docs/sphinx/qapidoc.py',
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meson.source_root() / 'docs/sphinx/qmp_lexer.py',
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qapi_gen_depends ]
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sphinx_template_files = [ meson.source_root() / 'docs/_templates/footer.html' ]
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have_ga = have_tools and config_host.has_key('CONFIG_GUEST_AGENT')
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@ -76,7 +77,7 @@ if build_docs
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output: 'docs.stamp',
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input: files('conf.py'),
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depfile: 'docs.d',
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depend_files: sphinx_extn_depends,
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depend_files: [ sphinx_extn_depends, sphinx_template_files ],
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command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
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'-Ddepfile_stamp=@OUTPUT0@',
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'-b', 'html', '-d', private_dir,
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@ -1,11 +1,8 @@
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.. This is the top level page for the 'specs' manual
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System Emulation Guest Hardware Specifications
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==============================================
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Contents:
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This section of the manual contains specifications of
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guest hardware that is specific to QEMU.
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.. toctree::
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:maxdepth: 2
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16
docs/system/arm/cubieboard.rst
Normal file
16
docs/system/arm/cubieboard.rst
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Cubietech Cubieboard (``cubieboard``)
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=====================================
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The ``cubieboard`` model emulates the Cubietech Cubieboard,
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which is a Cortex-A8 based single-board computer using
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the AllWinner A10 SoC.
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Emulated devices:
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- Timer
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- UART
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- RTC
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- EMAC
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- SDHCI
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- USB controller
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- SATA controller
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15
docs/system/arm/emcraft-sf2.rst
Normal file
15
docs/system/arm/emcraft-sf2.rst
Normal file
@ -0,0 +1,15 @@
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Emcraft SmartFusion2 SOM kit (``emcraft-sf2``)
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==============================================
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The ``emcraft-sf2`` board emulates the SmartFusion2 SOM kit from
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Emcraft (M2S010). This is a System-on-Module from EmCraft systems,
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based on the SmartFusion2 SoC FPGA from Microsemi Corporation.
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The SoC is based on a Cortex-M4 processor.
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Emulated devices:
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- System timer
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- System registers
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- SPI controller
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- UART
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- EMAC
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19
docs/system/arm/highbank.rst
Normal file
19
docs/system/arm/highbank.rst
Normal file
@ -0,0 +1,19 @@
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Calxeda Highbank and Midway (``highbank``, ``midway``)
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======================================================
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``highbank`` is a model of the Calxeda Highbank (ECX-1000) system,
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which has four Cortex-A9 cores.
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``midway`` is a model of the Calxeda Midway (ECX-2000) system,
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which has four Cortex-A15 cores.
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Emulated devices:
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- L2x0 cache controller
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- SP804 dual timer
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- PL011 UART
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- PL061 GPIOs
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- PL031 RTC
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- PL022 synchronous serial port controller
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- AHCI
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- XGMAC ethernet controllers
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@ -1,16 +1,11 @@
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.. This is the top level page for the 'system' manual.
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System Emulation
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================
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This manual is the overall guide for users using QEMU
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This section of the manual is the overall guide for users using QEMU
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for full system emulation (as opposed to user-mode emulation).
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This includes working with hypervisors such as KVM, Xen, Hax
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or Hypervisor.Framework.
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Contents:
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.. toctree::
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:maxdepth: 3
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@ -40,7 +35,3 @@ Contents:
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targets
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security
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multi-process
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deprecated
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removed-features
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build-platforms
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license
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@ -85,6 +85,9 @@ undocumented; you can get a complete list by running
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arm/aspeed
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arm/sabrelite
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arm/digic
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arm/cubieboard
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arm/emcraft-sf2
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arm/highbank
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arm/musicpal
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arm/gumstix
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arm/nrf
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@ -1,11 +1,8 @@
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.. This is the top level page for the 'tools' manual
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Tools
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=====
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Contents:
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This section of the manual documents QEMU's "tools": its
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command line utilities and other standalone programs.
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.. toctree::
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:maxdepth: 2
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@ -1,15 +1,10 @@
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.. This is the top level page for the 'user' manual.
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User Mode Emulation
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===================
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This manual is the overall guide for users using QEMU
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This section of the manual is the overall guide for users using QEMU
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for user-mode emulation. In this mode, QEMU can launch
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processes compiled for one CPU on another CPU.
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|
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Contents:
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.. toctree::
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:maxdepth: 2
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@ -4106,8 +4106,9 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
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.raw_writefn = vmsa_ttbcr_raw_write,
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
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offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
|
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/* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]),
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offsetof(CPUARMState, cp15.tcr_el[1])} },
|
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REGINFO_SENTINEL
|
||||
};
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@ -4118,8 +4119,10 @@ static const ARMCPRegInfo ttbcr2_reginfo = {
|
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.name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
|
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.type = ARM_CP_ALIAS,
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.bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
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offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
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.bank_fieldoffsets = {
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offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr),
|
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offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr),
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},
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};
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static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
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@ -41,8 +41,8 @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
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vd=%vd_dp
|
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||||
# Neon load/store single structure to one lane
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%imm1_5_p1 5:1 !function=plus1
|
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%imm1_6_p1 6:1 !function=plus1
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%imm1_5_p1 5:1 !function=plus_1
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%imm1_6_p1 6:1 !function=plus_1
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VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
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vd=%vd_dp size=0 stride=1
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@ -38,7 +38,7 @@
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||||
# which is 0 for fp16 and 1 for fp32 into a MO_* constant.
|
||||
# (Note that this is the reverse of the sense of the 1-bit size
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||||
# field in the 3same_fp Neon insns.)
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||||
%vcadd_size 20:1 !function=plus1
|
||||
%vcadd_size 20:1 !function=plus_1
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||||
VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \
|
||||
vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size
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||||
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||||
@ -22,7 +22,7 @@
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||||
###########################################################################
|
||||
# Named fields. These are primarily for disjoint fields.
|
||||
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||||
%imm4_16_p1 16:4 !function=plus1
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||||
%imm4_16_p1 16:4 !function=plus_1
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||||
%imm6_22_5 22:1 5:5
|
||||
%imm7_22_16 22:2 16:5
|
||||
%imm8_16_10 16:5 10:3
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@ -28,11 +28,6 @@
|
||||
#include "translate.h"
|
||||
#include "translate-a32.h"
|
||||
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||||
static inline int plus1(DisasContext *s, int x)
|
||||
{
|
||||
return x + 1;
|
||||
}
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||||
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||||
static inline int neon_3same_fp_size(DisasContext *s, int x)
|
||||
{
|
||||
/* Convert 0==fp32, 1==fp16 into a MO_* value */
|
||||
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||||
@ -70,11 +70,6 @@ static int tszimm_shl(DisasContext *s, int x)
|
||||
return x - (8 << tszimm_esz(s, x));
|
||||
}
|
||||
|
||||
static inline int plus1(DisasContext *s, int x)
|
||||
{
|
||||
return x + 1;
|
||||
}
|
||||
|
||||
/* The SH bit is in bit 8. Extract the low 8 and shift. */
|
||||
static inline int expand_imm_sh8s(DisasContext *s, int x)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user