OpenE2K/qemu-e2k
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sh4 target (Samuel Tardieu)

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1861 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2006-04-27 21:07:38 +00:00
parent 66a93e0f47
commit fdf9b3e831
24 changed files with 5905 additions and 6 deletions
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20
Makefile.target
View File

@ -225,6 +225,10 @@ ifeq ($(TARGET_BASE_ARCH), arm)
LIBOBJS+= op_helper.o helper.o
endif
ifeq ($(TARGET_BASE_ARCH), sh4)
LIBOBJS+= op_helper.o helper.o
endif
# NOTE: the disassembler code is only needed for debugging
LIBOBJS+=disas.o
ifeq ($(findstring i386, $(TARGET_ARCH) $(ARCH)),i386)
@ -254,6 +258,9 @@ endif
ifeq ($(findstring m68k, $(TARGET_ARCH) $(ARCH)),m68k)
LIBOBJS+=m68k-dis.o
endif
ifeq ($(findstring sh4, $(TARGET_ARCH) $(ARCH)),sh4)
LIBOBJS+=sh4-dis.o
endif
ifdef CONFIG_GDBSTUB
OBJS+=gdbstub.o
@ -341,6 +348,9 @@ ifeq ($(TARGET_BASE_ARCH), arm)
VL_OBJS+= integratorcp.o versatilepb.o ps2.o smc91c111.o arm_pic.o arm_timer.o
VL_OBJS+= pl011.o pl050.o pl080.o pl110.o pl190.o
endif
ifeq ($(TARGET_BASE_ARCH), sh4)
VL_OBJS+= shix.o sh7750.o sh7750_regnames.o tc58128.o
endif
ifdef CONFIG_GDBSTUB
VL_OBJS+=gdbstub.o
endif
@ -462,6 +472,16 @@ endif
loader.o: loader.c elf_ops.h
ifeq ($(TARGET_ARCH), sh4)
op.o: op.c op_mem.c cpu.h
op_helper.o: op_helper.c exec.h cpu.h
helper.o: helper.c exec.h cpu.h
sh7750.o: sh7750.c sh7750.h sh7750_regs.h sh7750_regnames.h cpu.h
shix.o: shix.c sh7750.h sh7750_regs.h sh7750_regnames.h tc58128.h
sh7750_regnames.o: sh7750_regnames.c sh7750_regnames.h sh7750_regs.h
tc58128.o: tc58128.c tc58128.h sh7750.h
endif
%.o: %.c
$(CC) $(CFLAGS) $(DEFINES) -c -o $@ $<

6
configure vendored
View File

@ -359,7 +359,7 @@ if test -z "$target_list" ; then
fi
# the following are Linux specific
if [ "$user" = "yes" ] ; then
target_list="i386-user arm-user armeb-user sparc-user ppc-user mips-user mipsel-user $target_list"
target_list="i386-user arm-user armeb-user sparc-user ppc-user mips-user mipsel-user sh4-user $target_list"
fi
else
target_list=`echo "$target_list" | sed -e 's/,/ /g'`
@ -807,6 +807,10 @@ elif test "$target_cpu" = "mips" -o "$target_cpu" = "mipsel" ; then
echo "TARGET_ARCH=mips" >> $config_mak
echo "#define TARGET_ARCH \"mips\"" >> $config_h
echo "#define TARGET_MIPS 1" >> $config_h
elif test "$target_cpu" = "sh4" ; then
echo "TARGET_ARCH=sh4" >> $config_mak
echo "#define TARGET_ARCH \"sh4\"" >> $config_h
echo "#define TARGET_SH4 1" >> $config_h
else
echo "Unsupported target CPU"
exit 1

7
cpu-all.h
View File

@ -732,6 +732,13 @@ void page_unprotect_range(target_ulong data, target_ulong data_size);
#define cpu_gen_code cpu_mips_gen_code
#define cpu_signal_handler cpu_mips_signal_handler
#elif defined(TARGET_SH4)
#define CPUState CPUSH4State
#define cpu_init cpu_sh4_init
#define cpu_exec cpu_sh4_exec
#define cpu_gen_code cpu_sh4_gen_code
#define cpu_signal_handler cpu_sh4_signal_handler
#else
#error unsupported target CPU

63
cpu-exec.c
View File

@ -190,6 +190,10 @@ static inline TranslationBlock *tb_find_fast(void)
flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
cs_base = 0;
pc = env->PC;
#elif defined(TARGET_SH4)
flags = env->sr & (SR_MD | SR_RB);
cs_base = 0; /* XXXXX */
pc = env->pc;
#else
#error unsupported CPU
#endif
@ -363,6 +367,8 @@ int cpu_exec(CPUState *env1)
#endif
#elif defined(TARGET_PPC)
#elif defined(TARGET_MIPS)
#elif defined(TARGET_SH4)
/* XXXXX */
#else
#error unsupported target CPU
#endif
@ -407,6 +413,8 @@ int cpu_exec(CPUState *env1)
do_interrupt(env->exception_index);
#elif defined(TARGET_ARM)
do_interrupt(env);
#elif defined(TARGET_SH4)
do_interrupt(env);
#endif
}
env->exception_index = -1;
@ -550,6 +558,8 @@ int cpu_exec(CPUState *env1)
env->exception_index = EXCP_IRQ;
do_interrupt(env);
}
#elif defined(TARGET_SH4)
/* XXXXX */
#endif
if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
@ -608,6 +618,8 @@ int cpu_exec(CPUState *env1)
cpu_dump_state(env, logfile, fprintf, 0);
#elif defined(TARGET_MIPS)
cpu_dump_state(env, logfile, fprintf, 0);
#elif defined(TARGET_SH4)
cpu_dump_state(env, logfile, fprintf, 0);
#else
#error unsupported target CPU
#endif
@ -817,6 +829,8 @@ int cpu_exec(CPUState *env1)
#endif
#elif defined(TARGET_PPC)
#elif defined(TARGET_MIPS)
#elif defined(TARGET_SH4)
/* XXXXX */
#else
#error unsupported target CPU
#endif
@ -1121,6 +1135,55 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
return 1;
}
#elif defined (TARGET_SH4)
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
int is_write, sigset_t *old_set,
void *puc)
{
TranslationBlock *tb;
int ret;
if (cpu_single_env)
env = cpu_single_env; /* XXX: find a correct solution for multithread */
#if defined(DEBUG_SIGNAL)
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
pc, address, is_write, *(unsigned long *)old_set);
#endif
/* XXX: locking issue */
if (is_write && page_unprotect(h2g(address), pc, puc)) {
return 1;
}
/* see if it is an MMU fault */
ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
if (ret < 0)
return 0; /* not an MMU fault */
if (ret == 0)
return 1; /* the MMU fault was handled without causing real CPU fault */
/* now we have a real cpu fault */
tb = tb_find_pc(pc);
if (tb) {
/* the PC is inside the translated code. It means that we have
a virtual CPU fault */
cpu_restore_state(tb, env, pc, puc);
}
if (ret == 1) {
#if 0
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
env->nip, env->error_code, tb);
#endif
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
sigprocmask(SIG_SETMASK, old_set, NULL);
// do_raise_exception_err(env->exception_index, env->error_code);
} else {
/* activate soft MMU for this block */
cpu_resume_from_signal(env, puc);
}
/* never comes here */
return 1;
}
#else
#error unsupported target CPU
#endif

15
dis-asm.h
View File

@ -163,10 +163,23 @@ enum bfd_architecture
#define bfd_mach_z8002 2
bfd_arch_h8500, /* Hitachi H8/500 */
bfd_arch_sh, /* Hitachi SH */
#define bfd_mach_sh 0
#define bfd_mach_sh 1
#define bfd_mach_sh2 0x20
#define bfd_mach_sh_dsp 0x2d
#define bfd_mach_sh2a 0x2a
#define bfd_mach_sh2a_nofpu 0x2b
#define bfd_mach_sh2e 0x2e
#define bfd_mach_sh3 0x30
#define bfd_mach_sh3_nommu 0x31
#define bfd_mach_sh3_dsp 0x3d
#define bfd_mach_sh3e 0x3e
#define bfd_mach_sh4 0x40
#define bfd_mach_sh4_nofpu 0x41
#define bfd_mach_sh4_nommu_nofpu 0x42
#define bfd_mach_sh4a 0x4a
#define bfd_mach_sh4a_nofpu 0x4b
#define bfd_mach_sh4al_dsp 0x4d
#define bfd_mach_sh5 0x50
bfd_arch_alpha, /* Dec Alpha */
bfd_arch_arm, /* Advanced Risc Machines ARM */
#define bfd_mach_arm_2 1

5
disas.c
View File

@ -73,7 +73,7 @@ generic_print_address (addr, info)
bfd_vma addr;
struct disassemble_info *info;
{
(*info->fprintf_func) (info->stream, "0x%llx", addr);
(*info->fprintf_func) (info->stream, "0x%llx", addr);
}
/* Just return the given address. */
@ -194,6 +194,9 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags)
#endif
#elif defined(TARGET_M68K)
print_insn = print_insn_m68k;
#elif defined(TARGET_SH4)
disasm_info.mach = bfd_mach_sh4;
print_insn = print_insn_sh;
#else
fprintf(out, "0x" TARGET_FMT_lx
": Asm output not supported on this arch\n", code);

2
exec-all.h
View File

@ -560,6 +560,8 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
is_user = (env->psrs == 0);
#elif defined (TARGET_ARM)
is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
#elif defined (TARGET_SH4)
is_user = ((env->sr & SR_MD) == 0);
#else
#error unimplemented CPU
#endif

43
gdbstub.c
View File

@ -487,6 +487,45 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
env->PC = tswapl(*(uint32_t *)ptr);
ptr += 4;
}
#elif defined (TARGET_SH4)
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
uint32_t *ptr = (uint32_t *)mem_buf;
int i;
#define SAVE(x) *ptr++=tswapl(x)
for (i = 0; i < 16; i++) SAVE(env->gregs[i]);
SAVE (env->pc);
SAVE (env->pr);
SAVE (env->gbr);
SAVE (env->vbr);
SAVE (env->mach);
SAVE (env->macl);
SAVE (env->sr);
SAVE (0); /* TICKS */
SAVE (0); /* STALLS */
SAVE (0); /* CYCLES */
SAVE (0); /* INSTS */
SAVE (0); /* PLR */
return ((uint8_t *)ptr - mem_buf);
}
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
{
uint32_t *ptr = (uint32_t *)mem_buf;
int i;
#define LOAD(x) (x)=*ptr++;
for (i = 0; i < 16; i++) LOAD(env->gregs[i]);
LOAD (env->pc);
LOAD (env->pr);
LOAD (env->gbr);
LOAD (env->vbr);
LOAD (env->mach);
LOAD (env->macl);
LOAD (env->sr);
}
#else
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
@ -531,6 +570,8 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
env->npc = addr + 4;
#elif defined (TARGET_ARM)
env->regs[15] = addr;
#elif defined (TARGET_SH4)
env->pc = addr;
#endif
}
#ifdef CONFIG_USER_ONLY
@ -551,6 +592,8 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
env->npc = addr + 4;
#elif defined (TARGET_ARM)
env->regs[15] = addr;
#elif defined (TARGET_SH4)
env->pc = addr;
#endif
}
cpu_single_step(env, 1);

24
linux-user/elfload.c
View File

@ -274,6 +274,30 @@ static inline void init_thread(struct target_pt_regs *regs, struct image_info *i
#endif /* TARGET_MIPS */
#ifdef TARGET_SH4
#define ELF_START_MMAP 0x80000000
#define elf_check_arch(x) ( (x) == EM_SH )
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2LSB
#define ELF_ARCH EM_SH
#define ELF_PLAT_INIT(_r) /* XXXXX */
static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop)
{
/* Check other registers XXXXX */
regs->pc = infop->entry;
regs->regs[15] = infop->start_stack - 16 * 4;
}
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
#endif
#ifndef ELF_PLATFORM
#define ELF_PLATFORM (NULL)
#endif

41
linux-user/main.c
View File

@ -1387,6 +1387,38 @@ void cpu_loop(CPUMIPSState *env)
}
#endif
#ifdef TARGET_SH4
void cpu_loop (CPUState *env)
{
int trapnr, ret;
// target_siginfo_t info;
while (1) {
trapnr = cpu_sh4_exec (env);
switch (trapnr) {
case 0x160:
ret = do_syscall(env,
env->gregs[0x13],
env->gregs[0x14],
env->gregs[0x15],
env->gregs[0x16],
env->gregs[0x17],
env->gregs[0x10],
0);
env->gregs[0x10] = ret;
env->pc += 2;
break;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
cpu_dump_state(env, stderr, fprintf, 0);
exit (1);
}
process_pending_signals (env);
}
}
#endif
void usage(void)
{
printf("qemu-" TARGET_ARCH " version " QEMU_VERSION ", Copyright (c) 2003-2005 Fabrice Bellard\n"
@ -1665,6 +1697,15 @@ int main(int argc, char **argv)
}
env->PC = regs->cp0_epc;
}
#elif defined(TARGET_SH4)
{
int i;
for(i = 0; i < 16; i++) {
env->gregs[i] = regs->regs[i];
}
env->pc = regs->pc;
}
#else
#error unsupported target CPU
#endif

12
linux-user/sh4/syscall.h Normal file
View File

@ -0,0 +1,12 @@
struct target_pt_regs {
unsigned long regs[16];
unsigned long pc;
unsigned long pr;
unsigned long sr;
unsigned long gbr;
unsigned long mach;
unsigned long macl;
long tra;
};
#define UNAME_MACHINE "sh4"

292
linux-user/sh4/syscall_nr.h Normal file
View File

@ -0,0 +1,292 @@
/*
* This file contains the system call numbers.
*/
#define TARGET_NR_restart_syscall 0
#define TARGET_NR_exit 1
#define TARGET_NR_fork 2
#define TARGET_NR_read 3
#define TARGET_NR_write 4
#define TARGET_NR_open 5
#define TARGET_NR_close 6
#define TARGET_NR_waitpid 7
#define TARGET_NR_creat 8
#define TARGET_NR_link 9
#define TARGET_NR_unlink 10
#define TARGET_NR_execve 11
#define TARGET_NR_chdir 12
#define TARGET_NR_time 13
#define TARGET_NR_mknod 14
#define TARGET_NR_chmod 15
#define TARGET_NR_lchown 16
#define TARGET_NR_break 17
#define TARGET_NR_oldstat 18
#define TARGET_NR_lseek 19
#define TARGET_NR_getpid 20
#define TARGET_NR_mount 21
#define TARGET_NR_umount 22
#define TARGET_NR_setuid 23
#define TARGET_NR_getuid 24
#define TARGET_NR_stime 25
#define TARGET_NR_ptrace 26
#define TARGET_NR_alarm 27
#define TARGET_NR_oldfstat 28
#define TARGET_NR_pause 29
#define TARGET_NR_utime 30
#define TARGET_NR_stty 31
#define TARGET_NR_gtty 32
#define TARGET_NR_access 33
#define TARGET_NR_nice 34
#define TARGET_NR_ftime 35
#define TARGET_NR_sync 36
#define TARGET_NR_kill 37
#define TARGET_NR_rename 38
#define TARGET_NR_mkdir 39
#define TARGET_NR_rmdir 40
#define TARGET_NR_dup 41
#define TARGET_NR_pipe 42
#define TARGET_NR_times 43
#define TARGET_NR_prof 44
#define TARGET_NR_brk 45
#define TARGET_NR_setgid 46
#define TARGET_NR_getgid 47
#define TARGET_NR_signal 48
#define TARGET_NR_geteuid 49
#define TARGET_NR_getegid 50
#define TARGET_NR_acct 51
#define TARGET_NR_umount2 52
#define TARGET_NR_lock 53
#define TARGET_NR_ioctl 54
#define TARGET_NR_fcntl 55
#define TARGET_NR_mpx 56
#define TARGET_NR_setpgid 57
#define TARGET_NR_ulimit 58
#define TARGET_NR_oldolduname 59
#define TARGET_NR_umask 60
#define TARGET_NR_chroot 61
#define TARGET_NR_ustat 62
#define TARGET_NR_dup2 63
#define TARGET_NR_getppid 64
#define TARGET_NR_getpgrp 65
#define TARGET_NR_setsid 66
#define TARGET_NR_sigaction 67
#define TARGET_NR_sgetmask 68
#define TARGET_NR_ssetmask 69
#define TARGET_NR_setreuid 70
#define TARGET_NR_setregid 71
#define TARGET_NR_sigsuspend 72
#define TARGET_NR_sigpending 73
#define TARGET_NR_sethostname 74
#define TARGET_NR_setrlimit 75
#define TARGET_NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
#define TARGET_NR_getrusage 77
#define TARGET_NR_gettimeofday 78
#define TARGET_NR_settimeofday 79
#define TARGET_NR_getgroups 80
#define TARGET_NR_setgroups 81
#define TARGET_NR_select 82
#define TARGET_NR_symlink 83
#define TARGET_NR_oldlstat 84
#define TARGET_NR_readlink 85
#define TARGET_NR_uselib 86
#define TARGET_NR_swapon 87
#define TARGET_NR_reboot 88
#define TARGET_NR_readdir 89
#define TARGET_NR_mmap 90
#define TARGET_NR_munmap 91
#define TARGET_NR_truncate 92
#define TARGET_NR_ftruncate 93
#define TARGET_NR_fchmod 94
#define TARGET_NR_fchown 95
#define TARGET_NR_getpriority 96
#define TARGET_NR_setpriority 97
#define TARGET_NR_profil 98
#define TARGET_NR_statfs 99
#define TARGET_NR_fstatfs 100
#define TARGET_NR_ioperm 101
#define TARGET_NR_socketcall 102
#define TARGET_NR_syslog 103
#define TARGET_NR_setitimer 104
#define TARGET_NR_getitimer 105
#define TARGET_NR_stat 106
#define TARGET_NR_lstat 107
#define TARGET_NR_fstat 108
#define TARGET_NR_olduname 109
#define TARGET_NR_iopl 110
#define TARGET_NR_vhangup 111
#define TARGET_NR_idle 112
#define TARGET_NR_vm86old 113
#define TARGET_NR_wait4 114
#define TARGET_NR_swapoff 115
#define TARGET_NR_sysinfo 116
#define TARGET_NR_ipc 117
#define TARGET_NR_fsync 118
#define TARGET_NR_sigreturn 119
#define TARGET_NR_clone 120
#define TARGET_NR_setdomainname 121
#define TARGET_NR_uname 122
#define TARGET_NR_modify_ldt 123
#define TARGET_NR_adjtimex 124
#define TARGET_NR_mprotect 125
#define TARGET_NR_sigprocmask 126
#define TARGET_NR_create_module 127
#define TARGET_NR_init_module 128
#define TARGET_NR_delete_module 129
#define TARGET_NR_get_kernel_syms 130
#define TARGET_NR_quotactl 131
#define TARGET_NR_getpgid 132
#define TARGET_NR_fchdir 133
#define TARGET_NR_bdflush 134
#define TARGET_NR_sysfs 135
#define TARGET_NR_personality 136
#define TARGET_NR_afs_syscall 137 /* Syscall for Andrew File System */
#define TARGET_NR_setfsuid 138
#define TARGET_NR_setfsgid 139
#define TARGET_NR__llseek 140
#define TARGET_NR_getdents 141
#define TARGET_NR__newselect 142
#define TARGET_NR_flock 143
#define TARGET_NR_msync 144
#define TARGET_NR_readv 145
#define TARGET_NR_writev 146
#define TARGET_NR_getsid 147
#define TARGET_NR_fdatasync 148
#define TARGET_NR__sysctl 149
#define TARGET_NR_mlock 150
#define TARGET_NR_munlock 151
#define TARGET_NR_mlockall 152
#define TARGET_NR_munlockall 153
#define TARGET_NR_sched_setparam 154
#define TARGET_NR_sched_getparam 155
#define TARGET_NR_sched_setscheduler 156
#define TARGET_NR_sched_getscheduler 157
#define TARGET_NR_sched_yield 158
#define TARGET_NR_sched_get_priority_max 159
#define TARGET_NR_sched_get_priority_min 160
#define TARGET_NR_sched_rr_get_interval 161
#define TARGET_NR_nanosleep 162
#define TARGET_NR_mremap 163
#define TARGET_NR_setresuid 164
#define TARGET_NR_getresuid 165
#define TARGET_NR_vm86 166
#define TARGET_NR_query_module 167
#define TARGET_NR_poll 168
#define TARGET_NR_nfsservctl 169
#define TARGET_NR_setresgid 170
#define TARGET_NR_getresgid 171
#define TARGET_NR_prctl 172
#define TARGET_NR_rt_sigreturn 173
#define TARGET_NR_rt_sigaction 174
#define TARGET_NR_rt_sigprocmask 175
#define TARGET_NR_rt_sigpending 176
#define TARGET_NR_rt_sigtimedwait 177
#define TARGET_NR_rt_sigqueueinfo 178
#define TARGET_NR_rt_sigsuspend 179
#define TARGET_NR_pread64 180
#define TARGET_NR_pwrite64 181
#define TARGET_NR_chown 182
#define TARGET_NR_getcwd 183
#define TARGET_NR_capget 184
#define TARGET_NR_capset 185
#define TARGET_NR_sigaltstack 186
#define TARGET_NR_sendfile 187
#define TARGET_NR_streams1 188 /* some people actually want it */
#define TARGET_NR_streams2 189 /* some people actually want it */
#define TARGET_NR_vfork 190
#define TARGET_NR_ugetrlimit 191 /* SuS compliant getrlimit */
#define TARGET_NR_mmap2 192
#define TARGET_NR_truncate64 193
#define TARGET_NR_ftruncate64 194
#define TARGET_NR_stat64 195
#define TARGET_NR_lstat64 196
#define TARGET_NR_fstat64 197
#define TARGET_NR_lchown32 198
#define TARGET_NR_getuid32 199
#define TARGET_NR_getgid32 200
#define TARGET_NR_geteuid32 201
#define TARGET_NR_getegid32 202
#define TARGET_NR_setreuid32 203
#define TARGET_NR_setregid32 204
#define TARGET_NR_getgroups32 205
#define TARGET_NR_setgroups32 206
#define TARGET_NR_fchown32 207
#define TARGET_NR_setresuid32 208
#define TARGET_NR_getresuid32 209
#define TARGET_NR_setresgid32 210
#define TARGET_NR_getresgid32 211
#define TARGET_NR_chown32 212
#define TARGET_NR_setuid32 213
#define TARGET_NR_setgid32 214
#define TARGET_NR_setfsuid32 215
#define TARGET_NR_setfsgid32 216
#define TARGET_NR_pivot_root 217
#define TARGET_NR_mincore 218
#define TARGET_NR_madvise 219
#define TARGET_NR_getdents64 220
#define TARGET_NR_fcntl64 221
/* 223 is unused */
#define TARGET_NR_gettid 224
#define TARGET_NR_setxattr 226
#define TARGET_NR_lsetxattr 227
#define TARGET_NR_fsetxattr 228
#define TARGET_NR_getxattr 229
#define TARGET_NR_lgetxattr 230
#define TARGET_NR_fgetxattr 231
#define TARGET_NR_listxattr 232
#define TARGET_NR_llistxattr 233
#define TARGET_NR_flistxattr 234
#define TARGET_NR_removexattr 235
#define TARGET_NR_lremovexattr 236
#define TARGET_NR_fremovexattr 237
#define TARGET_NR_tkill 238
#define TARGET_NR_sendfile64 239
#define TARGET_NR_futex 240
#define TARGET_NR_sched_setaffinity 241
#define TARGET_NR_sched_getaffinity 242
#define TARGET_NR_set_thread_area 243
#define TARGET_NR_get_thread_area 244
#define TARGET_NR_io_setup 245
#define TARGET_NR_io_destroy 246
#define TARGET_NR_io_getevents 247
#define TARGET_NR_io_submit 248
#define TARGET_NR_io_cancel 249
#define TARGET_NR_fadvise64 250
#define TARGET_NR_exit_group 252
#define TARGET_NR_lookup_dcookie 253
#define TARGET_NR_epoll_create 254
#define TARGET_NR_epoll_ctl 255
#define TARGET_NR_epoll_wait 256
#define TARGET_NR_remap_file_pages 257
#define TARGET_NR_set_tid_address 258
#define TARGET_NR_timer_create 259
#define TARGET_NR_timer_settime (TARGET_NR_timer_create+1)
#define TARGET_NR_timer_gettime (TARGET_NR_timer_create+2)
#define TARGET_NR_timer_getoverrun (TARGET_NR_timer_create+3)
#define TARGET_NR_timer_delete (TARGET_NR_timer_create+4)
#define TARGET_NR_clock_settime (TARGET_NR_timer_create+5)
#define TARGET_NR_clock_gettime (TARGET_NR_timer_create+6)
#define TARGET_NR_clock_getres (TARGET_NR_timer_create+7)
#define TARGET_NR_clock_nanosleep (TARGET_NR_timer_create+8)
#define TARGET_NR_statfs64 268
#define TARGET_NR_fstatfs64 269
#define TARGET_NR_tgkill 270
#define TARGET_NR_utimes 271
#define TARGET_NR_fadvise64_64 272
#define TARGET_NR_vserver 273
#define TARGET_NR_mbind 274
#define TARGET_NR_get_mempolicy 275
#define TARGET_NR_set_mempolicy 276
#define TARGET_NR_mq_open 277
#define TARGET_NR_mq_unlink (TARGET_NR_mq_open+1)
#define TARGET_NR_mq_timedsend (TARGET_NR_mq_open+2)
#define TARGET_NR_mq_timedreceive (TARGET_NR_mq_open+3)
#define TARGET_NR_mq_notify (TARGET_NR_mq_open+4)
#define TARGET_NR_mq_getsetattr (TARGET_NR_mq_open+5)
#define TARGET_NR_sys_kexec_load 283
#define TARGET_NR_waitid 284
#define TARGET_NR_add_key 285
#define TARGET_NR_request_key 286
#define TARGET_NR_keyctl 287
#define TARGET_NR_readahead 225 /* XXXXX */

274
linux-user/sh4/termbits.h Normal file
View File

@ -0,0 +1,274 @@
/* from asm/termbits.h */
#define TARGET_NCCS 19
struct target_termios {
unsigned int c_iflag; /* input mode flags */
unsigned int c_oflag; /* output mode flags */
unsigned int c_cflag; /* control mode flags */
unsigned int c_lflag; /* local mode flags */
unsigned char c_line; /* line discipline */
unsigned char c_cc[TARGET_NCCS]; /* control characters */
};
/* c_cc characters */
#define TARGET_VINTR 0
#define TARGET_VQUIT 1
#define TARGET_VERASE 2
#define TARGET_VKILL 3
#define TARGET_VEOF 4
#define TARGET_VTIME 5
#define TARGET_VMIN 6
#define TARGET_VSWTC 7
#define TARGET_VSTART 8
#define TARGET_VSTOP 9
#define TARGET_VSUSP 10
#define TARGET_VEOL 11
#define TARGET_VREPRINT 12
#define TARGET_VDISCARD 13
#define TARGET_VWERASE 14
#define TARGET_VLNEXT 15
#define TARGET_VEOL2 16
/* c_iflag bits */
#define TARGET_IGNBRK 0000001
#define TARGET_BRKINT 0000002
#define TARGET_IGNPAR 0000004
#define TARGET_PARMRK 0000010
#define TARGET_INPCK 0000020
#define TARGET_ISTRIP 0000040
#define TARGET_INLCR 0000100
#define TARGET_IGNCR 0000200
#define TARGET_ICRNL 0000400
#define TARGET_IUCLC 0001000
#define TARGET_IXON 0002000
#define TARGET_IXANY 0004000
#define TARGET_IXOFF 0010000
#define TARGET_IMAXBEL 0020000
#define TARGET_IUTF8 0040000
/* c_oflag bits */
#define TARGET_OPOST 0000001
#define TARGET_OLCUC 0000002
#define TARGET_ONLCR 0000004
#define TARGET_OCRNL 0000010
#define TARGET_ONOCR 0000020
#define TARGET_ONLRET 0000040
#define TARGET_OFILL 0000100
#define TARGET_OFDEL 0000200
#define TARGET_NLDLY 0000400
#define TARGET_NL0 0000000
#define TARGET_NL1 0000400
#define TARGET_CRDLY 0003000
#define TARGET_CR0 0000000
#define TARGET_CR1 0001000
#define TARGET_CR2 0002000
#define TARGET_CR3 0003000
#define TARGET_TABDLY 0014000
#define TARGET_TAB0 0000000
#define TARGET_TAB1 0004000
#define TARGET_TAB2 0010000
#define TARGET_TAB3 0014000
#define TARGET_XTABS 0014000
#define TARGET_BSDLY 0020000
#define TARGET_BS0 0000000
#define TARGET_BS1 0020000
#define TARGET_VTDLY 0040000
#define TARGET_VT0 0000000
#define TARGET_VT1 0040000
#define TARGET_FFDLY 0100000
#define TARGET_FF0 0000000
#define TARGET_FF1 0100000
/* c_cflag bit meaning */
#define TARGET_CBAUD 0010017
#define TARGET_B0 0000000 /* hang up */
#define TARGET_B50 0000001
#define TARGET_B75 0000002
#define TARGET_B110 0000003
#define TARGET_B134 0000004
#define TARGET_B150 0000005
#define TARGET_B200 0000006
#define TARGET_B300 0000007
#define TARGET_B600 0000010
#define TARGET_B1200 0000011
#define TARGET_B1800 0000012
#define TARGET_B2400 0000013
#define TARGET_B4800 0000014
#define TARGET_B9600 0000015
#define TARGET_B19200 0000016
#define TARGET_B38400 0000017
#define TARGET_EXTA B19200
#define TARGET_EXTB B38400
#define TARGET_CSIZE 0000060
#define TARGET_CS5 0000000
#define TARGET_CS6 0000020
#define TARGET_CS7 0000040
#define TARGET_CS8 0000060
#define TARGET_CSTOPB 0000100
#define TARGET_CREAD 0000200
#define TARGET_PARENB 0000400
#define TARGET_PARODD 0001000
#define TARGET_HUPCL 0002000
#define TARGET_CLOCAL 0004000
#define TARGET_CBAUDEX 0010000
#define TARGET_B57600 0010001
#define TARGET_B115200 0010002
#define TARGET_B230400 0010003
#define TARGET_B460800 0010004
#define TARGET_B500000 0010005
#define TARGET_B576000 0010006
#define TARGET_B921600 0010007
#define TARGET_B1000000 0010010
#define TARGET_B1152000 0010011
#define TARGET_B1500000 0010012
#define TARGET_B2000000 0010013
#define TARGET_B2500000 0010014
#define TARGET_B3000000 0010015
#define TARGET_B3500000 0010016
#define TARGET_B4000000 0010017
#define TARGET_CIBAUD 002003600000 /* input baud rate (not used) */
#define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */
#define TARGET_CRTSCTS 020000000000 /* flow control */
/* c_lflag bits */
#define TARGET_ISIG 0000001
#define TARGET_ICANON 0000002
#define TARGET_XCASE 0000004
#define TARGET_ECHO 0000010
#define TARGET_ECHOE 0000020
#define TARGET_ECHOK 0000040
#define TARGET_ECHONL 0000100
#define TARGET_NOFLSH 0000200
#define TARGET_TOSTOP 0000400
#define TARGET_ECHOCTL 0001000
#define TARGET_ECHOPRT 0002000
#define TARGET_ECHOKE 0004000
#define TARGET_FLUSHO 0010000
#define TARGET_PENDIN 0040000
#define TARGET_IEXTEN 0100000
/* tcflow() and TCXONC use these */
#define TARGET_TCOOFF 0
#define TARGET_TCOON 1
#define TARGET_TCIOFF 2
#define TARGET_TCION 3
/* tcflush() and TCFLSH use these */
#define TARGET_TCIFLUSH 0
#define TARGET_TCOFLUSH 1
#define TARGET_TCIOFLUSH 2
/* tcsetattr uses these */
#define TARGET_TCSANOW 0
#define TARGET_TCSADRAIN 1
#define TARGET_TARGET_TCSAFLUSH 2
/* ioctl */
#define TARGET_FIOCLEX TARGET_IO('f', 1)
#define TARGET_FIONCLEX TARGET_IO('f', 2)
#define TARGET_FIOASYNC TARGET_IOW('f', 125, int)
#define TARGET_FIONBIO TARGET_IOW('f', 126, int)
#define TARGET_FIONREAD TARGET_IOR('f', 127, int)
#define TARGET_TIOCINQ TARGET_FIONREAD
#define TARGET_FIOQSIZE TARGET_IOR('f', 128, loff_t)
#define TARGET_TCGETS 0x5401
#define TARGET_TCSETS 0x5402
#define TARGET_TCSETSW 0x5403
#define TARGET_TCSETSF 0x5404
#define TARGET_TCGETA TARGET_IOR('t', 23, struct termio)
#define TARGET_TIOCSWINSZ TARGET_IOW('t', 103, struct winsize)
#define TARGET_TIOCGWINSZ TARGET_IOR('t', 104, struct winsize)
#define TARGET_TIOCSTART TARGET_IO('t', 110) /* start output, like ^Q */
#define TARGET_TIOCSTOP TARGET_IO('t', 111) /* stop output, like ^S */
#define TARGET_TIOCOUTQ TARGET_IOR('t', 115, int) /* output queue size */
#define TARGET_TIOCSPGRP TARGET_IOW('t', 118, int)
#define TARGET_TIOCGPGRP TARGET_IOR('t', 119, int)
#define TARGET_TCSETA TARGET_IOW('t', 24, struct termio)
#define TARGET_TCSETAW TARGET_IOW('t', 25, struct termio)
#define TARGET_TCSETAF TARGET_IOW('t', 28, struct termio)
#define TARGET_TCSBRK TARGET_IO('t', 29)
#define TARGET_TCXONC TARGET_IO('t', 30)
#define TARGET_TCFLSH TARGET_IO('t', 31)
#define TARGET_TIOCSWINSZ TARGET_IOW('t', 103, struct winsize)
#define TARGET_TIOCGWINSZ TARGET_IOR('t', 104, struct winsize)
#define TARGET_TIOCSTART TARGET_IO('t', 110) /* start output, like ^Q */
#define TARGET_TIOCSTOP TARGET_IO('t', 111) /* stop output, like ^S */
#define TARGET_TIOCOUTQ TARGET_IOR('t', 115, int) /* output queue size */
#define TARGET_TIOCSPGRP TARGET_IOW('t', 118, int)
#define TARGET_TIOCGPGRP TARGET_IOR('t', 119, int)
#define TARGET_TIOCEXCL TARGET_IO('T', 12) /* 0x540C */
#define TARGET_TIOCNXCL TARGET_IO('T', 13) /* 0x540D */
#define TARGET_TIOCSCTTY TARGET_IO('T', 14) /* 0x540E */
#define TARGET_TIOCSTI TARGET_IOW('T', 18, char) /* 0x5412 */
#define TARGET_TIOCMGET TARGET_IOR('T', 21, unsigned int) /* 0x5415 */
#define TARGET_TIOCMBIS TARGET_IOW('T', 22, unsigned int) /* 0x5416 */
#define TARGET_TIOCMBIC TARGET_IOW('T', 23, unsigned int) /* 0x5417 */
#define TARGET_TIOCMSET TARGET_IOW('T', 24, unsigned int) /* 0x5418 */
#define TARGET_TIOCM_LE 0x001
#define TARGET_TIOCM_DTR 0x002
#define TARGET_TIOCM_RTS 0x004
#define TARGET_TIOCM_ST 0x008
#define TARGET_TIOCM_SR 0x010
#define TARGET_TIOCM_CTS 0x020
#define TARGET_TIOCM_CAR 0x040
#define TARGET_TIOCM_RNG 0x080
#define TARGET_TIOCM_DSR 0x100
#define TARGET_TIOCM_CD TARGET_TIOCM_CAR
#define TARGET_TIOCM_RI TARGET_TIOCM_RNG
#define TARGET_TIOCGSOFTCAR TARGET_IOR('T', 25, unsigned int) /* 0x5419 */
#define TARGET_TIOCSSOFTCAR TARGET_IOW('T', 26, unsigned int) /* 0x541A */
#define TARGET_TIOCLINUX TARGET_IOW('T', 28, char) /* 0x541C */
#define TARGET_TIOCCONS TARGET_IO('T', 29) /* 0x541D */
#define TARGET_TIOCGSERIAL TARGET_IOR('T', 30, int) /* 0x541E */
#define TARGET_TIOCSSERIAL TARGET_IOW('T', 31, int) /* 0x541F */
#define TARGET_TIOCPKT TARGET_IOW('T', 32, int) /* 0x5420 */
#define TARGET_TIOCPKT_DATA 0
#define TARGET_TIOCPKT_FLUSHREAD 1
#define TARGET_TIOCPKT_FLUSHWRITE 2
#define TARGET_TIOCPKT_STOP 4
#define TARGET_TIOCPKT_START 8
#define TARGET_TIOCPKT_NOSTOP 16
#define TARGET_TIOCPKT_DOSTOP 32
#define TARGET_TIOCNOTTY TARGET_IO('T', 34) /* 0x5422 */
#define TARGET_TIOCSETD TARGET_IOW('T', 35, int) /* 0x5423 */
#define TARGET_TIOCGETD TARGET_IOR('T', 36, int) /* 0x5424 */
#define TARGET_TCSBRKP TARGET_IOW('T', 37, int) /* 0x5425 */ /* Needed for POSIX tcse
ndbreak() */
#define TARGET_TIOCSBRK TARGET_IO('T', 39) /* 0x5427 */ /* BSD compatibility */
#define TARGET_TIOCCBRK TARGET_IO('T', 40) /* 0x5428 */ /* BSD compatibility */
#define TARGET_TIOCGSID TARGET_IOR('T', 41, pid_t) /* 0x5429 */ /* Return the session
ID of FD */
#define TARGET_TIOCGPTN TARGET_IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-m
ux device) */
#define TARGET_TIOCSPTLCK TARGET_IOW('T',0x31, int) /* Lock/unlock Pty */
#define TARGET_TIOCSERCONFIG TARGET_IO('T', 83) /* 0x5453 */
#define TARGET_TIOCSERGWILD TARGET_IOR('T', 84, int) /* 0x5454 */
#define TARGET_TIOCSERSWILD TARGET_IOW('T', 85, int) /* 0x5455 */
#define TARGET_TIOCGLCKTRMIOS 0x5456
#define TARGET_TIOCSLCKTRMIOS 0x5457
#define TARGET_TIOCSERGSTRUCT TARGET_IOR('T', 88, int) /* 0x5458 */ /* For d
ebugging only */
#define TARGET_TIOCSERGETLSR TARGET_IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line sta
tus register */
/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
#define TARGET_TIOCSERGETMULTI TARGET_IOR('T', 90, int) /* 0x545A
*/ /* Get multiport config */
#define TARGET_TIOCSERSETMULTI TARGET_IOW('T', 91, int) /* 0x545B
*/ /* Set multiport config */
#define TARGET_TIOCMIWAIT TARGET_IO('T', 92) /* 0x545C */ /* wait for a change on
serial input line(s) */
#define TARGET_TIOCGICOUNT TARGET_IOR('T', 93, int) /* 0x545D */ /* read
serial port inline interrupt counts */

5
linux-user/syscall.c
View File

@ -1618,6 +1618,11 @@ int do_fork(CPUState *env, unsigned int flags, unsigned long newsp)
for (i = 7; i < 32; i++)
new_env->gpr[i] = 0;
}
#elif defined(TARGET_SH4)
if (!newsp)
newsp = env->gregs[15];
new_env->gregs[15] = newsp;
/* XXXXX */
#else
#error unsupported target CPU
#endif

6
linux-user/syscall_defs.h
View File

@ -48,7 +48,7 @@
#define TARGET_IOC_NRBITS 8
#define TARGET_IOC_TYPEBITS 8
#if defined(TARGET_I386) || defined(TARGET_ARM)
#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SH4)
#define TARGET_IOC_SIZEBITS 14
#define TARGET_IOC_DIRBITS 2
@ -293,7 +293,7 @@ struct target_sigaction;
int do_sigaction(int sig, const struct target_sigaction *act,
struct target_sigaction *oact);
#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_PPC) || defined(TARGET_MIPS)
#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_PPC) || defined(TARGET_MIPS) || defined (TARGET_SH4)
#if defined(TARGET_SPARC)
#define TARGET_SA_NOCLDSTOP 8u
@ -863,7 +863,7 @@ struct target_winsize {
#define TARGET_MAP_NORESERVE 0x4000 /* don't check for reservations */
#endif
#if defined(TARGET_I386) || defined(TARGET_ARM)
#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SH4)
struct target_stat {
unsigned short st_dev;
unsigned short __pad1;

2096
sh4-dis.c Normal file
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File diff suppressed because it is too large Load Diff

4
softmmu_header.h
View File

@ -61,6 +61,8 @@
#define CPU_MEM_INDEX ((env->psrs) == 0)
#elif defined (TARGET_ARM)
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
#elif defined (TARGET_SH4)
#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
#else
#error unsupported CPU
#endif
@ -78,6 +80,8 @@
#define CPU_MEM_INDEX ((env->psrs) == 0)
#elif defined (TARGET_ARM)
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
#elif defined (TARGET_SH4)
#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
#else
#error unsupported CPU
#endif

138
target-sh4/cpu.h Normal file
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@ -0,0 +1,138 @@
/*
* SH4 emulation
*
* Copyright (c) 2005 Samuel Tardieu
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _CPU_SH4_H
#define _CPU_SH4_H
#include "config.h"
#define TARGET_LONG_BITS 32
#define TARGET_HAS_ICE 1
#include "cpu-defs.h"
#define TARGET_PAGE_BITS 12 /* 4k XXXXX */
#define SR_MD (1 << 30)
#define SR_RB (1 << 29)
#define SR_BL (1 << 28)
#define SR_FD (1 << 15)
#define SR_M (1 << 9)
#define SR_Q (1 << 8)
#define SR_S (1 << 1)
#define SR_T (1 << 0)
#define FPSCR_FR (1 << 21)
#define FPSCR_SZ (1 << 20)
#define FPSCR_PR (1 << 19)
#define FPSCR_DN (1 << 18)
#define DELAY_SLOT (1 << 0)
#define DELAY_SLOT_CONDITIONAL (1 << 1)
/* Those are used in contexts only */
#define BRANCH (1 << 2)
#define BRANCH_CONDITIONAL (1 << 3)
#define MODE_CHANGE (1 << 4) /* Potential MD|RB change */
#define BRANCH_EXCEPTION (1 << 5) /* Branch after exception */
/* XXXXX The structure could be made more compact */
typedef struct tlb_t {
uint8_t asid; /* address space identifier */
uint32_t vpn; /* virtual page number */
uint8_t v; /* validity */
uint32_t ppn; /* physical page number */
uint8_t sz; /* page size */
uint32_t size; /* cached page size in bytes */
uint8_t sh; /* share status */
uint8_t c; /* cacheability */
uint8_t pr; /* protection key */
uint8_t d; /* dirty */
uint8_t wt; /* write through */
uint8_t sa; /* space attribute (PCMCIA) */
uint8_t tc; /* timing control */
} tlb_t;
#define UTLB_SIZE 64
#define ITLB_SIZE 4
typedef struct CPUSH4State {
uint32_t flags; /* general execution flags */
uint32_t gregs[24]; /* general registers */
uint32_t fregs[32]; /* floating point registers */
uint32_t sr; /* status register */
uint32_t ssr; /* saved status register */
uint32_t spc; /* saved program counter */
uint32_t gbr; /* global base register */
uint32_t vbr; /* vector base register */
uint32_t sgr; /* saved global register 15 */
uint32_t dbr; /* debug base register */
uint32_t pc; /* program counter */
uint32_t delayed_pc; /* target of delayed jump */
uint32_t mach; /* multiply and accumulate high */
uint32_t macl; /* multiply and accumulate low */
uint32_t pr; /* procedure register */
uint32_t fpscr; /* floating point status/control register */
uint32_t fpul; /* floating point communication register */
/* Those belong to the specific unit (SH7750) but are handled here */
uint32_t mmucr; /* MMU control register */
uint32_t pteh; /* page table entry high register */
uint32_t ptel; /* page table entry low register */
uint32_t ptea; /* page table entry assistance register */
uint32_t ttb; /* tranlation table base register */
uint32_t tea; /* TLB exception address register */
uint32_t tra; /* TRAPA exception register */
uint32_t expevt; /* exception event register */
uint32_t intevt; /* interrupt event register */
jmp_buf jmp_env;
int user_mode_only;
int interrupt_request;
int exception_index;
CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
} CPUSH4State;
CPUSH4State *cpu_sh4_init(void);
int cpu_sh4_exec(CPUSH4State * s);
struct siginfo;
int cpu_sh4_signal_handler(int hostsignum, struct siginfo *info,
void *puc);
#include "softfloat.h"
#include "cpu-all.h"
/* Memory access type */
enum {
/* Privilege */
ACCESS_PRIV = 0x01,
/* Direction */
ACCESS_WRITE = 0x02,
/* Type of instruction */
ACCESS_CODE = 0x10,
ACCESS_INT = 0x20
};
/* MMU control register */
#define MMUCR 0x1F000010
#define MMUCR_AT (1<<0)
#define MMUCR_SV (1<<8)
#endif /* _CPU_SH4_H */

75
target-sh4/exec.h Normal file
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@ -0,0 +1,75 @@
/*
* SH4 emulation
*
* Copyright (c) 2005 Samuel Tardieu
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _EXEC_SH4_H
#define _EXEC_SH4_H
#include "config.h"
#include "dyngen-exec.h"
register struct CPUSH4State *env asm(AREG0);
register uint32_t T0 asm(AREG1);
register uint32_t T1 asm(AREG2);
register uint32_t T2 asm(AREG3);
#include "cpu.h"
#include "exec-all.h"
#ifndef CONFIG_USER_ONLY
#include "softmmu_exec.h"
#endif
#define RETURN() __asm__ __volatile__("")
static inline void regs_to_env(void)
{
/* XXXXX */
}
static inline void env_to_regs(void)
{
/* XXXXX */
}
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
int is_user, int is_softmmu);
int find_itlb_entry(CPUState * env, target_ulong address,
int use_asid, int update);
int find_utlb_entry(CPUState * env, target_ulong address, int use_asid);
void helper_addc_T0_T1(void);
void helper_addv_T0_T1(void);
void helper_div1_T0_T1(void);
void helper_dmulsl_T0_T1(void);
void helper_dmulul_T0_T1(void);
void helper_macl_T0_T1(void);
void helper_macw_T0_T1(void);
void helper_negc_T0(void);
void helper_subc_T0_T1(void);
void helper_subv_T0_T1(void);
void helper_rotcl(uint32_t * addr);
void helper_rotcr(uint32_t * addr);
void do_interrupt(CPUState * env);
void cpu_loop_exit(void);
void do_raise_exception(void);
#endif /* _EXEC_SH4_H */

398
target-sh4/helper.c Normal file
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@ -0,0 +1,398 @@
/*
* SH4 emulation
*
* Copyright (c) 2005 Samuel Tardieu
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>
#include "cpu.h"
#include "exec-all.h"
#define MMU_OK 0
#define MMU_ITLB_MISS (-1)
#define MMU_ITLB_MULTIPLE (-2)
#define MMU_ITLB_VIOLATION (-3)
#define MMU_DTLB_MISS_READ (-4)
#define MMU_DTLB_MISS_WRITE (-5)
#define MMU_DTLB_INITIAL_WRITE (-6)
#define MMU_DTLB_VIOLATION_READ (-7)
#define MMU_DTLB_VIOLATION_WRITE (-8)
#define MMU_DTLB_MULTIPLE (-9)
#define MMU_DTLB_MISS (-10)
void do_interrupt(CPUState * env)
{
if (loglevel & CPU_LOG_INT) {
const char *expname;
switch (env->exception_index) {
case 0x0e0:
expname = "addr_error";
break;
case 0x040:
expname = "tlb_miss";
break;
case 0x0a0:
expname = "tlb_violation";
break;
case 0x180:
expname = "illegal_instruction";
break;
case 0x1a0:
expname = "slot_illegal_instruction";
break;
case 0x800:
expname = "fpu_disable";
break;
case 0x820:
expname = "slot_fpu";
break;
case 0x100:
expname = "data_write";
break;
case 0x060:
expname = "dtlb_miss_write";
break;
case 0x0c0:
expname = "dtlb_violation_write";
break;
case 0x120:
expname = "fpu_exception";
break;
case 0x080:
expname = "initial_page_write";
break;
case 0x160:
expname = "trapa";
break;
default:
expname = "???";
break;
}
fprintf(logfile, "exception 0x%03x [%s] raised\n",
env->exception_index, expname);
cpu_dump_state(env, logfile, fprintf, 0);
}
env->ssr = env->sr;
env->spc = env->spc;
env->sgr = env->gregs[15];
env->sr |= SR_BL | SR_MD | SR_RB;
env->expevt = env->exception_index & 0x7ff;
switch (env->exception_index) {
case 0x040:
case 0x060:
case 0x080:
env->pc = env->vbr + 0x400;
break;
case 0x140:
env->pc = 0xa0000000;
break;
default:
env->pc = env->vbr + 0x100;
break;
}
}
static void update_itlb_use(CPUState * env, int itlbnb)
{
uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
switch (itlbnb) {
case 0:
and_mask = 0x7f;
break;
case 1:
and_mask = 0xe7;
or_mask = 0x80;
break;
case 2:
and_mask = 0xfb;
or_mask = 0x50;
break;
case 3:
or_mask = 0x2c;
break;
}
env->mmucr &= (and_mask << 24);
env->mmucr |= (or_mask << 24);
}
static int itlb_replacement(CPUState * env)
{
if ((env->mmucr & 0xe0000000) == 0xe0000000)
return 0;
if ((env->mmucr & 0x98000000) == 0x08000000)
return 1;
if ((env->mmucr & 0x54000000) == 0x04000000)
return 2;
if ((env->mmucr & 0x2c000000) == 0x00000000)
return 3;
assert(0);
}
/* Find the corresponding entry in the right TLB
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
static int find_tlb_entry(CPUState * env, target_ulong address,
tlb_t * entries, uint8_t nbtlb, int use_asid)
{
int match = MMU_DTLB_MISS;
uint32_t start, end;
uint8_t asid;
int i;
asid = env->pteh & 0xff;
for (i = 0; i < nbtlb; i++) {
if (!entries[i].v)
continue; /* Invalid entry */
if (use_asid && entries[i].asid != asid && !entries[i].sh)
continue; /* Bad ASID */
#if 0
switch (entries[i].sz) {
case 0:
size = 1024; /* 1kB */
break;
case 1:
size = 4 * 1024; /* 4kB */
break;
case 2:
size = 64 * 1024; /* 64kB */
break;
case 3:
size = 1024 * 1024; /* 1MB */
break;
default:
assert(0);
}
#endif
start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
end = start + entries[i].size - 1;
if (address >= start && address <= end) { /* Match */
if (match != -1)
return MMU_DTLB_MULTIPLE; /* Multiple match */
match = i;
}
}
return match;
}
/* Find itlb entry - update itlb from utlb if necessary and asked for
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
Update the itlb from utlb if update is not 0
*/
int find_itlb_entry(CPUState * env, target_ulong address,
int use_asid, int update)
{
int e, n;
e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
if (e == MMU_DTLB_MULTIPLE)
e = MMU_ITLB_MULTIPLE;
else if (e == MMU_DTLB_MISS && update) {
e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
if (e >= 0) {
n = itlb_replacement(env);
env->itlb[n] = env->utlb[e];
e = n;
}
}
if (e >= 0)
update_itlb_use(env, e);
return e;
}
/* Find utlb entry
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
{
uint8_t urb, urc;
/* Increment URC */
urb = ((env->mmucr) >> 18) & 0x3f;
urc = ((env->mmucr) >> 10) & 0x3f;
urc++;
if (urc == urb || urc == UTLB_SIZE - 1)
urc = 0;
env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
/* Return entry */
return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
}
/* Match address against MMU
Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
*/
static int get_mmu_address(CPUState * env, target_ulong * physical,
int *prot, target_ulong address,
int rw, int access_type)
{
int use_asid, is_code, n;
tlb_t *matching = NULL;
use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
is_code = env->pc == address; /* Hack */
/* Use a hack to find if this is an instruction or data access */
if (env->pc == address && !(rw & PAGE_WRITE)) {
n = find_itlb_entry(env, address, use_asid, 1);
if (n >= 0) {
matching = &env->itlb[n];
if ((env->sr & SR_MD) & !(matching->pr & 2))
n = MMU_ITLB_VIOLATION;
else
*prot = PAGE_READ;
}
} else {
n = find_utlb_entry(env, address, use_asid);
if (n >= 0) {
matching = &env->utlb[n];
switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
case 0: /* 000 */
case 2: /* 010 */
n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
MMU_DTLB_VIOLATION_READ;
break;
case 1: /* 001 */
case 4: /* 100 */
case 5: /* 101 */
if (rw & PAGE_WRITE)
n = MMU_DTLB_VIOLATION_WRITE;
else
*prot = PAGE_READ;
break;
case 3: /* 011 */
case 6: /* 110 */
case 7: /* 111 */
*prot = rw & (PAGE_READ | PAGE_WRITE);
break;
}
} else if (n == MMU_DTLB_MISS) {
n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
MMU_DTLB_MISS_READ;
}
}
if (n >= 0) {
*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
(address & (matching->size - 1));
if ((rw & PAGE_WRITE) & !matching->d)
n = MMU_DTLB_INITIAL_WRITE;
else
n = MMU_OK;
}
return n;
}
int get_physical_address(CPUState * env, target_ulong * physical,
int *prot, target_ulong address,
int rw, int access_type)
{
/* P1, P2 and P4 areas do not use translation */
if ((address >= 0x80000000 && address < 0xc0000000) ||
address >= 0xe0000000) {
if (!(env->sr & SR_MD)
&& (address < 0xe0000000 || address > 0xe4000000)) {
/* Unauthorized access in user mode (only store queues are available) */
fprintf(stderr, "Unauthorized access\n");
return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
MMU_DTLB_MISS_READ;
}
/* Mask upper 3 bits */
*physical = address & 0x1FFFFFFF;
*prot = PAGE_READ | PAGE_WRITE;
return MMU_OK;
}
/* If MMU is disabled, return the corresponding physical page */
if (!env->mmucr & MMUCR_AT) {
*physical = address & 0x1FFFFFFF;
*prot = PAGE_READ | PAGE_WRITE;
return MMU_OK;
}
/* We need to resort to the MMU */
return get_mmu_address(env, physical, prot, address, rw, access_type);
}
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
int is_user, int is_softmmu)
{
target_ulong physical, page_offset, page_size;
int prot, ret, access_type;
/* XXXXX */
#if 0
fprintf(stderr, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
__func__, env->pc, address, rw, is_user, is_softmmu);
#endif
access_type = ACCESS_INT;
ret =
get_physical_address(env, &physical, &prot, address, rw,
access_type);
if (ret != MMU_OK) {
env->tea = address;
switch (ret) {
case MMU_ITLB_MISS:
case MMU_DTLB_MISS_READ:
env->exception_index = 0x040;
break;
case MMU_DTLB_MULTIPLE:
case MMU_ITLB_MULTIPLE:
env->exception_index = 0x140;
break;
case MMU_ITLB_VIOLATION:
env->exception_index = 0x0a0;
break;
case MMU_DTLB_MISS_WRITE:
env->exception_index = 0x060;
break;
case MMU_DTLB_INITIAL_WRITE:
env->exception_index = 0x080;
break;
case MMU_DTLB_VIOLATION_READ:
env->exception_index = 0x0a0;
break;
case MMU_DTLB_VIOLATION_WRITE:
env->exception_index = 0x0c0;
break;
default:
assert(0);
}
return 1;
}
page_size = TARGET_PAGE_SIZE;
page_offset =
(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
address = (address & TARGET_PAGE_MASK) + page_offset;
physical = (physical & TARGET_PAGE_MASK) + page_offset;
return tlb_set_page(env, address, physical, prot, is_user, is_softmmu);
}

882
target-sh4/op.c Normal file
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@ -0,0 +1,882 @@
/*
* SH4 emulation
*
* Copyright (c) 2005 Samuel Tardieu
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "exec.h"
static inline void set_flag(uint32_t flag)
{
env->flags |= flag;
}
static inline void clr_flag(uint32_t flag)
{
env->flags &= ~flag;
}
static inline void set_t(void)
{
env->sr |= SR_T;
}
static inline void clr_t(void)
{
env->sr &= ~SR_T;
}
static inline void cond_t(int cond)
{
if (cond)
set_t();
else
clr_t();
}
void OPPROTO op_movl_imm_T0(void)
{
T0 = (uint32_t) PARAM1;
RETURN();
}
void OPPROTO op_movl_imm_T1(void)
{
T0 = (uint32_t) PARAM1;
RETURN();
}
void OPPROTO op_movl_imm_T2(void)
{
T0 = (uint32_t) PARAM1;
RETURN();
}
void OPPROTO op_cmp_eq_imm_T0(void)
{
cond_t((int32_t) T0 == (int32_t) PARAM1);
RETURN();
}
void OPPROTO op_cmd_eq_T0_T1(void)
{
cond_t(T0 == T1);
RETURN();
}
void OPPROTO op_cmd_hs_T0_T1(void)
{
cond_t((uint32_t) T0 <= (uint32_t) T1);
RETURN();
}
void OPPROTO op_cmd_ge_T0_T1(void)
{
cond_t((int32_t) T0 <= (int32_t) T1);
RETURN();
}
void OPPROTO op_cmd_hi_T0_T1(void)
{
cond_t((uint32_t) T0 < (uint32_t) T1);
RETURN();
}
void OPPROTO op_cmd_gt_T0_T1(void)
{
cond_t((int32_t) T0 < (int32_t) T1);
RETURN();
}
void OPPROTO op_not_T0(void)
{
T0 = ~T0;
RETURN();
}
void OPPROTO op_bf_s(void)
{
T2 = ~env->sr;
env->delayed_pc = PARAM1;
set_flag(DELAY_SLOT_CONDITIONAL);
RETURN();
}
void OPPROTO op_bt_s(void)
{
T2 = env->sr;
env->delayed_pc = PARAM1;
set_flag(DELAY_SLOT_CONDITIONAL);
RETURN();
}
void OPPROTO op_bra(void)
{
env->delayed_pc = PARAM1;
set_flag(DELAY_SLOT);
RETURN();
}
void OPPROTO op_braf_T0(void)
{
env->delayed_pc = PARAM1 + T0;
set_flag(DELAY_SLOT);
RETURN();
}
void OPPROTO op_bsr(void)
{
env->pr = PARAM1;
env->delayed_pc = PARAM2;
set_flag(DELAY_SLOT);
RETURN();
}
void OPPROTO op_bsrf_T0(void)
{
env->pr = PARAM1;
env->delayed_pc = PARAM1 + T0;
set_flag(DELAY_SLOT);
RETURN();
}
void OPPROTO op_jsr_T0(void)
{
env->pr = PARAM1;
env->delayed_pc = T0;
set_flag(DELAY_SLOT);
RETURN();
}
void OPPROTO op_rts(void)
{
env->delayed_pc = env->pr;
set_flag(DELAY_SLOT);
RETURN();
}
void OPPROTO op_clr_delay_slot(void)
{
clr_flag(DELAY_SLOT);
RETURN();
}
void OPPROTO op_clr_delay_slot_conditional(void)
{
clr_flag(DELAY_SLOT_CONDITIONAL);
RETURN();
}
void OPPROTO op_exit_tb(void)
{
EXIT_TB();
RETURN();
}
void OPPROTO op_addl_imm_T0(void)
{
T0 += PARAM1;
RETURN();
}
void OPPROTO op_addl_imm_T1(void)
{
T1 += PARAM1;
RETURN();
}
void OPPROTO op_clrmac(void)
{
env->mach = env->macl = 0;
RETURN();
}
void OPPROTO op_clrs(void)
{
env->sr &= ~SR_S;
RETURN();
}
void OPPROTO op_clrt(void)
{
env->sr &= ~SR_T;
RETURN();
}
void OPPROTO op_sets(void)
{
env->sr |= SR_S;
RETURN();
}
void OPPROTO op_sett(void)
{
env->sr |= SR_T;
RETURN();
}
void OPPROTO op_rte(void)
{
env->sr = env->ssr;
env->delayed_pc = env->spc;
set_flag(DELAY_SLOT);
RETURN();
}
void OPPROTO op_swapb_T0(void)
{
T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff);
RETURN();
}
void OPPROTO op_swapw_T0(void)
{
T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff);
RETURN();
}
void OPPROTO op_xtrct_T0_T1(void)
{
T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff);
RETURN();
}
void OPPROTO op_addc_T0_T1(void)
{
helper_addc_T0_T1();
RETURN();
}
void OPPROTO op_addv_T0_T1(void)
{
helper_addv_T0_T1();
RETURN();
}
void OPPROTO op_cmp_eq_T0_T1(void)
{
cond_t(T1 == T0);
RETURN();
}
void OPPROTO op_cmp_ge_T0_T1(void)
{
cond_t((int32_t) T1 >= (int32_t) T0);
RETURN();
}
void OPPROTO op_cmp_gt_T0_T1(void)
{
cond_t((int32_t) T1 > (int32_t) T0);
RETURN();
}
void OPPROTO op_cmp_hi_T0_T1(void)
{
cond_t((uint32_t) T1 > (uint32_t) T0);
RETURN();
}
void OPPROTO op_cmp_hs_T0_T1(void)
{
cond_t((uint32_t) T1 >= (uint32_t) T0);
RETURN();
}
void OPPROTO op_cmp_str_T0_T1(void)
{
cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) ||
(T0 & 0x0000ff00) == (T1 & 0x0000ff00) ||
(T0 & 0x00ff0000) == (T1 & 0x00ff0000) ||
(T0 & 0xff000000) == (T1 & 0xff000000));
RETURN();
}
void OPPROTO op_tst_T0_T1(void)
{
cond_t((T1 & T0) == 0);
RETURN();
}
void OPPROTO op_div0s_T0_T1(void)
{
if (T1 & 0x80000000)
env->sr |= SR_Q;
else
env->sr &= ~SR_Q;
if (T0 & 0x80000000)
env->sr |= SR_M;
else
env->sr &= ~SR_M;
cond_t((T1 ^ T0) & 0x80000000);
RETURN();
}
void OPPROTO op_div0u(void)
{
env->sr &= ~(SR_M | SR_Q | SR_T);
RETURN();
}
void OPPROTO op_div1_T0_T1(void)
{
helper_div1_T0_T1();
RETURN();
}
void OPPROTO op_dmulsl_T0_T1(void)
{
helper_dmulsl_T0_T1();
RETURN();
}
void OPPROTO op_dmulul_T0_T1(void)
{
helper_dmulul_T0_T1();
RETURN();
}
void OPPROTO op_macl_T0_T1(void)
{
helper_macl_T0_T1();
RETURN();
}
void OPPROTO op_macw_T0_T1(void)
{
helper_macw_T0_T1();
RETURN();
}
void OPPROTO op_mull_T0_T1(void)
{
env->macl = (T0 * T1) & 0xffffffff;
RETURN();
}
void OPPROTO op_mulsw_T0_T1(void)
{
env->macl = (int32_t) T0 *(int32_t) T1;
RETURN();
}
void OPPROTO op_muluw_T0_T1(void)
{
env->macl = (uint32_t) T0 *(uint32_t) T1;
RETURN();
}
void OPPROTO op_neg_T0(void)
{
T0 = -T0;
RETURN();
}
void OPPROTO op_negc_T0(void)
{
helper_negc_T0();
RETURN();
}
void OPPROTO op_shad_T0_T1(void)
{
if ((T0 & 0x80000000) == 0)
T1 <<= (T0 & 0x1f);
else if ((T0 & 0x1f) == 0)
T1 = 0;
else
T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1);
RETURN();
}
void OPPROTO op_shld_T0_T1(void)
{
if ((T0 & 0x80000000) == 0)
T1 <<= (T0 & 0x1f);
else if ((T0 & 0x1f) == 0)
T1 = 0;
else
T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1);
RETURN();
}
void OPPROTO op_subc_T0_T1(void)
{
helper_subc_T0_T1();
RETURN();
}
void OPPROTO op_subv_T0_T1(void)
{
helper_subv_T0_T1();
RETURN();
}
void OPPROTO op_trapa(void)
{
env->tra = PARAM1 * 2;
env->exception_index = 0x160;
do_raise_exception();
RETURN();
}
void OPPROTO op_cmp_pl_T0(void)
{
cond_t((int32_t) T0 > 0);
RETURN();
}
void OPPROTO op_cmp_pz_T0(void)
{
cond_t((int32_t) T0 >= 0);
RETURN();
}
void OPPROTO op_jmp_T0(void)
{
env->delayed_pc = T0;
set_flag(DELAY_SLOT);
RETURN();
}
void OPPROTO op_movl_rN_rN(void)
{
env->gregs[PARAM2] = env->gregs[PARAM1];
RETURN();
}
void OPPROTO op_ldcl_rMplus_rN_bank(void)
{
env->gregs[PARAM2] = env->gregs[PARAM1];
env->gregs[PARAM1] += 4;
RETURN();
}
#define LDSTOPS(target,load,store) \
void OPPROTO op_##load##_T0_##target (void) \
{ env ->target = T0; RETURN(); \
} \
void OPPROTO op_##store##_##target##_T0 (void) \
{ T0 = env->target; RETURN(); \
} \
LDSTOPS(sr, ldc, stc)
LDSTOPS(gbr, ldc, stc)
LDSTOPS(vbr, ldc, stc)
LDSTOPS(ssr, ldc, stc)
LDSTOPS(spc, ldc, stc)
LDSTOPS(sgr, ldc, stc)
LDSTOPS(dbr, ldc, stc)
LDSTOPS(mach, lds, sts)
LDSTOPS(macl, lds, sts)
LDSTOPS(pr, lds, sts)
void OPPROTO op_movt_rN(void)
{
env->gregs[PARAM1] = env->sr & SR_T;
RETURN();
}
void OPPROTO op_rotcl_Rn(void)
{
helper_rotcl(&env->gregs[PARAM1]);
RETURN();
}
void OPPROTO op_rotcr_Rn(void)
{
helper_rotcr(&env->gregs[PARAM1]);
RETURN();
}
void OPPROTO op_rotl_Rn(void)
{
cond_t(env->gregs[PARAM1] & 0x80000000);
env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
RETURN();
}
void OPPROTO op_rotr_Rn(void)
{
cond_t(env->gregs[PARAM1] & 1);
env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
((env->sr & SR_T) ? 0x80000000 : 0);
RETURN();
}
void OPPROTO op_shal_Rn(void)
{
cond_t(env->gregs[PARAM1] & 0x80000000);
env->gregs[PARAM1] <<= 1;
RETURN();
}
void OPPROTO op_shar_Rn(void)
{
cond_t(env->gregs[PARAM1] & 1);
*(int32_t *) & env->gregs[PARAM1] >>= 1;
RETURN();
}
void OPPROTO op_shlr_Rn(void)
{
cond_t(env->gregs[PARAM1] & 1);
*(uint32_t *) & env->gregs[PARAM1] >>= 1;
RETURN();
}
void OPPROTO op_shll2_Rn(void)
{
env->gregs[PARAM1] <<= 2;
RETURN();
}
void OPPROTO op_shll8_Rn(void)
{
env->gregs[PARAM1] <<= 8;
RETURN();
}
void OPPROTO op_shll16_Rn(void)
{
env->gregs[PARAM1] <<= 16;
RETURN();
}
void OPPROTO op_shlr2_Rn(void)
{
*(uint32_t *) & env->gregs[PARAM1] >>= 2;
RETURN();
}
void OPPROTO op_shlr8_Rn(void)
{
*(uint32_t *) & env->gregs[PARAM1] >>= 8;
RETURN();
}
void OPPROTO op_shlr16_Rn(void)
{
*(uint32_t *) & env->gregs[PARAM1] >>= 16;
RETURN();
}
void OPPROTO op_tasb_rN(void)
{
cond_t(*(int8_t *) env->gregs[PARAM1] == 0);
*(int8_t *) env->gregs[PARAM1] |= 0x80;
RETURN();
}
void OPPROTO op_movl_T0_rN(void)
{
env->gregs[PARAM1] = T0;
RETURN();
}
void OPPROTO op_movl_T1_rN(void)
{
env->gregs[PARAM1] = T1;
RETURN();
}
void OPPROTO op_movb_rN_T0(void)
{
T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
RETURN();
}
void OPPROTO op_movub_rN_T0(void)
{
T0 = env->gregs[PARAM1] & 0xff;
RETURN();
}
void OPPROTO op_movw_rN_T0(void)
{
T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
RETURN();
}
void OPPROTO op_movuw_rN_T0(void)
{
T0 = env->gregs[PARAM1] & 0xffff;
RETURN();
}
void OPPROTO op_movl_rN_T0(void)
{
T0 = env->gregs[PARAM1];
RETURN();
}
void OPPROTO op_movb_rN_T1(void)
{
T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
RETURN();
}
void OPPROTO op_movub_rN_T1(void)
{
T1 = env->gregs[PARAM1] & 0xff;
RETURN();
}
void OPPROTO op_movw_rN_T1(void)
{
T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
RETURN();
}
void OPPROTO op_movuw_rN_T1(void)
{
T1 = env->gregs[PARAM1] & 0xffff;
RETURN();
}
void OPPROTO op_movl_rN_T1(void)
{
T1 = env->gregs[PARAM1];
RETURN();
}
void OPPROTO op_movl_imm_rN(void)
{
env->gregs[PARAM2] = PARAM1;
RETURN();
}
void OPPROTO op_dec1_rN(void)
{
env->gregs[PARAM1] -= 1;
RETURN();
}
void OPPROTO op_dec2_rN(void)
{
env->gregs[PARAM1] -= 2;
RETURN();
}
void OPPROTO op_dec4_rN(void)
{
env->gregs[PARAM1] -= 4;
RETURN();
}
void OPPROTO op_inc1_rN(void)
{
env->gregs[PARAM1] += 1;
RETURN();
}
void OPPROTO op_inc2_rN(void)
{
env->gregs[PARAM1] += 2;
RETURN();
}
void OPPROTO op_inc4_rN(void)
{
env->gregs[PARAM1] += 4;
RETURN();
}
void OPPROTO op_add_T0_rN(void)
{
env->gregs[PARAM1] += T0;
RETURN();
}
void OPPROTO op_sub_T0_rN(void)
{
env->gregs[PARAM1] -= T0;
RETURN();
}
void OPPROTO op_and_T0_rN(void)
{
env->gregs[PARAM1] &= T0;
RETURN();
}
void OPPROTO op_or_T0_rN(void)
{
env->gregs[PARAM1] |= T0;
RETURN();
}
void OPPROTO op_xor_T0_rN(void)
{
env->gregs[PARAM1] ^= T0;
RETURN();
}
void OPPROTO op_add_rN_T0(void)
{
T0 += env->gregs[PARAM1];
RETURN();
}
void OPPROTO op_add_rN_T1(void)
{
T1 += env->gregs[PARAM1];
RETURN();
}
void OPPROTO op_add_imm_rN(void)
{
env->gregs[PARAM2] += PARAM1;
RETURN();
}
void OPPROTO op_and_imm_rN(void)
{
env->gregs[PARAM2] &= PARAM1;
RETURN();
}
void OPPROTO op_or_imm_rN(void)
{
env->gregs[PARAM2] |= PARAM1;
RETURN();
}
void OPPROTO op_xor_imm_rN(void)
{
env->gregs[PARAM2] ^= PARAM1;
RETURN();
}
void OPPROTO op_dt_rN(void)
{
cond_t((--env->gregs[PARAM1]) == 0);
RETURN();
}
void OPPROTO op_tst_imm_rN(void)
{
cond_t((env->gregs[PARAM2] & PARAM1) == 0);
RETURN();
}
void OPPROTO op_movl_T0_T1(void)
{
T1 = T0;
RETURN();
}
void OPPROTO op_goto_tb0(void)
{
GOTO_TB(op_goto_tb0, PARAM1, 0);
RETURN();
}
void OPPROTO op_goto_tb1(void)
{
GOTO_TB(op_goto_tb1, PARAM1, 1);
RETURN();
}
void OPPROTO op_movl_imm_PC(void)
{
env->pc = PARAM1;
RETURN();
}
void OPPROTO op_jT(void)
{
if (env->sr & SR_T)
GOTO_LABEL_PARAM(1);
RETURN();
}
void OPPROTO op_jTT2(void)
{
if (T2 & SR_T)
GOTO_LABEL_PARAM(1);
RETURN();
}
void OPPROTO op_movl_delayed_pc_PC(void)
{
env->pc = env->delayed_pc;
RETURN();
}
void OPPROTO op_addl_GBR_T0(void)
{
T0 += env->gbr;
RETURN();
}
void OPPROTO op_and_imm_T0(void)
{
T0 &= PARAM1;
RETURN();
}
void OPPROTO op_or_imm_T0(void)
{
T0 |= PARAM1;
RETURN();
}
void OPPROTO op_xor_imm_T0(void)
{
T0 ^= PARAM1;
RETURN();
}
void OPPROTO op_tst_imm_T0(void)
{
cond_t((T0 & PARAM1) == 0);
RETURN();
}
void OPPROTO op_raise_illegal_instruction(void)
{
env->exception_index = 0x180;
do_raise_exception();
RETURN();
}
void OPPROTO op_raise_slot_illegal_instruction(void)
{
env->exception_index = 0x1a0;
do_raise_exception();
RETURN();
}
void OPPROTO op_debug(void)
{
env->exception_index = EXCP_DEBUG;
cpu_loop_exit();
}
/* Load and store */
#define MEMSUFFIX _raw
#include "op_mem.c"
#undef MEMSUFFIX
#if !defined(CONFIG_USER_ONLY)
#define MEMSUFFIX _user
#include "op_mem.c"
#undef MEMSUFFIX
#define MEMSUFFIX _kernel
#include "op_mem.c"
#undef MEMSUFFIX
#endif

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/*
* SH4 emulation
*
* Copyright (c) 2005 Samuel Tardieu
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <assert.h>
#include "exec.h"
void cpu_loop_exit(void)
{
longjmp(env->jmp_env, 1);
}
void do_raise_exception(void)
{
cpu_loop_exit();
}
#ifndef CONFIG_USER_ONLY
#define MMUSUFFIX _mmu
#define GETPC() (__builtin_return_address(0))
#define SHIFT 0
#include "softmmu_template.h"
#define SHIFT 1
#include "softmmu_template.h"
#define SHIFT 2
#include "softmmu_template.h"
#define SHIFT 3
#include "softmmu_template.h"
void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
{
TranslationBlock *tb;
CPUState *saved_env;
unsigned long pc;
int ret;
/* XXX: hack to restore env in all cases, even if not called from
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, is_user, 1);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */
pc = (unsigned long) retaddr;
tb = tb_find_pc(pc);
if (tb) {
/* the PC is inside the translated code. It means that we have
a virtual CPU fault */
cpu_restore_state(tb, env, pc, NULL);
}
}
do_raise_exception();
}
env = saved_env;
}
#endif
void helper_addc_T0_T1(void)
{
uint32_t tmp0, tmp1;
tmp1 = T0 + T1;
tmp0 = T1;
T1 = tmp1 + (env->sr & 1);
if (tmp0 > tmp1)
env->sr |= SR_T;
else
env->sr &= ~SR_T;
if (tmp1 > T1)
env->sr |= SR_T;
}
void helper_addv_T0_T1(void)
{
uint32_t dest, src, ans;
if ((int32_t) T1 >= 0)
dest = 0;
else
dest = 1;
if ((int32_t) T0 >= 0)
src = 0;
else
src = 1;
src += dest;
T1 += T0;
if ((int32_t) T1 >= 0)
ans = 0;
else
ans = 1;
ans += dest;
if (src == 0 || src == 2) {
if (ans == 1)
env->sr |= SR_T;
else
env->sr &= ~SR_T;
} else
env->sr &= ~SR_T;
}
#define T (env->sr & SR_T)
#define Q (env->sr & SR_Q ? 1 : 0)
#define M (env->sr & SR_M ? 1 : 0)
#define SETT env->sr |= SR_T
#define CLRT env->sr &= ~SR_T
#define SETQ env->sr |= SR_Q
#define CLRQ env->sr &= ~SR_Q
#define SETM env->sr |= SR_M
#define CLRM env->sr &= ~SR_M
void helper_div1_T0_T1(void)
{
uint32_t tmp0, tmp2;
uint8_t old_q, tmp1 = 0xff;
printf("div1 T0=0x%08x T1=0x%08x M=%d Q=%d T=%d\n", T0, T1, M, Q, T);
old_q = Q;
if ((0x80000000 & T1) != 0)
SETQ;
else
CLRQ;
tmp2 = T0;
T1 <<= 1;
T1 |= T;
switch (old_q) {
case 0:
switch (M) {
case 0:
tmp0 = T1;
T1 -= tmp2;
tmp1 = T1 > tmp0;
switch (Q) {
case 0:
if (tmp1)
SETQ;
else
CLRQ;
break;
case 1:
if (tmp1 == 0)
SETQ;
else
CLRQ;
break;
}
break;
case 1:
tmp0 = T1;
T1 += tmp2;
tmp1 = T1 < tmp0;
switch (Q) {
case 0:
if (tmp1 == 0)
SETQ;
else
CLRQ;
break;
case 1:
if (tmp1)
SETQ;
else
CLRQ;
break;
}
break;
}
break;
case 1:
switch (M) {
case 0:
tmp0 = T1;
T1 += tmp2;
tmp1 = T1 < tmp0;
switch (Q) {
case 0:
if (tmp1)
SETQ;
else
CLRQ;
break;
case 1:
if (tmp1 == 0)
SETQ;
else
CLRQ;
break;
}
break;
case 1:
tmp0 = T1;
T1 -= tmp2;
tmp1 = T1 > tmp0;
switch (Q) {
case 0:
if (tmp1 == 0)
SETQ;
else
CLRQ;
break;
case 1:
if (tmp1)
SETQ;
else
CLRQ;
break;
}
break;
}
break;
}
if (Q == M)
SETT;
else
CLRT;
printf("Output: T1=0x%08x M=%d Q=%d T=%d\n", T1, M, Q, T);
}
void helper_dmulsl_T0_T1()
{
int64_t res;
res = (int64_t) (int32_t) T0 *(int64_t) (int32_t) T1;
env->mach = (res >> 32) & 0xffffffff;
env->macl = res & 0xffffffff;
}
void helper_dmulul_T0_T1()
{
uint64_t res;
res = (uint64_t) (uint32_t) T0 *(uint64_t) (uint32_t) T1;
env->mach = (res >> 32) & 0xffffffff;
env->macl = res & 0xffffffff;
}
void helper_macl_T0_T1()
{
int64_t res;
res = ((uint64_t) env->mach << 32) | env->macl;
res += (int64_t) (int32_t) T0 *(int64_t) (int32_t) T1;
env->mach = (res >> 32) & 0xffffffff;
env->macl = res & 0xffffffff;
if (env->sr & SR_S) {
if (res < 0)
env->mach |= 0xffff0000;
else
env->mach &= 0x00007fff;
}
}
void helper_macw_T0_T1()
{
int64_t res;
res = ((uint64_t) env->mach << 32) | env->macl;
res += (int64_t) (int16_t) T0 *(int64_t) (int16_t) T1;
env->mach = (res >> 32) & 0xffffffff;
env->macl = res & 0xffffffff;
if (env->sr & SR_S) {
if (res < -0x80000000) {
env->mach = 1;
env->macl = 0x80000000;
} else if (res > 0x000000007fffffff) {
env->mach = 1;
env->macl = 0x7fffffff;
}
}
}
void helper_negc_T0()
{
uint32_t temp;
temp = -T0;
T0 = temp - (env->sr & SR_T);
if (0 < temp)
env->sr |= SR_T;
else
env->sr &= ~SR_T;
if (temp < T0)
env->sr |= SR_T;
}
void helper_subc_T0_T1()
{
uint32_t tmp0, tmp1;
tmp1 = T1 - T0;
tmp0 = T1;
T1 = tmp1 - (env->sr & SR_T);
if (tmp0 < tmp1)
env->sr |= SR_T;
else
env->sr &= ~SR_T;
if (tmp1 < T1)
env->sr |= SR_T;
}
void helper_subv_T0_T1()
{
int32_t dest, src, ans;
if ((int32_t) T1 >= 0)
dest = 0;
else
dest = 1;
if ((int32_t) T0 >= 0)
src = 0;
else
src = 1;
src += dest;
T1 -= T0;
if ((int32_t) T1 >= 0)
ans = 0;
else
ans = 1;
ans += dest;
if (src == 1) {
if (ans == 1)
env->sr |= SR_T;
else
env->sr &= ~SR_T;
} else
env->sr &= ~SR_T;
}
void helper_rotcl(uint32_t * addr)
{
uint32_t new;
new = (*addr << 1) | (env->sr & SR_T);
if (*addr & 0x80000000)
env->sr |= SR_T;
else
env->sr &= ~SR_T;
*addr = new;
}
void helper_rotcr(uint32_t * addr)
{
uint32_t new;
new = (*addr >> 1) | ((env->sr & SR_T) ? 0x80000000 : 0);
if (*addr & 1)
env->sr |= SR_T;
else
env->sr &= ~SR_T;
*addr = new;
}

58
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/*
* SH4 emulation
*
* Copyright (c) 2005 Samuel Tardieu
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
void glue(op_ldb_T0_T0, MEMSUFFIX) (void) {
T0 = glue(ldsb, MEMSUFFIX) (T0);
RETURN();
}
void glue(op_ldub_T0_T0, MEMSUFFIX) (void) {
T0 = glue(ldub, MEMSUFFIX) (T0);
RETURN();
}
void glue(op_stb_T0_T1, MEMSUFFIX) (void) {
glue(stb, MEMSUFFIX) (T1, T0);
RETURN();
}
void glue(op_ldw_T0_T0, MEMSUFFIX) (void) {
T0 = glue(ldsw, MEMSUFFIX) (T0);
RETURN();
}
void glue(op_lduw_T0_T0, MEMSUFFIX) (void) {
T0 = glue(lduw, MEMSUFFIX) (T0);
RETURN();
}
void glue(op_stw_T0_T1, MEMSUFFIX) (void) {
glue(stw, MEMSUFFIX) (T1, T0);
RETURN();
}
void glue(op_ldl_T0_T0, MEMSUFFIX) (void) {
T0 = glue(ldl, MEMSUFFIX) (T0);
RETURN();
}
void glue(op_stl_T0_T1, MEMSUFFIX) (void) {
glue(stl, MEMSUFFIX) (T1, T0);
RETURN();
}

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