target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
Define svep based on the size of the predicates, not the primary vector registers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -297,7 +297,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
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/* Create the predicate vector type. */
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g_string_append_printf(s,
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"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
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reg_width / 8);
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pred_width / 8);
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/* Define the vector registers. */
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for (i = 0; i < 32; i++) {
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