apb: rename APB functions to use sabre prefix
As hinted in the comment at the top of the file, the naming convention for the APB types/QOM functions isn't correct. As a starting point we can at least rename the APB type and related functions to improve the readability of apb.c. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
This commit is contained in:
Mark Cave-Ayland
parent
90302adaba
commit
fe984c7d0c
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@ -70,7 +70,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#define NO_IRQ_REQUEST (MAX_IVEC + 1)
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static inline void pbm_set_request(APBState *s, unsigned int irq_num)
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static inline void sabre_set_request(APBState *s, unsigned int irq_num)
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{
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APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
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@ -78,14 +78,13 @@ static inline void pbm_set_request(APBState *s, unsigned int irq_num)
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qemu_set_irq(s->ivec_irqs[irq_num], 1);
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}
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static inline void pbm_check_irqs(APBState *s)
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static inline void sabre_check_irqs(APBState *s)
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{
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unsigned int i;
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/* Previous request is not acknowledged, resubmit */
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if (s->irq_request != NO_IRQ_REQUEST) {
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pbm_set_request(s, s->irq_request);
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sabre_set_request(s, s->irq_request);
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return;
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}
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/* no request pending */
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@ -95,7 +94,7 @@ static inline void pbm_check_irqs(APBState *s)
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for (i = 0; i < 32; i++) {
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if (s->pci_irq_in & (1ULL << i)) {
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if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
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pbm_set_request(s, i);
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sabre_set_request(s, i);
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return;
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}
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}
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@ -103,28 +102,28 @@ static inline void pbm_check_irqs(APBState *s)
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for (i = 32; i < 64; i++) {
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if (s->pci_irq_in & (1ULL << i)) {
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if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
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pbm_set_request(s, i);
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sabre_set_request(s, i);
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break;
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}
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}
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}
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}
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static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
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static inline void sabre_clear_request(APBState *s, unsigned int irq_num)
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{
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APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
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qemu_set_irq(s->ivec_irqs[irq_num], 0);
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s->irq_request = NO_IRQ_REQUEST;
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}
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static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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{
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IOMMUState *is = opaque;
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return &is->iommu_as;
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}
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static void apb_config_writel (void *opaque, hwaddr addr,
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static void sabre_config_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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APBState *s = opaque;
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@ -141,9 +140,9 @@ static void apb_config_writel (void *opaque, hwaddr addr,
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s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
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s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
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if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
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pbm_clear_request(s, ino);
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sabre_clear_request(s, ino);
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}
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pbm_check_irqs(s);
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sabre_check_irqs(s);
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}
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break;
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case 0x1000 ... 0x107f: /* OBIO interrupt control */
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@ -153,17 +152,17 @@ static void apb_config_writel (void *opaque, hwaddr addr,
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s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
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if ((s->irq_request == (ino | 0x20))
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&& !(val & ~PBM_PCI_IMR_MASK)) {
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pbm_clear_request(s, ino | 0x20);
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sabre_clear_request(s, ino | 0x20);
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}
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pbm_check_irqs(s);
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sabre_check_irqs(s);
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}
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break;
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case 0x1400 ... 0x14ff: /* PCI interrupt clear */
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if (addr & 4) {
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unsigned int ino = (addr & 0xff) >> 5;
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if ((s->irq_request / 4) == ino) {
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pbm_clear_request(s, s->irq_request);
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pbm_check_irqs(s);
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sabre_clear_request(s, s->irq_request);
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sabre_check_irqs(s);
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}
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}
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break;
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@ -171,8 +170,8 @@ static void apb_config_writel (void *opaque, hwaddr addr,
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if (addr & 4) {
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unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
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if (s->irq_request == ino) {
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pbm_clear_request(s, ino);
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pbm_check_irqs(s);
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sabre_clear_request(s, ino);
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sabre_check_irqs(s);
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}
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}
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break;
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@ -202,7 +201,7 @@ static void apb_config_writel (void *opaque, hwaddr addr,
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}
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}
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static uint64_t apb_config_readl (void *opaque,
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static uint64_t sabre_config_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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APBState *s = opaque;
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@ -258,14 +257,14 @@ static uint64_t apb_config_readl (void *opaque,
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return val;
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}
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static const MemoryRegionOps apb_config_ops = {
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.read = apb_config_readl,
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.write = apb_config_writel,
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static const MemoryRegionOps sabre_config_ops = {
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.read = sabre_config_read,
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.write = sabre_config_write,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void apb_pci_config_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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static void sabre_pci_config_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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APBState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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@ -274,8 +273,8 @@ static void apb_pci_config_write(void *opaque, hwaddr addr,
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pci_data_write(phb->bus, addr, val, size);
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}
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static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
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unsigned size)
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static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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uint32_t ret;
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APBState *s = opaque;
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@ -286,8 +285,8 @@ static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
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return ret;
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}
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/* The APB host has an IRQ line for each IRQ line of each slot. */
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static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
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/* The sabre host has an IRQ line for each IRQ line of each slot. */
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static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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/* Return the irq as swizzled by the PBM */
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return irq_num;
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@ -316,7 +315,7 @@ static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
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return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
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}
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static void pci_apb_set_irq(void *opaque, int irq_num, int level)
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static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
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{
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APBState *s = opaque;
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@ -326,7 +325,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
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if (level) {
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s->pci_irq_in |= 1ULL << irq_num;
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if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
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pbm_set_request(s, irq_num);
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sabre_set_request(s, irq_num);
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}
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} else {
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s->pci_irq_in &= ~(1ULL << irq_num);
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@ -338,7 +337,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
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s->pci_irq_in |= 1ULL << irq_num;
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if ((s->irq_request == NO_IRQ_REQUEST)
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&& (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
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pbm_set_request(s, irq_num);
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sabre_set_request(s, irq_num);
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}
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} else {
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s->pci_irq_in &= ~(1ULL << irq_num);
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@ -346,7 +345,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
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}
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}
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static void pci_pbm_reset(DeviceState *d)
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static void sabre_reset(DeviceState *d)
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{
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APBState *s = APB_DEVICE(d);
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PCIDevice *pci_dev;
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@ -379,12 +378,12 @@ static void pci_pbm_reset(DeviceState *d)
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}
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static const MemoryRegionOps pci_config_ops = {
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.read = apb_pci_config_read,
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.write = apb_pci_config_write,
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.read = sabre_pci_config_read,
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.write = sabre_pci_config_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void pci_pbm_realize(DeviceState *dev, Error **errp)
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static void sabre_realize(DeviceState *dev, Error **errp)
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{
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APBState *s = APB_DEVICE(dev);
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PCIHostState *phb = PCI_HOST_BRIDGE(dev);
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@ -403,17 +402,17 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp)
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&s->pci_mmio);
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phb->bus = pci_register_root_bus(dev, "pci",
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pci_apb_set_irq, pci_apb_map_irq, s,
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pci_sabre_set_irq, pci_sabre_map_irq, s,
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&s->pci_mmio,
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&s->pci_ioport,
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0, 32, TYPE_PCI_BUS);
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pci_create_simple(phb->bus, 0, "pbm-pci");
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/* APB IOMMU */
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/* IOMMU */
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memory_region_add_subregion_overlap(&s->apb_config, 0x200,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1);
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pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, s->iommu);
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pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
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/* APB secondary busses */
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
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@ -429,7 +428,7 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp)
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qdev_init_nofail(&pci_dev->qdev);
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}
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static void pci_pbm_init(Object *obj)
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static void sabre_init(Object *obj)
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{
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APBState *s = APB_DEVICE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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@ -444,7 +443,7 @@ static void pci_pbm_init(Object *obj)
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for (i = 0; i < 32; i++) {
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s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
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}
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qdev_init_gpio_in_named(DEVICE(s), pci_apb_set_irq, "pbm-irq", MAX_IVEC);
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qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC);
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qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC);
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s->irq_request = NO_IRQ_REQUEST;
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s->pci_irq_in = 0ULL;
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@ -456,7 +455,7 @@ static void pci_pbm_init(Object *obj)
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0, NULL);
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/* apb_config */
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memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s,
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memory_region_init_io(&s->apb_config, OBJECT(s), &sabre_config_ops, s,
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"apb-config", 0x10000);
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/* at region 0 */
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sysbus_init_mmio(sbd, &s->apb_config);
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@ -473,7 +472,7 @@ static void pci_pbm_init(Object *obj)
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sysbus_init_mmio(sbd, &s->pci_ioport);
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}
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static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
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static void sabre_pci_host_realize(PCIDevice *d, Error **errp)
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{
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pci_set_word(d->config + PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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@ -482,12 +481,12 @@ static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
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PCI_STATUS_DEVSEL_MEDIUM);
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}
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static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
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static void sabre_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = pbm_pci_host_realize;
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k->realize = sabre_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_SUN;
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k->device_id = PCI_DEVICE_ID_SUN_SABRE;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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@ -502,41 +501,41 @@ static const TypeInfo pbm_pci_host_info = {
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.name = "pbm-pci",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = pbm_pci_host_class_init,
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.class_init = sabre_pci_host_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static Property pbm_pci_host_properties[] = {
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static Property sabre_properties[] = {
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DEFINE_PROP_UINT64("special-base", APBState, special_base, 0),
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DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pbm_host_class_init(ObjectClass *klass, void *data)
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static void sabre_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = pci_pbm_realize;
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dc->reset = pci_pbm_reset;
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dc->props = pbm_pci_host_properties;
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dc->realize = sabre_realize;
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dc->reset = sabre_reset;
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dc->props = sabre_properties;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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}
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static const TypeInfo pbm_host_info = {
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static const TypeInfo sabre_info = {
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.name = TYPE_APB,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(APBState),
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.instance_init = pci_pbm_init,
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.class_init = pbm_host_class_init,
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.instance_init = sabre_init,
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.class_init = sabre_class_init,
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};
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static void pbm_register_types(void)
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static void sabre_register_types(void)
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{
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type_register_static(&pbm_host_info);
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type_register_static(&sabre_info);
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type_register_static(&pbm_pci_host_info);
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}
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type_init(pbm_register_types)
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type_init(sabre_register_types)
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@ -15,7 +15,6 @@
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#define OBIO_SER_IRQ 0x2b
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#define TYPE_APB "pbm"
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#define APB_DEVICE(obj) \
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OBJECT_CHECK(APBState, (obj), TYPE_APB)
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